Sometimes under load, the Blackfin core is able to send SPI register
updates out before the controller is actually disabled. So when we
go to reprogram the entire state (to switch to a different slave),
make sure we sync after disabling the controller.
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
bfin_spi_disable(drv_data);
dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
+ SSYNC();
+
/* Load the registers */
write_CTRL(drv_data, chip->ctl_reg);
write_BAUD(drv_data, chip->baud);