usb: chipidea: add tx/rx burst size configuration interface
authorPeter Chen <peter.chen@freescale.com>
Tue, 17 Mar 2015 09:32:45 +0000 (17:32 +0800)
committerPeter Chen <peter.chen@freescale.com>
Fri, 14 Aug 2015 02:03:58 +0000 (10:03 +0800)
The user can adjust it through dts or platform data

Signed-off-by: Peter Chen <peter.chen@freescale.com>
drivers/usb/chipidea/bits.h
drivers/usb/chipidea/ci.h
drivers/usb/chipidea/core.c
include/linux/usb/chipidea.h

index 462ad02167b8b5959c76710bc8d132f11095e947..e462f55c8b996a3c15af54160c80060d8db2c7b5 100644 (file)
 /* Set non-zero value for internal TT Hub address representation */
 #define TTCTRL_TTHA            (0x7fUL << 24)
 
+/* BURSTSIZE */
+#define RX_BURST_MASK          0xff
+#define TX_BURST_MASK          0xff00
+
 /* PORTSC */
 #define PORTSC_CCS            BIT(0)
 #define PORTSC_CSC            BIT(1)
index 1320a4dbbcd5a7ec9d160032b84e2613d36c6b33..62f2a7be06972ba62f1844d09d9b5cf8a6d9e179 100644 (file)
@@ -51,6 +51,7 @@ enum ci_hw_regs {
        OP_DEVICEADDR,
        OP_ENDPTLISTADDR,
        OP_TTCTRL,
+       OP_BURSTSIZE,
        OP_PORTSC,
        OP_DEVLC,
        OP_OTGSC,
index ce0489754fde015d279e5d05aeb8ac66bc048756..50cd23b3b7f12e3fd678f374ab875bc79eca344d 100644 (file)
@@ -86,6 +86,7 @@ static const u8 ci_regs_nolpm[] = {
        [OP_DEVICEADDR]         = 0x14U,
        [OP_ENDPTLISTADDR]      = 0x18U,
        [OP_TTCTRL]             = 0x1CU,
+       [OP_BURSTSIZE]          = 0x20U,
        [OP_PORTSC]             = 0x44U,
        [OP_DEVLC]              = 0x84U,
        [OP_OTGSC]              = 0x64U,
@@ -109,6 +110,7 @@ static const u8 ci_regs_lpm[] = {
        [OP_DEVICEADDR]         = 0x14U,
        [OP_ENDPTLISTADDR]      = 0x18U,
        [OP_TTCTRL]             = 0x1CU,
+       [OP_BURSTSIZE]          = 0x20U,
        [OP_PORTSC]             = 0x44U,
        [OP_DEVLC]              = 0x84U,
        [OP_OTGSC]              = 0xC4U,
@@ -441,6 +443,17 @@ void ci_platform_configure(struct ci_hdrc *ci)
        if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
                hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
                        ci->platdata->ahb_burst_config);
+
+       /* override burst size, take effect only when ahb_burst_config is 0 */
+       if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
+               if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
+                       hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
+                       ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
+
+               if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
+                       hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
+                               ci->platdata->rx_burst_size);
+       }
 }
 
 /**
@@ -647,6 +660,28 @@ static int ci_get_platdata(struct device *dev,
                platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
        }
 
+       if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) {
+               ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
+                       &platdata->tx_burst_size);
+               if (ret) {
+                       dev_err(dev,
+                               "failed to get tx-burst-size-dword\n");
+                       return ret;
+               }
+               platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
+       }
+
+       if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) {
+               ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
+                       &platdata->rx_burst_size);
+               if (ret) {
+                       dev_err(dev,
+                               "failed to get rx-burst-size-dword\n");
+                       return ret;
+               }
+               platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
+       }
+
        return 0;
 }
 
index cd7fcad4901709dca23c24dca9923f91a1b12cc2..575eaf0ebac1cafeb8335430a369643e5f3b48af 100644 (file)
@@ -34,6 +34,8 @@ struct ci_hdrc_platform_data {
 #define CI_HDRC_TURN_VBUS_EARLY_ON     BIT(7)
 #define CI_HDRC_SET_NON_ZERO_TTHA      BIT(8)
 #define CI_HDRC_OVERRIDE_AHB_BURST     BIT(9)
+#define CI_HDRC_OVERRIDE_TX_BURST      BIT(10)
+#define CI_HDRC_OVERRIDE_RX_BURST      BIT(11)
        enum usb_dr_mode        dr_mode;
 #define CI_HDRC_CONTROLLER_RESET_EVENT         0
 #define CI_HDRC_CONTROLLER_STOPPED_EVENT       1
@@ -43,6 +45,8 @@ struct ci_hdrc_platform_data {
        /* interrupt threshold setting */
        u32                     itc_setting;
        u32                     ahb_burst_config;
+       u32                     tx_burst_size;
+       u32                     rx_burst_size;
 };
 
 /* Default offset of capability registers */