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drm/i915: Gather all the power well->domain mappings to one place
authorImre Deak <imre.deak@intel.com>
Thu, 6 Jul 2017 14:40:40 +0000 (17:40 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 27 Jul 2017 07:38:54 +0000 (09:38 +0200)
Shuffle the power well->domain mapping macros around so they are at one
place in old->new GEN order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-19-git-send-email-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_runtime_pm.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3f24483071af4eca7cebc24ee1d9650d1cf8fdba..a709a686b978e83abf6e2bba6b940153edbb7502 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -422,172 +422,6 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
        return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 }
 
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
-       BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (         \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (             \
-       SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
-       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
-       BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (             \
-       BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
-       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_A_POWER_DOMAINS (                 \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS (                        \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
-       BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
-#define GLK_DPIO_CMN_A_POWER_DOMAINS (                 \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_B_POWER_DOMAINS (                 \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_C_POWER_DOMAINS (                 \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS (             \
-       GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
-       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
-       BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (           \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (              \
-       BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (             \
-       CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
-       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
-       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-
 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 {
        WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
@@ -1712,37 +1546,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        intel_runtime_pm_put(dev_priv);
 }
 
-#define HSW_DISPLAY_POWER_DOMAINS (                    \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
-       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
-       BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
-       BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
-       BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BDW_DISPLAY_POWER_DOMAINS (                    \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
-       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
-       BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
-       BIT_ULL(POWER_DOMAIN_VGA) |                             \
-       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+#define I830_PIPES_POWER_DOMAINS (             \
+       BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
+       BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
        BIT_ULL(POWER_DOMAIN_INIT))
 
 #define VLV_DISPLAY_POWER_DOMAINS (            \
@@ -1825,13 +1635,203 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        BIT_ULL(POWER_DOMAIN_AUX_D) |           \
        BIT_ULL(POWER_DOMAIN_INIT))
 
-#define I830_PIPES_POWER_DOMAINS (             \
-       BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
-       BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
-       BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
-       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
-       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
+#define HSW_DISPLAY_POWER_DOMAINS (                    \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+       BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
+       BIT_ULL(POWER_DOMAIN_VGA) |                             \
+       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BDW_DISPLAY_POWER_DOMAINS (                    \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
+       BIT_ULL(POWER_DOMAIN_VGA) |                             \
+       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_VGA) |                             \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (         \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (             \
+       SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
+       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_VGA) |                             \
+       BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (             \
+       BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
+       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DPIO_CMN_A_POWER_DOMAINS (                 \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DPIO_CMN_BC_POWER_DOMAINS (                        \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_VGA) |                             \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
+#define GLK_DPIO_CMN_A_POWER_DOMAINS (                 \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_B_POWER_DOMAINS (                 \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_C_POWER_DOMAINS (                 \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_A_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_B_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_C_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS (             \
+       GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
+       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+
+#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (                \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+       BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+       BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
+       BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+       BIT_ULL(POWER_DOMAIN_VGA) |                             \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (           \
+       BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (              \
+       BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
+       BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (             \
+       CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
+       BIT_ULL(POWER_DOMAIN_MODESET) |                 \
+       BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
        BIT_ULL(POWER_DOMAIN_INIT))
 
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {