mmc: sdhci-pltfm: add -pltfm driver for imx35/51
authorWolfram Sang <w.sang@pengutronix.de>
Fri, 15 Oct 2010 10:21:04 +0000 (12:21 +0200)
committerChris Ball <cjb@laptop.org>
Sat, 23 Oct 2010 13:11:22 +0000 (21:11 +0800)
This driver adds basic support for the esdhc-core found on e.g.
imx35/51, as a platform driver.

Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Tested-by: Eric BĂ©nard <eric@eukrea.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
drivers/mmc/host/Kconfig
drivers/mmc/host/Makefile
drivers/mmc/host/sdhci-esdhc-imx.c [new file with mode: 0644]
drivers/mmc/host/sdhci-pltfm.c
drivers/mmc/host/sdhci-pltfm.h

index 0b7024a4ffc28fb02209f94a303a9b262cd6e4c6..c9c2520a0c4a96a9d050263ff8990ce3aaf439d6 100644 (file)
@@ -130,6 +130,16 @@ config MMC_SDHCI_CNS3XXX
 
          If unsure, say N.
 
+config MMC_SDHCI_ESDHC_IMX
+       bool "SDHCI platform support for the Freescale eSDHC i.MX controller"
+       depends on MMC_SDHCI_PLTFM && (ARCH_MX25 || ARCH_MX35 || ARCH_MX5)
+       select MMC_SDHCI_IO_ACCESSORS
+       help
+         This selects the Freescale eSDHC controller support on the platform
+         bus, found on platforms like mx35/51.
+
+         If unsure, say N.
+
 config MMC_SDHCI_S3C
        tristate "SDHCI support on Samsung S3C SoC"
        depends on MMC_SDHCI && PLAT_SAMSUNG
index eae5d62711f77b9aaf40777ec506ad6801650c21..6c4ac67f739f04ae2ca59bf34d80f17191594e10 100644 (file)
@@ -37,6 +37,7 @@ obj-$(CONFIG_MMC_USHC)                += ushc.o
 obj-$(CONFIG_MMC_SDHCI_PLTFM)                  += sdhci-platform.o
 sdhci-platform-y                               := sdhci-pltfm.o
 sdhci-platform-$(CONFIG_MMC_SDHCI_CNS3XXX)     += sdhci-cns3xxx.o
+sdhci-platform-$(CONFIG_MMC_SDHCI_ESDHC_IMX)   += sdhci-esdhc-imx.o
 
 obj-$(CONFIG_MMC_SDHCI_OF)     += sdhci-of.o
 sdhci-of-y                             := sdhci-of-core.o
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
new file mode 100644 (file)
index 0000000..2e9cca1
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * Freescale eSDHC i.MX controller driver for the platform bus.
+ *
+ * derived from the OF-version.
+ *
+ * Copyright (c) 2010 Pengutronix e.K.
+ *   Author: Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdhci-pltfm.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+#include "sdhci-esdhc.h"
+
+static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
+{
+       void __iomem *base = host->ioaddr + (reg & ~0x3);
+       u32 shift = (reg & 0x3) * 8;
+
+       writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
+}
+
+static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
+{
+       if (unlikely(reg == SDHCI_HOST_VERSION))
+               reg ^= 2;
+
+       return readw(host->ioaddr + reg);
+}
+
+static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+       switch (reg) {
+       case SDHCI_TRANSFER_MODE:
+               /*
+                * Postpone this write, we must do it together with a
+                * command write that is down below.
+                */
+               pltfm_host->scratchpad = val;
+               return;
+       case SDHCI_COMMAND:
+               writel(val << 16 | pltfm_host->scratchpad,
+                       host->ioaddr + SDHCI_TRANSFER_MODE);
+               return;
+       case SDHCI_BLOCK_SIZE:
+               val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
+               break;
+       }
+       esdhc_clrset_le(host, 0xffff, val, reg);
+}
+
+static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
+{
+       u32 new_val;
+
+       switch (reg) {
+       case SDHCI_POWER_CONTROL:
+               /*
+                * FSL put some DMA bits here
+                * If your board has a regulator, code should be here
+                */
+               return;
+       case SDHCI_HOST_CONTROL:
+               /* FSL messed up here, so we can just keep those two */
+               new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
+               /* ensure the endianess */
+               new_val |= ESDHC_HOST_CONTROL_LE;
+               /* DMA mode bits are shifted */
+               new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
+
+               esdhc_clrset_le(host, 0xffff, new_val, reg);
+               return;
+       }
+       esdhc_clrset_le(host, 0xff, val, reg);
+}
+
+static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+       return clk_get_rate(pltfm_host->clk);
+}
+
+static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+       return clk_get_rate(pltfm_host->clk) / 256 / 16;
+}
+
+static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pdata)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+       struct clk *clk;
+
+       clk = clk_get(mmc_dev(host->mmc), NULL);
+       if (IS_ERR(clk)) {
+               dev_err(mmc_dev(host->mmc), "clk err\n");
+               return PTR_ERR(clk);
+       }
+       clk_enable(clk);
+       pltfm_host->clk = clk;
+
+       return 0;
+}
+
+static void esdhc_pltfm_exit(struct sdhci_host *host)
+{
+       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+       clk_disable(pltfm_host->clk);
+       clk_put(pltfm_host->clk);
+}
+
+static struct sdhci_ops sdhci_esdhc_ops = {
+       .read_w = esdhc_readw_le,
+       .write_w = esdhc_writew_le,
+       .write_b = esdhc_writeb_le,
+       .set_clock = esdhc_set_clock,
+       .get_max_clock = esdhc_pltfm_get_max_clock,
+       .get_min_clock = esdhc_pltfm_get_min_clock,
+};
+
+struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
+       .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_MULTIBLOCK
+                       | SDHCI_QUIRK_BROKEN_ADMA,
+       /* ADMA has issues. Might be fixable */
+       /* NO_MULTIBLOCK might be MX35 only (Errata: ENGcm07207) */
+       .ops = &sdhci_esdhc_ops,
+       .init = esdhc_pltfm_init,
+       .exit = esdhc_pltfm_exit,
+};
index 00e8a8ab638e629469688e4f66dc2ebd85832097..0502f89f662b3a8a5fe2173ef7f4052e71fbda05 100644 (file)
@@ -166,6 +166,9 @@ static const struct platform_device_id sdhci_pltfm_ids[] = {
        { "sdhci", },
 #ifdef CONFIG_MMC_SDHCI_CNS3XXX
        { "sdhci-cns3xxx", (kernel_ulong_t)&sdhci_cns3xxx_pdata },
+#endif
+#ifdef CONFIG_MMC_SDHCI_ESDHC_IMX
+       { "sdhci-esdhc-imx", (kernel_ulong_t)&sdhci_esdhc_imx_pdata },
 #endif
        { },
 };
index 562b92957f182951d55895f91e0a7fff793a732e..c1bfe48af56a2c5388e56574ec5df508c14de681 100644 (file)
@@ -21,5 +21,6 @@ struct sdhci_pltfm_host {
 };
 
 extern struct sdhci_pltfm_data sdhci_cns3xxx_pdata;
+extern struct sdhci_pltfm_data sdhci_esdhc_imx_pdata;
 
 #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */