ARM: S3C24XX: Add address map and clock definitions for HSMMC0
authorYauhen Kharuzhy <jekhor@gmail.com>
Thu, 6 Jan 2011 04:04:33 +0000 (13:04 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Thu, 6 Jan 2011 05:09:18 +0000 (14:09 +0900)
Define maps for HSMMC devices.

S3C2443 has one HSMMC device with base address 0x4A800000.
S3C2416 has HSMMC0 at 0x4AC00000 and HSMMC1 at 0x4A800000.

So suppose that S3C2443 has only HSMMC1.

Define clock for hsmmc0 device and register it.

Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-s3c2410/include/mach/irqs.h
arch/arm/mach-s3c2410/include/mach/map.h
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
arch/arm/mach-s3c2416/clock.c
arch/arm/mach-s3c2443/Kconfig
arch/arm/mach-s3c2443/clock.c
arch/arm/mach-s3c2443/mach-smdk2443.c
arch/arm/plat-s3c24xx/s3c2443-clock.c

index 11bb0f08fe6a8e010d50eed0f9e64732fbc9990b..e5a68ea131138637e715628eb2ab01cfd00dc115 100644 (file)
 
 #define IRQ_S3C2416_HSMMC0     S3C2410_IRQ(21)         /* S3C2416/S3C2450 */
 
-#define IRQ_HSMMC0             IRQ_S3C2443_HSMMC
-#define IRQ_HSMMC1             IRQ_S3C2416_HSMMC0
+#define IRQ_HSMMC0             IRQ_S3C2416_HSMMC0
+#define IRQ_HSMMC1             IRQ_S3C2443_HSMMC
 
 #define IRQ_S3C2443_LCD1       S3C2410_IRQSUB(14)
 #define IRQ_S3C2443_LCD2       S3C2410_IRQSUB(15)
index cd3983ad41604ee71234b2d14ce79e51563bad91..25bbf5a942dd004605c9d1455662101d98bccd7c 100644 (file)
 #define S3C_PA_IIC          S3C2410_PA_IIC
 #define S3C_PA_UART        S3C24XX_PA_UART
 #define S3C_PA_USBHOST S3C2410_PA_USBHOST
-#define S3C_PA_HSMMC0      S3C2443_PA_HSMMC
-#define S3C_PA_HSMMC1      S3C2416_PA_HSMMC0
+#define S3C_PA_HSMMC0      S3C2416_PA_HSMMC0
+#define S3C_PA_HSMMC1      S3C2443_PA_HSMMC
 #define S3C_PA_WDT         S3C2410_PA_WATCHDOG
 #define S3C_PA_NAND        S3C24XX_PA_NAND
 
index 101aeea22310026a164b0ce62be1a79284ac5101..44494a56e68b6e3c3fceee465b0311b7df3aae23 100644 (file)
@@ -86,6 +86,7 @@
 #define S3C2443_HCLKCON_LCDC           (1<<9)
 #define S3C2443_HCLKCON_USBH           (1<<11)
 #define S3C2443_HCLKCON_USBD           (1<<12)
+#define S3C2416_HCLKCON_HSMMC0         (1<<15)
 #define S3C2443_HCLKCON_HSMMC          (1<<16)
 #define S3C2443_HCLKCON_CFC            (1<<17)
 #define S3C2443_HCLKCON_SSMC           (1<<18)
index 7ccf5a2a2bfc34840c43cada10ac9da562aba62c..3b02d8506e25a37843cb4e11cbe3d76ae4467ee8 100644 (file)
@@ -38,12 +38,11 @@ static unsigned int armdiv[8] = {
        [7] = 8,
 };
 
-/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
 static struct clksrc_clk hsmmc_div[] = {
        [0] = {
                .clk = {
                        .name   = "hsmmc-div",
-                       .id     = 1,
+                       .id     = 0,
                        .parent = &clk_esysclk.clk,
                },
                .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -51,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
        [1] = {
                .clk = {
                        .name   = "hsmmc-div",
-                       .id     = 0,
+                       .id     = 1,
                        .parent = &clk_esysclk.clk,
                },
                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -61,7 +60,7 @@ static struct clksrc_clk hsmmc_div[] = {
 static struct clksrc_clk hsmmc_mux[] = {
        [0] = {
                .clk    = {
-                       .id     = 1,
+                       .id     = 0,
                        .name   = "hsmmc-if",
                        .ctrlbit = (1 << 6),
                        .enable = s3c2443_clkcon_enable_s,
@@ -77,7 +76,7 @@ static struct clksrc_clk hsmmc_mux[] = {
        },
        [1] = {
                .clk    = {
-                       .id     = 0,
+                       .id     = 1,
                        .name   = "hsmmc-if",
                        .ctrlbit = (1 << 12),
                        .enable = s3c2443_clkcon_enable_s,
@@ -93,6 +92,13 @@ static struct clksrc_clk hsmmc_mux[] = {
        },
 };
 
+static struct clk hsmmc0_clk = {
+       .name           = "hsmmc",
+       .id             = 0,
+       .parent         = &clk_h,
+       .enable         = s3c2443_clkcon_enable_h,
+       .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
+};
 
 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 {
@@ -130,6 +136,8 @@ void __init s3c2416_init_clocks(int xtal)
        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                s3c_register_clksrc(clksrcs[ptr], 1);
 
+       s3c24xx_register_clock(&hsmmc0_clk);
+
        s3c_pwmclk_init();
 
 }
index 31babec90cecc9b92ff4a08b00da33c8a8446833..8814031516ce2de3f15e5d7757b3579df5169763 100644 (file)
@@ -25,7 +25,7 @@ config MACH_SMDK2443
        bool "SMDK2443"
        select CPU_S3C2443
        select MACH_SMDK
-       select S3C_DEV_HSMMC
+       select S3C_DEV_HSMMC1
        help
          Say Y here if you are using an SMDK2443
 
index 0c3c0c884cd300b3c4b0a152309ddedba2be6c9f..f4ec6d5715c8956805de27b9673409e80f2183fc 100644 (file)
@@ -196,7 +196,7 @@ static struct clksrc_clk clk_hsspi = {
 static struct clksrc_clk clk_hsmmc_div = {
        .clk    = {
                .name           = "hsmmc-div",
-               .id             = -1,
+               .id             = 1,
                .parent         = &clk_esysclk.clk,
        },
        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +231,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
 
 static struct clk clk_hsmmc = {
        .name           = "hsmmc-if",
-       .id             = -1,
+       .id             = 1,
        .parent         = &clk_hsmmc_div.clk,
        .enable         = s3c2443_enable_hsmmc,
        .ops            = &(struct clk_ops) {
index 4337f0a9960d17eef0c6fbe413a95ea10f2c626b..d3b2922517e0cb83a8ac26175c0d94b9d1d5ecfd 100644 (file)
@@ -105,7 +105,7 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
 static struct platform_device *smdk2443_devices[] __initdata = {
        &s3c_device_wdt,
        &s3c_device_i2c0,
-       &s3c_device_hsmmc0,
+       &s3c_device_hsmmc1,
 #ifdef CONFIG_SND_SOC_SMDK2443_WM9710
        &s3c_device_ac97,
 #endif
index 461f070eb62d85190ed1edae36e82aba0c1d4aaf..82f2d4a3929159ffef96dc14204592fccff3ea70 100644 (file)
@@ -271,7 +271,7 @@ static struct clk init_clocks[] = {
                .ctrlbit        = S3C2443_HCLKCON_DMA5,
        }, {
                .name           = "hsmmc",
-               .id             = 0,
+               .id             = 1,
                .parent         = &clk_h,
                .enable         = s3c2443_clkcon_enable_h,
                .ctrlbit        = S3C2443_HCLKCON_HSMMC,