writel(cmd << 16 , devpriv->base_addr + reg);
}
-#define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
+static bool s626_mc_test(struct comedi_device *dev,
+ unsigned int cmd, unsigned int reg)
+{
+ struct s626_private *devpriv = dev->private;
+ unsigned int val;
+
+ val = readl(devpriv->base_addr + reg);
+
+ return (val & cmd) ? true : false;
+}
/* #define WR7146(REGARDS,CTRLWORD)
writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
/* Initiate upload of shadow RAM to DEBI control register */
s626_mc_enable(dev, MC2_UPLD_DEBI, P_MC2);
- /* Wait for completion of upload from shadow RAM to DEBI control */
- /* register. */
- while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
+ /*
+ * Wait for completion of upload from shadow RAM to
+ * DEBI control register.
+ */
+ while (!s626_mc_test(dev, MC2_UPLD_DEBI, P_MC2))
;
/* Wait until DEBI transfer is done. */
* wait for upload confirmation.
*/
s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
- while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
+ while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
;
/* Wait until I2C bus transfer is finished or an error occurs. */
s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
/* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
- while (MC_TEST(P_MC2, MC2_ADC_RPS))
+ while (s626_mc_test(dev, MC2_ADC_RPS, P_MC2))
;
/*
for (i = 0; i < 2; i++) {
WR7146(P_I2CSTAT, I2C_CLKSEL);
s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
- while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
+ while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
;
}