RX_FIFO_RESET_BIT = 0x4,
TX_ENABLE_BIT = 0x10,
RX_ENABLE_BIT = 0x20,
- DEMAND_DMA_DIRECTION_TX_BIT = 0x40, /* for channel 0, channel 1 can only transmit (when present) */
+ DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
+ /* for ch 0, ch 1 can only transmit (when present) */
LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
START_TX_BIT = 0x10,
CABLE_THROTTLE_ENABLE_BIT = 0x20,
bits |= PLX_DMA_EN_READYIN_BIT;
/* enable dma chaining */
bits |= PLX_EN_CHAIN_BIT;
- /* enable interrupt on dma done (probably don't need this, since chain never finishes) */
+ /* enable interrupt on dma done
+ * (probably don't need this, since chain never finishes) */
bits |= PLX_EN_DMA_DONE_INTR_BIT;
- /* don't increment local address during transfers (we are transferring from a fixed fifo register) */
+ /* don't increment local address during transfers
+ * (we are transferring from a fixed fifo register) */
bits |= PLX_LOCAL_ADDR_CONST_BIT;
/* route dma interrupt to pci bus */
bits |= PLX_DMA_INTR_PCI_BIT;
if (dev->irq)
free_irq(dev->irq, dev);
- if (priv(dev)) {
- if (priv(dev)->hw_dev) {
- if (priv(dev)->plx9080_iobase) {
- disable_plx_interrupts(dev);
- iounmap((void *)priv(dev)->plx9080_iobase);
- }
- if (priv(dev)->hpdi_iobase)
- iounmap((void *)priv(dev)->hpdi_iobase);
- /* free pci dma buffers */
- for (i = 0; i < NUM_DMA_BUFFERS; i++) {
- if (priv(dev)->dio_buffer[i])
- pci_free_consistent(priv(dev)->hw_dev,
- DMA_BUFFER_SIZE,
- priv(dev)->
- dio_buffer[i],
- priv
- (dev)->dio_buffer_phys_addr
- [i]);
- }
- /* free dma descriptors */
- if (priv(dev)->dma_desc)
+ if ((priv(dev)) && (priv(dev)->hw_dev)) {
+ if (priv(dev)->plx9080_iobase) {
+ disable_plx_interrupts(dev);
+ iounmap((void *)priv(dev)->plx9080_iobase);
+ }
+ if (priv(dev)->hpdi_iobase)
+ iounmap((void *)priv(dev)->hpdi_iobase);
+ /* free pci dma buffers */
+ for (i = 0; i < NUM_DMA_BUFFERS; i++) {
+ if (priv(dev)->dio_buffer[i])
pci_free_consistent(priv(dev)->hw_dev,
- sizeof(struct plx_dma_desc)
- * NUM_DMA_DESCRIPTORS,
- priv(dev)->dma_desc,
+ DMA_BUFFER_SIZE,
priv(dev)->
- dma_desc_phys_addr);
- if (priv(dev)->hpdi_phys_iobase) {
- comedi_pci_disable(priv(dev)->hw_dev);
- }
- pci_dev_put(priv(dev)->hw_dev);
+ dio_buffer[i],
+ priv
+ (dev)->dio_buffer_phys_addr
+ [i]);
}
+ /* free dma descriptors */
+ if (priv(dev)->dma_desc)
+ pci_free_consistent(priv(dev)->hw_dev,
+ sizeof(struct plx_dma_desc)
+ * NUM_DMA_DESCRIPTORS,
+ priv(dev)->dma_desc,
+ priv(dev)->
+ dma_desc_phys_addr);
+ if (priv(dev)->hpdi_phys_iobase)
+ comedi_pci_disable(priv(dev)->hw_dev);
+ pci_dev_put(priv(dev)->hw_dev);
}
return 0;
}
if (err)
return 4;
- if (cmd->chanlist) {
- for (i = 1; i < cmd->chanlist_len; i++) {
- if (CR_CHAN(cmd->chanlist[i]) != i) {
- /* XXX could support 8 channels or 16 channels */
- comedi_error(dev,
- "chanlist must be channels 0 to 31 in order");
- err++;
- break;
- }
+ if (!cmd->chanlist)
+ return 0;
+
+ for (i = 1; i < cmd->chanlist_len; i++) {
+ if (CR_CHAN(cmd->chanlist[i]) != i) {
+ /* XXX could support 8 or 16 channels */
+ comedi_error(dev,
+ "chanlist must be ch 0 to 31 in order");
+ err++;
+ break;
}
}
static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
struct comedi_cmd *cmd)
{
- if (priv(dev)->dio_config_output) {
+ if (priv(dev)->dio_config_output)
return -EINVAL;
- } else
+ else
return di_cmd_test(dev, s, cmd);
}
static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
{
- if (priv(dev)->dio_config_output) {
+ if (priv(dev)->dio_config_output)
return -EINVAL;
- } else
+ else
return di_cmd(dev, s);
}
uint8_t dma0_status, dma1_status;
unsigned long flags;
- if (!dev->attached) {
+ if (!dev->attached)
return IRQ_NONE;
- }
plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
- if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0) {
+ if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
return IRQ_NONE;
- }
hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
- if (dma0_status & PLX_DMA_EN_BIT) {
+ if (dma0_status & PLX_DMA_EN_BIT)
drain_dma_buffers(dev, 0);
- }
DEBUG_PRINT(" cleared dma ch0 interrupt\n");
}
spin_unlock_irqrestore(&dev->spinlock, flags);