# EXYNOS_ARM64_COMMON_CLK to avoid building them on ARMv7:
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
+config COMPOSITE_CLK_SAMSUNG
+ bool
+ default y
+ depends on ARCH_EXYNOS9 || ARCH_EXYNOS8 || ARCH_EXYNOS7
+
config EXYNOS_ARM64_COMMON_CLK
bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
depends on COMMON_CLK_SAMSUNG
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS9610) += clk-exynos9610.o
else
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
-obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
-obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
+ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
+ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
endif
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
struct init_vclk exynos9610_dispaud_hwacg_vclks[] __initdata = {
HWACG_VCLK(MUX_AUD_FM, MUX_CLK_AUD_FM, "MUX_AUD_FM", NULL, 0, 0, NULL),
- HWACG_VCLK(UMUX_CLKCMU_DISPAUD_BUS, MUX_CLKCMU_DISPAUD_DISP, "MUX_CLKCMU_DISPAUD_DISP", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DISPAUD_BUS, MUX_CLKCMU_DISPAUD_DISP_USER, "MUX_CLKCMU_DISPAUD_DISP_USER", NULL, 0, 0, NULL),
HWACG_VCLK(GATE_ABOX_QCH_CPU, ABOX_QCH_CPU, "GATE_ABOX_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_ABOX_QCH_S_ACLK, ABOX_QCH_S_ACLK, "GATE_ABOX_QCH_S_ACLK", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_ABOX_QCH_S_BCLK0, ABOX_QCH_S_BCLK0, "GATE_ABOX_QCH_S_BCLK0", NULL, 0, VCLK_GATE, NULL),
struct init_vclk exynos9610_peri_hwacg_vclks[] __initdata = {
HWACG_VCLK(UMUX_CLKCMU_PERI_UART, MUX_CLKCMU_PERI_UART_USER, "UMUX_CLKCMU_PERI_UART", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS_USER, "UMUX_CLKCMU_PERI_BUS", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_CAMI2C_0_QCH, CAMI2C_0_QCH, "GATE_CAMI2C_0_QCH", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_CAMI2C_1_QCH, CAMI2C_1_QCH, "GATE_CAMI2C_1_QCH", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_CAMI2C_2_QCH, CAMI2C_2_QCH, "GATE_CAMI2C_2_QCH", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_CAMI2C_3_QCH, CAMI2C_3_QCH, "GATE_CAMI2C_3_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_0_QCH, I2C_0_QCH, "GATE_I2C_0_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_1_QCH, I2C_1_QCH, "GATE_I2C_1_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_2_QCH, I2C_2_QCH, "GATE_I2C_2_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_3_QCH, I2C_3_QCH, "GATE_I2C_3_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_4_QCH, I2C_4_QCH, "GATE_I2C_4_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_5_QCH, I2C_5_QCH, "GATE_I2C_5_QCH", NULL, 0, VCLK_GATE, NULL),
- HWACG_VCLK(GATE_I2C_6_QCH, I2C_6_QCH, "GATE_I2C_6_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_0_QCH, I2C_0_QCH, "GATE_I2C_0_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_1_QCH, I2C_1_QCH, "GATE_I2C_1_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_2_QCH, I2C_2_QCH, "GATE_I2C_2_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_3_QCH, I2C_3_QCH, "GATE_I2C_3_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_4_QCH, I2C_4_QCH, "GATE_I2C_4_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_5_QCH, I2C_5_QCH, "GATE_I2C_5_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_6_QCH, I2C_6_QCH, "GATE_I2C_6_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_MCT_QCH, MCT_QCH, "GATE_MCT_QCH", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_OTP_CON_TOP_QCH, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP_QCH", NULL, 0, VCLK_GATE, NULL),
HWACG_VCLK(GATE_PWM_MOTOR_QCH, PWM_MOTOR_QCH, "GATE_PWM_MOTOR_QCH", NULL, 0, VCLK_GATE, NULL),
VCLK(DOUT_CLK_AUD_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_CLK_AUD_UAIF1", 0, 0, NULL),
VCLK(DOUT_CLK_AUD_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_AUD_UAIF2", 0, 0, NULL),
VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_FM, DIV_CLK_AUD_FM, "DOUT_CLK_AUD_FM", 0, 0, NULL),
};
struct init_vclk exynos9610_cmgp_vclks[] __initdata = {
struct init_vclk exynos9610_fsys_vclks[] __initdata = {
VCLK(MMC_EMBD, CLKCMU_FSYS_MMC_EMBD, "MMC_EMBD", 0, 0, NULL),
VCLK(MMC_CARD, CLKCMU_FSYS_MMC_CARD, "MMC_CARD", 0, 0, NULL),
- VCLK(UFS_EMBD, CLKCMU_FSYS_UFS_EMBD, "UFS_EMBD", 0, 0, NULL),
+ VCLK(UFS_EMBD, CLKCMU_FSYS_BUS, "UFS_EMBD", 0, 0, NULL),
};
struct init_vclk exynos9610_usb_vclks[] __initdata = {
VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
};
-#if 0
static __initdata struct of_device_id ext_clk_match[] = {
{.compatible = "samsung,exynos9610-oscclk", .data = (void *)0},
{},
};
-#endif
void exynos9610_vclk_init(void)
{
- /* Common clock init */
+ cal_clk_setrate(DIV_CLK_AUD_FM, 40000);
}
/* register exynos9610 clocks */
void __init exynos9610_clk_init(struct device_node *np)
{
-#if 0
void __iomem *reg_base;
int ret;
samsung_clk_of_add_provider(np, exynos9610_clk_provider);
late_time_init = exynos9610_vclk_init;
-#endif
+
pr_info("EXYNOS9610: Clock setup completed\n");
}
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions for composite clocks.
+ */
+
+#include <linux/syscore_ops.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <soc/samsung/cal-if.h>
+
+#include "composite.h"
+
+#define PLL_STAT_OSC (0x0)
+#define PLL_STAT_PLL (0x1)
+#define PLL_STAT_CHANGE (0x4)
+#define PLL_STAT_MASK (0x7)
+
+#define to_comp_pll(_hw) container_of(_hw, struct samsung_composite_pll, hw)
+#define to_comp_mux(_hw) container_of(_hw, struct samsung_composite_mux, hw)
+#define to_comp_divider(_hw) container_of(_hw, struct samsung_composite_divider, hw)
+#define to_usermux(_hw) container_of(_hw, struct clk_samsung_usermux, hw)
+#define to_vclk(_hw) container_of(_hw, struct samsung_vclk, hw)
+
+static DEFINE_SPINLOCK(lock);
+
+#ifdef CONFIG_PM_SLEEP
+void samsung_clk_save(void __iomem *base,
+ struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs)
+{
+ for (; num_regs > 0; --num_regs, ++rd)
+ rd->value = readl(base + rd->offset);
+}
+
+void samsung_clk_restore(void __iomem *base,
+ const struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs)
+{
+ for (; num_regs > 0; --num_regs, ++rd)
+ writel(rd->value, base + rd->offset);
+}
+
+struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
+ const unsigned long *rdump,
+ unsigned long nr_rdump)
+{
+ struct samsung_clk_reg_dump *rd;
+ unsigned int i;
+
+ rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
+ if (!rd)
+ return NULL;
+
+ for (i = 0; i < nr_rdump; ++i)
+ rd[i].offset = rdump[i];
+
+ return rd;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+/* setup the essentials required to support clock lookup using ccf */
+struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks)
+{
+ struct samsung_clk_provider *ctx = NULL;
+ struct clk **clk_table;
+ int i;
+
+ if (!np)
+ return ctx;
+
+ ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
+ if (!ctx)
+ panic("could not allocate clock provider context.\n");
+
+ clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_table)
+ panic("could not allocate clock lookup table\n");
+
+ for (i = 0; i < nr_clks; ++i)
+ clk_table[i] = ERR_PTR(-ENOENT);
+
+ ctx->reg_base = base;
+ ctx->clk_data.clks = clk_table;
+ ctx->clk_data.clk_num = nr_clks;
+ spin_lock_init(&ctx->lock);
+
+ return ctx;
+}
+
+void __init samsung_clk_of_add_provider(struct device_node *np,
+ struct samsung_clk_provider *ctx)
+{
+ if (np) {
+ if (of_clk_add_provider(np, of_clk_src_onecell_get,
+ &ctx->clk_data))
+ panic("could not register clk provider\n");
+ }
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+static void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
+ unsigned int id)
+{
+ if (ctx->clk_data.clks && id)
+ ctx->clk_data.clks[id] = clk;
+}
+
+/* register a list of fixed clocks */
+void __init samsung_register_fixed_rate(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_rate(NULL, list->name,
+ list->parent_name, list->flags, list->fixed_rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /*
+ * Unconditionally add a clock lookup for the fixed rate clocks.
+ * There are not many of these on any of Samsung platforms.
+ */
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/* register a list of fixed factor clocks */
+void __init samsung_register_fixed_factor(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_factor *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_factor(NULL, list->name,
+ list->parent_name, list->flags, list->mult, list->div);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/*
+ * obtain the clock speed of all external fixed clock sources from device
+ * tree and register it
+ */
+void __init samsung_register_of_fixed_ext(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ struct of_device_id *clk_matches)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ u32 freq;
+
+ for_each_matching_node_and_match(np, clk_matches, &match) {
+ if (of_property_read_u32(np, "clock-frequency", &freq))
+ continue;
+ fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
+ }
+ samsung_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
+}
+
+/* operation functions for pll clocks */
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_composite_pll *pll, unsigned long rate)
+{
+ const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ for (i = 0; i < pll->rate_count; i++) {
+ if (rate == rate_table[i].rate)
+ return &rate_table[i];
+ }
+
+ return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ /* Assumming rate_table is in descending order */
+ for (i = 0; i < pll->rate_count; i++) {
+ if (drate >= rate_table[i].rate)
+ return rate_table[i].rate;
+ }
+
+ /* return minimum supported value */
+ return rate_table[i - 1].rate;
+}
+
+static int samsung_composite_pll_is_enabled(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ reg = readl(pll->enable_reg);
+
+ return (((reg >> pll->enable_bit) & 1) == set) ? 1 : 0;
+}
+
+static int samsung_composite_pll_enable(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* Setting Enable register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg |= (1 << pll->enable_bit);
+ else
+ reg &= ~(1 << pll->enable_bit);
+ writel(reg, pll->enable_reg);
+
+ /* setting CTRL mux register to 1 */
+ reg = readl(pll->sel_reg);
+ reg |= (1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) != PLL_STAT_PLL);
+
+ return 0;
+}
+
+static void samsung_composite_pll_disable(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* setting CTRL mux register to 0 */
+ reg = readl(pll->sel_reg);
+ reg &= ~(1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) != PLL_STAT_OSC);
+
+ /* Setting Register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg &= ~(1 << pll->enable_bit);
+ else
+ reg |= (1 << pll->enable_bit);
+
+ writel(reg, pll->enable_reg);
+}
+
+static unsigned long samsung_pll145xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl(pll->con_reg);
+ mdiv = (pll_con >> PLL145XX_MDIV_SHIFT) & PLL145XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL145XX_PDIV_SHIFT) & PLL145XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL145XX_SDIV_SHIFT) & PLL145XX_SDIV_MASK;
+ /* Do calculation */
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll145xx_mp_check(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ return ((mdiv != ((pll_con >> PLL145XX_MDIV_SHIFT) & PLL145XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con >> PLL145XX_PDIV_SHIFT) & PLL145XX_PDIV_MASK)));
+}
+
+static int samsung_pll145xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 pll_con;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con = readl(pll->con_reg);
+ if (!(samsung_pll145xx_mp_check(rate->mdiv, rate->pdiv, pll_con))) {
+ if ((rate->sdiv) == ((pll_con >> PLL145XX_SDIV_SHIFT) & PLL145XX_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con &= ~(PLL145XX_SDIV_MASK << PLL145XX_SDIV_SHIFT);
+ pll_con |= rate->sdiv << PLL145XX_SDIV_SHIFT;
+ writel(pll_con, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL145XX_LOCK_FACTOR, pll->lock_reg);
+ /* Change PLL PMS values */
+ pll_con &= ~((PLL145XX_MDIV_MASK << PLL145XX_MDIV_SHIFT) |
+ (PLL145XX_PDIV_MASK << PLL145XX_PDIV_SHIFT) |
+ (PLL145XX_SDIV_MASK << PLL145XX_SDIV_SHIFT));
+ pll_con |= (rate->mdiv << PLL145XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL145XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL145XX_SDIV_SHIFT);
+ /* To prevent instable PLL operation, preset ENABLE bit with 0 */
+ pll_con &= ~BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con |= BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ do {
+ cpu_relax();
+ pll_con = readl(pll->con_reg);
+ } while (!(pll_con & (PLL145XX_LOCKED_MASK << PLL145XX_LOCKED_SHIFT)));
+
+ return 0;
+}
+
+
+static unsigned long samsung_pll1460x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL1460X_MDIV_SHIFT) & PLL1460X_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL1460X_PDIV_SHIFT) & PLL1460X_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL1460X_SDIV_SHIFT) & PLL1460X_SDIV_MASK;
+ kdiv = (s16)((pll_con1 >> PLL1460X_KDIV_SHIFT) & PLL1460X_KDIV_MASK);
+ /* Do calculation */
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll1460x_mpk_check(u32 mdiv, u32 pdiv, u32 kdiv, u32 pll_con0, u32 pll_con1)
+{
+ return ((mdiv != ((pll_con0 >> PLL1460X_MDIV_SHIFT) & PLL1460X_MDIV_MASK)) ||
+ (pdiv != ((pll_con0 >> PLL1460X_PDIV_SHIFT) & PLL1460X_PDIV_MASK)) ||
+ (kdiv != ((pll_con1 >> PLL1460X_KDIV_SHIFT) & PLL1460X_KDIV_MASK)));
+}
+
+static int samsung_pll1460x_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ if (!(samsung_pll1460x_mpk_check(rate->mdiv, rate->pdiv, rate->kdiv, pll_con0, pll_con1))) {
+ if ((rate->sdiv) == ((pll_con0 >> PLL1460X_SDIV_SHIFT) & PLL1460X_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con0 &= ~(PLL1460X_SDIV_MASK << PLL1460X_SDIV_SHIFT);
+ pll_con0 |= (rate->sdiv << PLL1460X_SDIV_SHIFT);
+ writel(pll_con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL1460X_LOCK_FACTOR, pll->lock_reg);
+
+ pll_con1 &= ~(PLL1460X_KDIV_MASK << PLL1460X_KDIV_SHIFT);
+ pll_con1 |= (rate->kdiv << PLL1460X_KDIV_SHIFT);
+ writel(pll_con1, pll->con_reg + 4);
+
+ pll_con0 &= ~((PLL1460X_MDIV_MASK << PLL1460X_MDIV_SHIFT) |
+ (PLL1460X_PDIV_MASK << PLL1460X_PDIV_SHIFT) |
+ (PLL1460X_SDIV_MASK << PLL1460X_SDIV_SHIFT));
+ pll_con0 |= (rate->mdiv << PLL1460X_MDIV_SHIFT) |
+ (rate->pdiv << PLL1460X_PDIV_SHIFT) |
+ (rate->sdiv << PLL1460X_SDIV_SHIFT);
+ /* To prevent instable PLL operation, preset ENABLE bit with 0 */
+ pll_con0 &= ~BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con0 |= BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /* Wait lock time */
+ do {
+ cpu_relax();
+ pll_con0 = readl(pll->con_reg);
+ } while (!(pll_con0 & (PLL1460X_LOCKED_MASK << PLL1460X_LOCKED_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll145xx_clk_ops = {
+ .recalc_rate = samsung_pll145xx_recalc_rate,
+ .set_rate = samsung_pll145xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable,
+ .disable = samsung_composite_pll_disable,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+static const struct clk_ops samsung_pll1460x_clk_ops = {
+ .recalc_rate = samsung_pll1460x_recalc_rate,
+ .set_rate = samsung_pll1460x_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable,
+ .disable = samsung_composite_pll_disable,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+static int samsung_composite_pll_enable_onchange(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* Setting Enable register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg |= (1 << pll->enable_bit);
+ else
+ reg &= ~(1 << pll->enable_bit);
+ writel(reg, pll->enable_reg);
+
+ /* setting CTRL mux register to 1 */
+ reg = readl(pll->sel_reg);
+ reg |= (1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) == PLL_STAT_CHANGE);
+
+ return 0;
+}
+
+static void samsung_composite_pll_disable_onchange(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* setting CTRL mux register to 0 */
+ reg = readl(pll->sel_reg);
+ reg &= ~(1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) == PLL_STAT_CHANGE);
+
+ /* Setting Register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg &= ~(1 << pll->enable_bit);
+ else
+ reg |= (1 << pll->enable_bit);
+
+ writel(reg, pll->enable_reg);
+}
+
+static unsigned long samsung_pll255xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl(pll->con_reg);
+ mdiv = (pll_con >> PLL255XX_MDIV_SHIFT) & PLL255XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL255XX_PDIV_SHIFT) & PLL255XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL255XX_SDIV_SHIFT) & PLL255XX_SDIV_MASK;
+ /* Do calculation */
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll255xx_mp_check(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ return ((mdiv != ((pll_con >> PLL255XX_MDIV_SHIFT) & PLL255XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con >> PLL255XX_PDIV_SHIFT) & PLL255XX_PDIV_MASK)));
+}
+
+static int samsung_pll255xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 pll_con;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con = readl(pll->con_reg);
+ if (!(samsung_pll255xx_mp_check(rate->mdiv, rate->pdiv, pll_con))) {
+ if ((rate->sdiv) == ((pll_con >> PLL255XX_SDIV_SHIFT) & PLL255XX_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con &= ~(PLL255XX_SDIV_MASK << PLL255XX_SDIV_SHIFT);
+ pll_con |= rate->sdiv << PLL255XX_SDIV_SHIFT;
+ writel(pll_con, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL255XX_LOCK_FACTOR, pll->lock_reg);
+ /* Change PLL PMS values */
+ pll_con &= ~((PLL255XX_MDIV_MASK << PLL255XX_MDIV_SHIFT) |
+ (PLL255XX_PDIV_MASK << PLL255XX_PDIV_SHIFT) |
+ (PLL255XX_SDIV_MASK << PLL255XX_SDIV_SHIFT));
+ pll_con |= (rate->mdiv << PLL255XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL255XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL255XX_SDIV_SHIFT);
+
+ /* To prevent unstable PLL operation, preset enable bit with 0 */
+ pll_con &= ~BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con |= BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ do {
+ cpu_relax();
+ pll_con = readl(pll->con_reg);
+ } while (!(pll_con & (PLL255XX_LOCKED_MASK << PLL255XX_LOCKED_SHIFT)));
+
+ return 0;
+}
+
+/* register function for pll clocks */
+static const struct clk_ops samsung_pll255xx_clk_ops = {
+ .recalc_rate = samsung_pll255xx_recalc_rate,
+ .set_rate = samsung_pll255xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable_onchange,
+ .disable = samsung_composite_pll_disable_onchange,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL2650X_MDIV_SHIFT) & PLL2650X_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650X_PDIV_SHIFT) & PLL2650X_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650X_SDIV_SHIFT) & PLL2650X_SDIV_MASK;
+ kdiv = (s16)((pll_con1 >> PLL2650X_KDIV_SHIFT) & PLL2650X_KDIV_MASK);
+ /* Do calculation */
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2650x_mpk_check(u32 mdiv, u32 pdiv, u32 kdiv, u32 pll_con0, u32 pll_con1)
+{
+ return ((mdiv != ((pll_con0 >> PLL2650X_MDIV_SHIFT) & PLL2650X_MDIV_MASK)) ||
+ (pdiv != ((pll_con0 >> PLL2650X_PDIV_SHIFT) & PLL2650X_PDIV_MASK)) ||
+ (kdiv != ((pll_con1 >> PLL2650X_KDIV_SHIFT) & PLL2650X_KDIV_MASK)));
+}
+
+static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ if (!(samsung_pll2650x_mpk_check(rate->mdiv, rate->pdiv, rate->kdiv, pll_con0, pll_con1))) {
+ if ((rate->sdiv) == ((pll_con0 >> PLL2650X_SDIV_SHIFT) & PLL2650X_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con0 &= ~(PLL2650X_SDIV_MASK << PLL2650X_SDIV_SHIFT);
+ pll_con0 |= (rate->sdiv << PLL2650X_SDIV_SHIFT);
+ writel(pll_con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
+
+ pll_con1 &= ~(PLL2650X_KDIV_MASK << PLL2650X_KDIV_SHIFT);
+ pll_con1 |= (rate->kdiv << PLL2650X_KDIV_SHIFT);
+ writel(pll_con1, pll->con_reg + 4);
+
+ pll_con0 &= ~((PLL2650X_MDIV_MASK << PLL2650X_MDIV_SHIFT) |
+ (PLL2650X_PDIV_MASK << PLL2650X_PDIV_SHIFT) |
+ (PLL2650X_SDIV_MASK << PLL2650X_SDIV_SHIFT));
+ pll_con0 |= (rate->mdiv << PLL2650X_MDIV_SHIFT) |
+ (rate->pdiv << PLL2650X_PDIV_SHIFT) |
+ (rate->sdiv << PLL2650X_SDIV_SHIFT);
+
+ /* To prevent unstable PLL operation, preset enable bit with 0 */
+ pll_con0 &= ~BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con0 |= BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /*
+ * Wait lock time
+ * unit address translation : us to ms for mdelay
+ */
+ mdelay(rate->pdiv * PLL2650X_LOCK_FACTOR / 1000);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650x_clk_ops = {
+ .recalc_rate = samsung_pll2650x_recalc_rate,
+ .set_rate = samsung_pll2650x_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable_onchange,
+ .disable = samsung_composite_pll_disable_onchange,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+/* register function for pll clocks */
+static void _samsung_register_comp_pll(struct samsung_clk_provider *ctx,
+ struct samsung_composite_pll *list)
+{
+ struct clk *clk;
+ static const char *pname[1] = {"fin_pll"};
+ int len;
+ unsigned int ret = 0;
+
+ if (list->rate_table) {
+ /* find count of rates in rate_table */
+ for (len = 0; list->rate_table[len].rate != 0; )
+ len++;
+ list->rate_count = len; }
+ else
+ list->rate_count = 0;
+
+ if (list->type == pll_1450x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll145xx_clk_ops,
+ &list->hw, &samsung_pll145xx_clk_ops, list->flag);
+ else if (list->type == pll_1451x || list->type == pll_1452x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll145xx_clk_ops,
+ &list->hw, &samsung_pll145xx_clk_ops, list->flag);
+ else if (list->type == pll_1460x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll1460x_clk_ops,
+ &list->hw, &samsung_pll1460x_clk_ops, list->flag);
+ else if (list->type == pll_2551x || list->type == pll_2555x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll255xx_clk_ops,
+ &list->hw, &samsung_pll255xx_clk_ops, list->flag);
+ else if (list->type == pll_2650x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll2650x_clk_ops,
+ &list->hw, &samsung_pll2650x_clk_ops, list->flag);
+ else {
+ pr_err("%s: invalid pll type %d\n", __func__, list->type);
+ return;
+ }
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n",
+ __func__, list->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+void samsung_register_comp_pll(struct samsung_clk_provider *ctx,
+ struct samsung_composite_pll *list, unsigned int nr_pll)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_pll; cnt++)
+ _samsung_register_comp_pll(ctx, &list[cnt]);
+}
+
+/* operation functions for mux clocks */
+static u8 samsung_mux_get_parent(struct clk_hw *hw)
+{
+ struct samsung_composite_mux *mux = to_comp_mux(hw);
+ u32 val;
+
+ val = readl(mux->sel_reg) >> mux->sel_bit;
+ val &= (BIT(mux->sel_width) - 1);
+
+ return (u8)val;
+}
+
+static int samsung_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct samsung_composite_mux *mux = to_comp_mux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+
+ val = readl(mux->sel_reg);
+ val &= ~((BIT(mux->sel_width) - 1) << mux->sel_bit);
+ val |= index << mux->sel_bit;
+ writel(val, mux->sel_reg);
+
+ if (mux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to set parent %s.\n",
+ __func__, clk_hw_get_name(hw));
+ pr_err("MUX_REG: %08x, MUX_STAT_REG: %08x\n",
+ readl(mux->sel_reg), readl(mux->stat_reg));
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(mux->stat_reg);
+ val &= ((BIT(mux->stat_width) - 1) << mux->stat_bit);
+ } while (val != (index << mux->stat_bit));
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_composite_mux_ops = {
+ .get_parent = samsung_mux_get_parent,
+ .set_parent = samsung_mux_set_parent,
+};
+
+/* operation functions for mux clocks checking status with "on changing" */
+
+static int samsung_mux_set_parent_onchange(struct clk_hw *hw, u8 index)
+{
+ struct samsung_composite_mux *mux = to_comp_mux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+
+ val = readl(mux->sel_reg);
+ val &= ~((BIT(mux->sel_width) - 1) << mux->sel_bit);
+ val |= index << mux->sel_bit;
+ writel(val, mux->sel_reg);
+
+ if (mux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to set parent %s.\n",
+ __func__, clk_hw_get_name(hw));
+ pr_err("MUX_REG: %08x, MUX_STAT_REG: %08x\n",
+ readl(mux->sel_reg), readl(mux->stat_reg));
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(mux->stat_reg);
+ val &= ((BIT(mux->stat_width) - 1) << mux->stat_bit);
+ } while (val == PLL_STAT_CHANGE);
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+
+ return 0;
+}
+static const struct clk_ops samsung_composite_mux_ops_onchange = {
+ .get_parent = samsung_mux_get_parent,
+ .set_parent = samsung_mux_set_parent_onchange,
+};
+
+/* register function for mux clock */
+static void _samsung_register_comp_mux(struct samsung_clk_provider *ctx,
+ struct samsung_composite_mux *list)
+{
+ struct clk *clk;
+ unsigned int ret = 0;
+
+ list->lock = &lock;
+
+ if (!(list->flag & CLK_ON_CHANGING))
+ clk = clk_register_composite(NULL, list->name, list->parents, list->num_parents,
+ &list->hw, &samsung_composite_mux_ops,
+ NULL, NULL,
+ NULL, NULL, list->flag);
+ else
+ clk = clk_register_composite(NULL, list->name, list->parents, list->num_parents,
+ &list->hw, &samsung_composite_mux_ops_onchange,
+ NULL, NULL,
+ NULL, NULL, list->flag);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register mux clock %s\n",
+ __func__, list->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+void samsung_register_comp_mux(struct samsung_clk_provider *ctx,
+ struct samsung_composite_mux *list, unsigned int nr_mux)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_mux; cnt++)
+ _samsung_register_comp_mux(ctx, &list[cnt]);
+}
+
+/* operation functions for divider clocks */
+static unsigned long samsung_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_divider *divider = to_comp_divider(hw);
+ unsigned int val;
+
+ val = readl(divider->rate_reg) >> divider->rate_bit;
+ val &= (1 << divider->rate_width) - 1;
+ val += 1;
+ if (!val)
+ return parent_rate;
+
+ return parent_rate / val;
+}
+
+static int samsung_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate)
+{
+ struct samsung_composite_divider *divider = to_comp_divider(hw);
+ int i, bestdiv = 0;
+ unsigned long parent_rate, maxdiv, now, best = 0;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ maxdiv = ((unsigned long)(1UL << (divider->rate_width)) - 1UL) + 1UL;
+
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestdiv = (parent_rate + rate - 1) / rate;
+ bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+ return bestdiv;
+ }
+
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (i = 1; i <= maxdiv; i++) {
+ if (rate * i == parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = clk_round_rate(clk_get_parent(hw->clk),
+ ((rate * i) + i - 1));
+ now = parent_rate / i;
+ if (now <= rate && now > best) {
+ bestdiv = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestdiv) {
+ bestdiv = ((1 << (divider->rate_width)) - 1) + 1;
+ *best_parent_rate = clk_round_rate(clk_get_parent(hw->clk), 1);
+ }
+
+ return bestdiv;
+}
+
+static long samsung_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ int div = 1;
+
+ div = samsung_divider_bestdiv(hw, rate, prate);
+ if (div == 0) {
+ pr_err("%s: divider value should not be %d\n", __func__, div);
+ div = 1;
+ }
+
+ return *prate / div;
+}
+
+static int samsung_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_divider *divider = to_comp_divider(hw);
+ unsigned int div;
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ div = (parent_rate / rate) - 1;
+
+ if (div > ((1 << divider->rate_width) - 1))
+ div = (1 << divider->rate_width) - 1;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+
+ val = readl(divider->rate_reg);
+ val &= ~(((1 << divider->rate_width) - 1) << divider->rate_bit);
+ val |= div << divider->rate_bit;
+ writel(val, divider->rate_reg);
+
+ if (divider->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: faild to set rate %s.\n",
+ __func__, clk_hw_get_name(hw));
+ pr_err("DIV_REG: %08x, MUX_STAT_REG: %08x\n",
+ readl(divider->rate_reg), readl(divider->stat_reg));
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(divider->stat_reg);
+ val &= BIT(divider->stat_width - 1) << divider->stat_bit;
+ } while (val);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_composite_divider_ops = {
+ .recalc_rate = samsung_divider_recalc_rate,
+ .round_rate = samsung_divider_round_rate,
+ .set_rate = samsung_divider_set_rate,
+};
+
+/* register function for divider clocks */
+static void _samsung_register_comp_divider(struct samsung_clk_provider *ctx,
+ struct samsung_composite_divider *list)
+{
+ struct clk *clk;
+ unsigned int ret = 0;
+
+ list->lock = &lock;
+
+ clk = clk_register_composite(NULL, list->name, &list->parent_name, 1,
+ NULL, NULL,
+ &list->hw, &samsung_composite_divider_ops,
+ NULL, NULL, list->flag);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register mux clock %s\n",
+ __func__, list->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+void samsung_register_comp_divider(struct samsung_clk_provider *ctx,
+ struct samsung_composite_divider *list, unsigned int nr_div)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_div; cnt++)
+ _samsung_register_comp_divider(ctx, &list[cnt]);
+}
+
+struct dummy_gate_clk {
+ unsigned long offset;
+ u8 bit_idx;
+ struct clk *clk;
+};
+
+static struct dummy_gate_clk **gate_clk_list;
+static unsigned int gate_clk_nr;
+
+int samsung_add_clk_gate_list(struct clk *clk, unsigned long offset, u8 bit_idx, const char *name)
+{
+ struct dummy_gate_clk *tmp_clk;
+
+ if (!clk || !offset)
+ return -EINVAL;
+
+ tmp_clk = kzalloc(sizeof(struct dummy_gate_clk), GFP_KERNEL);
+ if (!tmp_clk) {
+ pr_err("%s: fail to alloc for gate_clk\n", __func__);
+ return -ENOMEM;
+ }
+
+ tmp_clk->offset = offset;
+ tmp_clk->bit_idx = bit_idx;
+ tmp_clk->clk = clk;
+
+ gate_clk_list[gate_clk_nr] = tmp_clk;
+
+ gate_clk_nr++;
+
+ return 0;
+}
+
+struct clk *samsung_clk_get_by_reg(unsigned long offset, u8 bit_idx)
+{
+ unsigned int i;
+
+ for (i = 0; i < gate_clk_nr; i++) {
+ if (gate_clk_list[i]->offset == offset) {
+ if (gate_clk_list[i]->bit_idx == bit_idx)
+ return gate_clk_list[i]->clk;
+ }
+ }
+
+ pr_err("%s: Fail to get clk by register offset\n", __func__);
+
+ return 0;
+}
+
+/* existing register function for gate clocks */
+static struct clk * __init _samsung_register_gate(
+ struct samsung_clk_provider *ctx, struct samsung_gate *list)
+{
+ struct clk *clk;
+ unsigned int ret = 0;
+
+ clk = clk_register_gate(NULL, list->name, list->parent_name,
+ list->flag, list->reg, list->bit,
+ list->flag, &lock);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ return 0;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+
+ return clk;
+}
+
+void __init samsung_register_gate(struct samsung_clk_provider *ctx,
+ struct samsung_gate *list, unsigned int nr_gate)
+{
+ int cnt;
+ struct clk *clk;
+ bool gate_list_fail = false;
+ unsigned int gate_enable_nr = 0;
+ struct clk **gate_enable_list;
+
+ gate_clk_list = kzalloc(sizeof(struct dummy_gate_clk *) * nr_gate, GFP_KERNEL);
+ if (!gate_clk_list) {
+ pr_err("%s: can not alloc for gate clock list\n", __func__);
+ gate_list_fail = true;
+ }
+
+ gate_enable_list = kzalloc(sizeof(struct clk *) * nr_gate, GFP_KERNEL);
+
+ if (!gate_enable_list) {
+ pr_err("%s: can not alloc for enable gate clock list\n", __func__);
+ return ;
+ }
+
+ for (cnt = 0; cnt < nr_gate; cnt++) {
+ clk = _samsung_register_gate(ctx, &list[cnt]);
+
+ if (((&list[cnt])->flag & CLK_GATE_ENABLE) && gate_enable_list) {
+ gate_enable_list[gate_enable_nr] = clk;
+ gate_enable_nr++;
+ }
+
+ /* Make list for gate clk to used by samsung_clk_get_by_reg */
+ if (!gate_list_fail)
+ samsung_add_clk_gate_list(clk, (unsigned long)(list[cnt].reg), list[cnt].bit, list[cnt].name);
+ }
+
+ /*
+ * Enable for not controlling gate clocks
+ */
+ for (cnt = 0; cnt < gate_enable_nr; cnt++)
+ clk_prepare_enable(gate_enable_list[cnt]);
+
+ if (gate_enable_list)
+ kfree(gate_enable_list);
+}
+
+/* operation functions for usermux clocks */
+static int samsung_usermux_is_enabled(struct clk_hw *hw)
+{
+ struct clk_samsung_usermux *usermux = to_usermux(hw);
+ u32 val;
+
+ val = readl(usermux->sel_reg);
+ val &= BIT(usermux->sel_bit);
+
+ return val ? 1 : 0;
+}
+
+static int samsung_usermux_enable(struct clk_hw *hw)
+{
+ struct clk_samsung_usermux *usermux = to_usermux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (usermux->lock)
+ spin_lock_irqsave(usermux->lock, flags);
+
+ val = readl(usermux->sel_reg);
+ val &= ~(1 << usermux->sel_bit);
+ val |= (1 << usermux->sel_bit);
+ writel(val, usermux->sel_reg);
+
+ if (usermux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to enable clock %s.\n",
+ __func__, clk_hw_get_name(hw));
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(usermux->stat_reg);
+ val &= BIT(2) << usermux->stat_bit;
+ } while (val);
+
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+
+ return 0;
+}
+
+static void samsung_usermux_disable(struct clk_hw *hw)
+{
+ struct clk_samsung_usermux *usermux = to_usermux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (usermux->lock)
+ spin_lock_irqsave(usermux->lock, flags);
+
+ val = readl(usermux->sel_reg);
+ val &= ~(1 << usermux->sel_bit);
+ writel(val, usermux->sel_reg);
+
+ if (usermux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to disable clock %s.\n",
+ __func__, clk_hw_get_name(hw));
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+ return;
+ }
+ val = readl(usermux->stat_reg);
+ val &= BIT(2) << usermux->stat_bit;
+ } while (val);
+
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+}
+
+static const struct clk_ops samsung_usermux_ops = {
+ .enable = samsung_usermux_enable,
+ .disable = samsung_usermux_disable,
+ .is_enabled = samsung_usermux_is_enabled,
+};
+
+/* register function for usermux clocks */
+static struct clk * __init _samsung_register_comp_usermux(struct samsung_usermux *list)
+{
+ struct clk_samsung_usermux *usermux;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ usermux = kzalloc(sizeof(struct clk_samsung_usermux), GFP_KERNEL);
+ if (!usermux) {
+ pr_err("%s: could not allocate usermux clk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = list->name;
+ init.ops = &samsung_usermux_ops;
+ init.flags = list->flag | CLK_IS_BASIC;
+ init.parent_names = (list->parent_name ? &list->parent_name : NULL);
+ init.num_parents = (list->parent_name ? 1 : 0);
+
+ usermux->sel_reg = list->sel_reg;
+ usermux->sel_bit = list->sel_bit;
+ usermux->stat_reg = list->stat_reg;
+ usermux->stat_bit = list->stat_bit;
+ usermux->flag = 0;
+ usermux->lock = &lock;
+ usermux->hw.init = &init;
+
+ clk = clk_register(NULL, &usermux->hw);
+
+ if (IS_ERR(clk))
+ kfree(usermux);
+
+ return clk;
+}
+
+void __init samsung_register_usermux(struct samsung_clk_provider *ctx,
+ struct samsung_usermux *list, unsigned int nr_usermux)
+{
+ struct clk *clk;
+ int cnt;
+ unsigned int ret = 0;
+
+ for (cnt = 0; cnt < nr_usermux; cnt++) {
+ clk = _samsung_register_comp_usermux(&list[cnt]);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ (&list[cnt])->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, (&list[cnt])->id);
+
+ if ((&list[cnt])->alias) {
+ ret = clk_register_clkdev(clk, (&list[cnt])->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, (&list[cnt])->alias);
+ }
+ }
+}
+
+/**
+ * Operations for virtual clock used in cal
+ * When cal is used to set clocks, following operations will be executed.
+ */
+int cal_vclk_enable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if ((vclk->flags & VCLK_GATE) && !(vclk->flags & VCLK_QCH_DIS))
+ return 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_IN);
+ /* Call cal api to enable virtual clock */
+ ret = cal_clk_enable(vclk->id);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %d.\n", __func__, vclk->id, ret);
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return 0;
+}
+
+void cal_vclk_disable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if ((vclk->flags & VCLK_GATE) && !(vclk->flags & VCLK_QCH_DIS))
+ return ;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+ /* Call cal api to disable virtual clock */
+ ret = cal_clk_disable(vclk->id);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %d.\n", __func__, vclk->id, ret);
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return;
+ }
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+}
+
+int cal_vclk_is_enabled(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ int ret = 0;
+
+ /*
+ * Call cal api to check whether clock is enabled or not
+ * Spinlock is not needed because only read operation will
+ * be executed
+ */
+ ret = cal_clk_is_enabled(vclk->id);
+
+ return ret;
+}
+
+unsigned long cal_vclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long ret = 0;
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+ /* Call cal api to recalculate rate */
+ ret = cal_clk_getrate(vclk->id);
+ exynos_ss_clk(hw, __func__, ret, ESS_FLAG_OUT);
+
+ return ret;
+}
+
+unsigned long cal_vclk_gate_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk;
+ struct clk_hw *parent;
+ unsigned long ret = 0;
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+ parent = clk_hw_get_parent(hw);
+ if (parent) {
+ vclk = to_vclk(parent);
+ /* call cal api to recalculate rate */
+ ret = cal_clk_getrate(vclk->id);
+ }
+ exynos_ss_clk(hw, __func__, ret, ESS_FLAG_OUT);
+
+ return ret;
+}
+
+long cal_vclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ /* round_rate ops is not needed when using cal */
+ return (long)rate;
+}
+
+int cal_vclk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_IN);
+ /* Call cal api to set rate of clock */
+ ret = cal_clk_setrate(vclk->id, rate);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %lu %d.\n", __func__,
+ vclk->id, rate, ret);
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return ret;
+}
+
+unsigned long cal_vclk_dfs_sw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long ret = 0;
+
+ /* Call cal api to recalculate rate */
+ ret = cal_dfs_cached_get_rate(vclk->id);
+
+ return ret;
+}
+unsigned long cal_vclk_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long ret = 0;
+
+ /* Call cal api to recalculate rate */
+ ret = cal_dfs_get_rate(vclk->id);
+
+ return ret;
+}
+
+int cal_vclk_dfs_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_IN);
+ /* Call cal api to set rate of clock */
+ ret = cal_dfs_set_rate(vclk->id, rate);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %lu %d.\n", __func__,
+ vclk->id, rate, ret);
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return ret;
+}
+
+int cal_vclk_dfs_set_rate_switch(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ /* Call cal api to set rate of clock */
+ ret = cal_dfs_set_rate_switch(vclk->id, rate);
+ if (ret) {
+ pr_err("[CAL]%s failed.\n", __func__);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return ret;
+}
+
+static int cal_vclk_qch_init(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ int ret = 0;
+
+ if (vclk->flags & VCLK_QCH_EN)
+ ret = cal_qch_init(vclk->id, 1);
+ else if (vclk->flags & VCLK_QCH_DIS)
+ ret = cal_qch_init(vclk->id, 0);
+
+ return ret;
+}
+
+int cal_vclk_qactive_enable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ unsigned int reg;
+
+ if (!(vclk->flags & VCLK_QACTIVE))
+ return 0;
+
+ if (!vclk->addr)
+ return 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_IN);
+
+ reg = readl(vclk->addr);
+ reg &= ~(vclk->mask);
+ reg |= vclk->val;
+ writel(reg, vclk->addr);
+
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return 0;
+}
+
+void cal_vclk_qactive_disable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ unsigned int reg;
+
+ if (!(vclk->flags & VCLK_QACTIVE))
+ return ;
+
+ if (!vclk->addr)
+ return ;;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+
+ reg = readl(vclk->addr);
+ reg &= ~(vclk->mask);
+ writel(reg, vclk->addr);
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+}
+
+static const struct clk_ops samsung_vclk_ops = {
+ .enable = cal_vclk_enable,
+ .disable = cal_vclk_disable,
+ .is_enabled = cal_vclk_is_enabled,
+ .recalc_rate = cal_vclk_recalc_rate,
+ .round_rate = cal_vclk_round_rate,
+ .set_rate = cal_vclk_set_rate,
+};
+
+static const struct clk_ops samsung_vclk_dfs_ops = {
+ .recalc_rate = cal_vclk_dfs_recalc_rate,
+ .round_rate = cal_vclk_round_rate,
+ .set_rate = cal_vclk_dfs_set_rate,
+};
+
+static const struct clk_ops samsung_vclk_dfs_sw_ops = {
+ .recalc_rate = cal_vclk_dfs_sw_recalc_rate,
+ .round_rate = cal_vclk_round_rate,
+ .set_rate = cal_vclk_dfs_set_rate_switch,
+};
+
+static const struct clk_ops samsung_vclk_gate_ops = {
+ .enable = cal_vclk_enable,
+ .disable = cal_vclk_disable,
+ .is_enabled = cal_vclk_is_enabled,
+ .recalc_rate = cal_vclk_gate_recalc_rate,
+};
+
+static const struct clk_ops samsung_vclk_qactive_ops = {
+ .enable = cal_vclk_qactive_enable,
+ .disable = cal_vclk_qactive_disable,
+};
+
+static struct clk * __init _samsung_register_vclk(struct init_vclk *list)
+{
+ struct samsung_vclk *vclk;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ vclk = kzalloc(sizeof(struct samsung_vclk), GFP_KERNEL);
+ if (!vclk) {
+ pr_err("%s: could not allocate struct vclk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = list->name;
+ if (list->vclk_flags & VCLK_DFS)
+ init.ops = &samsung_vclk_dfs_ops;
+ else if (list->vclk_flags & VCLK_DFS_SWITCH)
+ init.ops = &samsung_vclk_dfs_sw_ops;
+ else if (list->vclk_flags & VCLK_GATE)
+ init.ops = &samsung_vclk_gate_ops;
+ else if (list->vclk_flags & VCLK_QACTIVE) {
+ init.ops = &samsung_vclk_qactive_ops;
+ vclk->addr = ioremap(list->addr, 4);
+ vclk->mask = list->mask;
+ vclk->val = list->val;
+ } else
+ init.ops = &samsung_vclk_ops;
+ init.flags = list->flags | (CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
+ init.parent_names = (list->parent ? &list->parent : NULL);
+ init.num_parents = (list->parent ? 1 : 0);
+ vclk->id = list->calid;
+ /* Flags for vclk are not defined yet */
+ vclk->flags = list->vclk_flags;
+ vclk->lock = &lock;
+ vclk->hw.init = &init;
+ clk = clk_register(NULL, &vclk->hw);
+
+ if (IS_ERR(clk))
+ kfree(vclk);
+
+ return clk;
+}
+
+void __init samsung_register_vclk(struct samsung_clk_provider *ctx,
+ struct init_vclk *list, unsigned int nr_vclk)
+{
+ struct clk *clk;
+ int cnt;
+ unsigned int ret = 0;
+
+ for (cnt = 0; cnt < nr_vclk; cnt++) {
+ clk = _samsung_register_vclk(&list[cnt]);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register virtual clock %s\n",
+ __func__, (&list[cnt])->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, (&list[cnt])->id);
+
+ /* Additional array of clocks for finding struct clk */
+ if ((&list[cnt])->alias) {
+ ret = clk_register_clkdev(clk, (&list[cnt])->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, (&list[cnt])->alias);
+ }
+
+ cal_vclk_qch_init(__clk_get_hw(clk));
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions for composite clocks.
+ */
+
+#ifndef __SAMSUNG_CLK_COMPOSITE_H
+#define __SAMSUNG_CLK_COMPOSITE_H
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+
+/*
+ * struct samsung_clk_provider: information about clock provider
+ * @reg_base: virtual address for the register base.
+ * @clk_data: holds clock related data like clk* and number of clocks.
+ * @lock: maintains exclusion bwtween callbacks for a given clock-provider.
+ */
+struct samsung_clk_provider {
+ void __iomem *reg_base;
+ struct clk_onecell_data clk_data;
+ spinlock_t lock;
+};
+
+/*
+ * struct samsung_clk_reg_dump: register dump of clock controller registers.
+ * @offset: clock register offset from the controller base address.
+ * @value: the value to be register at offset.
+ */
+struct samsung_clk_reg_dump {
+ unsigned long offset;
+ u32 value;
+};
+
+/*
+ * struct samsung_fixed_rate_clock: information about fixed-rate clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-rate clock.
+ * @parent_name: optional parent clock name.
+ * @flags: optional fixed-rate clock flags.
+ * @fixed-rate: fixed clock rate of this clock.
+ */
+struct samsung_fixed_rate {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long fixed_rate;
+};
+
+#define FRATE(_id, cname, pname, f, frate) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .fixed_rate = frate, \
+ }
+
+extern void __init samsung_register_fixed_rate(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *list,
+ unsigned int nr_clk);
+/*
+ * struct samsung_fixed_factor_clock: information about fixed-factor clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-factor clock.
+ * @parent_name: parent clock name.
+ * @mult: fixed multiplication factor.
+ * @div: fixed division factor.
+ * @flags: optional fixed-factor clock flags.
+ */
+struct samsung_fixed_factor {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long mult;
+ unsigned long div;
+ unsigned long flags;
+};
+
+#define FFACTOR(_id, cname, pname, m, d, f) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .mult = m, \
+ .div = d, \
+ .flags = f, \
+ }
+
+extern void __init samsung_register_fixed_factor(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_factor *list,
+ unsigned int nr_clk);
+
+/*
+ * PLL145xx Clock Type: PLL1450x, PLL1451x, PLL1452x
+ * Maximum lock time can be 150 * Pdiv cycles
+ */
+#define PLL145XX_LOCK_FACTOR (150)
+#define PLL145XX_MDIV_MASK (0x3FF)
+#define PLL145XX_PDIV_MASK (0x03F)
+#define PLL145XX_SDIV_MASK (0x007)
+#define PLL145XX_LOCKED_MASK (0x1)
+#define PLL145XX_MDIV_SHIFT (16)
+#define PLL145XX_PDIV_SHIFT (8)
+#define PLL145XX_SDIV_SHIFT (0)
+#define PLL145XX_LOCKED_SHIFT (29)
+
+/*
+ * PLL1460X Clock Type
+ * Maximum lock time can be 3000 * Pdiv cycles
+ */
+#define PLL1460X_LOCK_FACTOR (3000)
+#define PLL1460X_MDIV_MASK (0x03FF)
+#define PLL1460X_PDIV_MASK (0x003F)
+#define PLL1460X_SDIV_MASK (0x0007)
+#define PLL1460X_KDIV_MASK (0xFFFF)
+#define PLL1460X_LOCKED_MASK (0x1)
+#define PLL1460X_MDIV_SHIFT (16)
+#define PLL1460X_PDIV_SHIFT (8)
+#define PLL1460X_SDIV_SHIFT (0)
+#define PLL1460X_KDIV_SHIFT (0)
+#define PLL1460X_LOCKED_SHIFT (29)
+
+/*
+ * PLL255xx Clock Type : PLL2551x, PLL2555x
+ * Maximum lock time can be 200 * Pdiv cycles
+ */
+#define PLL255XX_LOCK_FACTOR (200)
+#define PLL255XX_MDIV_MASK (0x3FF)
+#define PLL255XX_PDIV_MASK (0x3F)
+#define PLL255XX_SDIV_MASK (0x7)
+#define PLL255XX_LOCKED_MASK (0x1)
+#define PLL255XX_MDIV_SHIFT (12)
+#define PLL255XX_PDIV_SHIFT (4)
+#define PLL255XX_SDIV_SHIFT (0)
+#define PLL255XX_LOCKED_SHIFT (29)
+
+/*
+ * PLL2650X Clock Type
+ * Maximum lock time can be 3000 * Pdiv cycles
+ */
+#define PLL2650X_LOCK_FACTOR (3000)
+#define PLL2650X_MDIV_MASK (0x01FF)
+#define PLL2650X_PDIV_MASK (0x003F)
+#define PLL2650X_SDIV_MASK (0x0007)
+#define PLL2650X_KDIV_MASK (0xFFFF)
+#define PLL2650X_LOCKED_MASK (0x1)
+#define PLL2650X_MDIV_SHIFT (12)
+#define PLL2650X_PDIV_SHIFT (4)
+#define PLL2650X_SDIV_SHIFT (0)
+#define PLL2650X_KDIV_SHIFT (0)
+#define PLL2650X_LOCKED_SHIFT (29)
+
+enum pll_type {
+ pll_1450x = 0,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
+ pll_2551x,
+ pll_2555x,
+ pll_2650x,
+};
+
+struct samsung_pll_rate_table {
+ long rate;
+ unsigned int pdiv;
+ unsigned int mdiv;
+ unsigned int sdiv;
+ unsigned int kdiv;
+};
+
+#define PLL_BYPASS BIT(0)
+#define CHK_ON_CHANGING BIT(7)
+/*
+ * struct samsung_composite_pll: information about composite-pll clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this pll clock.
+ * @type: type of this pll clock.
+ * @lock_reg: register for locking pll.
+ * @con_reg: configuration register for pll.
+ * @enable_reg: it can be different whether pll can be gated or only bypassed.
+ * @enable_bit: bit index for en/disable pll.
+ * @sel_reg: composite-pll has ctrl-mux. when disabled, it is set by 0.
+ * @sel_bit: bit index for ctrl-mux.
+ * @stat_reg: when sel_reg is set, status register must be checked.
+ * @stat_bit: bit index for status register.
+ * @rate_table: available pll output ratio table.
+ * @alias: support alias for this clock.
+ */
+struct samsung_composite_pll {
+ struct clk_hw hw;
+ unsigned int id;
+ const char *name;
+ enum pll_type type;
+ void __iomem *lock_reg;
+ void __iomem *con_reg;
+ void __iomem *enable_reg;
+ unsigned int enable_bit;
+ void __iomem *sel_reg;
+ unsigned int sel_bit;
+ void __iomem *stat_reg;
+ unsigned int stat_bit;
+ const struct samsung_pll_rate_table *rate_table;
+ unsigned int rate_count;
+ unsigned int pll_flag;
+ u8 flag;
+ const char *alias;
+};
+
+#define PLL(_id, cname, _type, lock, con, en, enbit, sel, selbit, stat, statbit, rtable, pf, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .type = _type, \
+ .lock_reg = lock, \
+ .con_reg = con, \
+ .enable_reg = en, \
+ .enable_bit = enbit, \
+ .sel_reg = sel, \
+ .sel_bit = selbit, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .rate_table = rtable, \
+ .rate_count = 0, \
+ .pll_flag = pf, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void samsung_register_comp_pll(
+ struct samsung_clk_provider *ctx,
+ struct samsung_composite_pll *pll_list,
+ unsigned int nr_pll);
+
+#define PNAME(x) static const char *x[]
+/*
+ * struct samsung_composite_mux: information about composite-mux clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this mux clock.
+ * @parents: array of parent clocks.
+ * @num_parents: number of parent clocks.
+ * @sel_reg: register for mux selection.
+ * @sel_bit: bit index for sel_reg.
+ * @sel_width: different by number of parent clocks.
+ * @stat_reg: status must be checked when changing parent.
+ * @stat_bit: bit index for status register.
+ * @stat_width: different by number of parent clocks.
+ * @flag: optional flag for clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct samsung_composite_mux {
+ struct clk_hw hw;
+ unsigned int id;
+ const char *name;
+ const char **parents;
+ unsigned int num_parents;
+ void __iomem *sel_reg;
+ unsigned int sel_bit;
+ unsigned int sel_width;
+ void __iomem *stat_reg;
+ unsigned int stat_bit;
+ unsigned int stat_width;
+ unsigned int flag;
+ const char *alias;
+ spinlock_t *lock;
+};
+
+#define MUX(_id, cname, pnames, sel, selbit, selwid, stat, statbit, statwid, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parents = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .sel_reg = sel, \
+ .sel_bit = selbit, \
+ .sel_width = selwid, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .stat_width = statwid, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void samsung_register_comp_mux(
+ struct samsung_clk_provider *ctx,
+ struct samsung_composite_mux *mux_list,
+ unsigned int nr_mux);
+
+/*
+ * struct samsung_composite_divider: information about composite-divider clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this divider clock.
+ * @parent_name: name of parent clock.
+ * @rate_reg: register for ratio selection.
+ * @rate_bit: bit index for rate_reg.
+ * @rate_width: can be different by bit index.
+ * @stat_reg: status must be checked when changing ratio.
+ * @stat_bit: bit index for status register.
+ * @stat_width: can be different by bit index.
+ * @flag: flag for clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct samsung_composite_divider {
+ struct clk_hw hw;
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ void __iomem *rate_reg;
+ unsigned int rate_bit;
+ unsigned int rate_width;
+ void __iomem *stat_reg;
+ unsigned int stat_bit;
+ unsigned int stat_width;
+ unsigned int flag;
+ const char *alias;
+ spinlock_t *lock;
+};
+
+#define DIV(_id, cname, pname, rate, ratebit, ratewid, stat, statbit, statwid, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .rate_reg = rate, \
+ .rate_bit = ratebit, \
+ .rate_width = ratewid, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .stat_width = statwid, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void samsung_register_comp_divider(struct samsung_clk_provider *ctx,
+ struct samsung_composite_divider *div_list, unsigned int nr_div);
+
+#define CLK_GATE_ENABLE BIT(20)
+#define CLK_ON_CHANGING BIT(7)
+/*
+ * struct samsung_gate: information about gate clocks
+ * @id: id of the clock for binding with device tree.
+ * @name:
+ * @parent_name:
+ * @reg:
+ * @bit:
+ * @flag:
+ * @alias:
+ */
+struct samsung_gate {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ void __iomem *reg;
+ u8 bit;
+ unsigned int flag;
+ const char *alias;
+};
+
+#define GATE(_id, cname, pname, r, b, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .reg = r, \
+ .bit = b, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void __init samsung_register_gate(
+ struct samsung_clk_provider *ctx,
+ struct samsung_gate *gate_list,
+ unsigned int nr_gate);
+
+struct clk_samsung_usermux {
+ struct clk_hw hw;
+ void __iomem *sel_reg;
+ u8 sel_bit;
+ void __iomem *stat_reg;
+ u8 stat_bit;
+ u8 flag;
+ spinlock_t *lock;
+};
+
+/*
+ * struct samsung_composite_usermux: information about usermux clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this usermux clock.
+ * @parent_name: name of parent clock.
+ * @sel_reg: register for usermux selection.
+ * @sel_bit: bit index for sel_reg.
+ * @stat_reg: status must be checked when changing parent.
+ * @stat_bit: bit index for status register.
+ * @flag: optional flag for clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct samsung_usermux {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ void __iomem *sel_reg;
+ u8 sel_bit;
+ void __iomem *stat_reg;
+ u8 stat_bit;
+ u8 flag;
+ const char *alias;
+};
+
+#define USERMUX(_id, cname, pname, sel, selbit, stat, statbit, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .sel_reg = sel, \
+ .sel_bit = selbit, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void __init samsung_register_usermux(
+ struct samsung_clk_provider *ctx,
+ struct samsung_usermux *list,
+ unsigned int nr_usermux);
+
+#define VCLK_DFS BIT(1)
+#define VCLK_DFS_SWITCH BIT(2)
+#define VCLK_GATE BIT(3)
+#define VCLK_QCH_EN BIT(4)
+#define VCLK_QCH_DIS BIT(5)
+#define VCLK_QACTIVE BIT(6)
+
+/*
+ * struct init_vclk: initial information for virtual clocks
+ * @id: id of the clock for binding with device tree.
+ * @calid: id of the clock for calling cal.
+ * @name: name of this virtual clock.
+ * @flags: optional flag for clock.
+ * @vclk_flags: optional flag for only virtual clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct init_vclk{
+ unsigned int id;
+ unsigned int calid;
+ const char *name;
+ const char *parent;
+ u8 flags;
+ u8 vclk_flags;
+ const char *alias;
+ u32 addr;
+ u32 mask;
+ u32 val;
+};
+
+struct samsung_vclk {
+ struct clk_hw hw;
+ unsigned int id;
+ u8 flags;
+ spinlock_t *lock;
+ void __iomem *addr;
+ u32 mask;
+ u32 val;
+};
+
+#define VCLK(_id, _calid, _name, f, vf, a) \
+ { \
+ .id = _id, \
+ .calid = _calid, \
+ .name = _name, \
+ .flags = f, \
+ .vclk_flags = vf, \
+ .alias = a, \
+ }
+
+#define HWACG_VCLK(_id, _calid, _name, _parent, f, vf, a) \
+ { \
+ .id = _id, \
+ .calid = _calid, \
+ .name = _name, \
+ .parent = _parent, \
+ .flags = f, \
+ .vclk_flags = vf, \
+ .alias = a, \
+ }
+
+#define HWACG_VCLK_QACTIVE(_id, _name, _parent, f, vf, a, _addr, _mask, _val) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent = _parent, \
+ .flags = f, \
+ .vclk_flags = vf, \
+ .alias = a, \
+ .addr = _addr, \
+ .mask = _mask, \
+ .val = _val, \
+ }
+
+extern void __init samsung_register_vclk(struct samsung_clk_provider *ctx,
+ struct init_vclk *list, unsigned int nr_vclk);
+
+extern struct samsung_clk_provider *__init samsung_clk_init(
+ struct device_node *np, void __iomem *base,
+ unsigned long nr_clks);
+
+extern void __init samsung_clk_of_add_provider(struct device_node *np,
+ struct samsung_clk_provider *ctx);
+
+extern void __init samsung_register_of_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ struct of_device_id *clk_matches);
+
+extern void samsung_clk_save(void __iomem *base,
+ struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs);
+extern void samsung_clk_restore(void __iomem *base,
+ const struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs);
+extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
+ const unsigned long *rdump,
+ unsigned long nr_rdump);
+
+#endif /* __SAMSUNG_CLK_COMPOSITE_H */
--- /dev/null
+# Recent Exynos platforms should just select COMMON_CLK_SAMSUNG:
+config COMMON_CLK_SAMSUNG
+ bool "Samsung Exynos clock controller support" if COMPILE_TEST
+ # Clocks on ARM64 SoCs (e.g. Exynos5433, Exynos7) are chosen by
+ # EXYNOS_ARM64_COMMON_CLK to avoid building them on ARMv7:
+ select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
+
+config COMPOSITE_CLK_SAMSUNG
+ bool
+ default y
+ depends on ARCH_EXYNOS9 || ARCH_EXYNOS8 || ARCH_EXYNOS7
+
+config EXYNOS_ARM64_COMMON_CLK
+ bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
+ depends on COMMON_CLK_SAMSUNG
+
+config EXYNOS_AUDSS_CLK_CON
+ tristate "Samsung Exynos AUDSS clock controller support"
+ depends on COMMON_CLK_SAMSUNG
+ default y if ARCH_EXYNOS
+ help
+ Support for the Audio Subsystem CLKCON clock controller present
+ on some Exynos SoC variants. Choose M or Y here if you want to
+ use audio devices such as I2S, PCM, etc.
+
+# For S3C24XX platforms, select following symbols:
+config S3C2410_COMMON_CLK
+ bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
+ select COMMON_CLK_SAMSUNG
+ help
+ Build the s3c2410 clock driver based on the common clock framework.
+
+config S3C2410_COMMON_DCLK
+ bool
+ select COMMON_CLK_SAMSUNG
+ select REGMAP_MMIO
+ help
+ Temporary symbol to build the dclk driver based on the common clock
+ framework.
+
+config S3C2412_COMMON_CLK
+ bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
+ select COMMON_CLK_SAMSUNG
+
+config S3C2443_COMMON_CLK
+ bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
+ select COMMON_CLK_SAMSUNG
--- /dev/null
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
+obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
+obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
+obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
+ifeq ($(CONFIG_COMPOSITE_CLK_SAMSUNG), y)
+ obj-y += composite.o
+ obj-$(CONFIG_SOC_EXYNOS8890) += clk-exynos8890.o
+ obj-$(CONFIG_SOC_EXYNOS8895) += clk-exynos8895.o
+ obj-$(CONFIG_SOC_EXYNOS9810_EVT1) += clk-exynos9810.o
+ obj-$(CONFIG_SOC_EXYNOS9810_EVT0) += clk-exynos9810_evt0.o
+ obj-$(CONFIG_SOC_EXYNOS9610) += clk-exynos9610.o
+else
+ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
+endif
+obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
+obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
+obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
+obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
+obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
+obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
+obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to the
+ * CPU clock rate and this relation is usually specified in the hardware manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is divided
+ * down in order to keep the output clock rate within the previous OPP limits.
+*/
+
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include "clk-cpu.h"
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU0 0x400
+#define E4210_DIV_STAT_CPU1 0x404
+
+#define E5433_MUX_SEL2 0x008
+#define E5433_MUX_STAT2 0x208
+#define E5433_DIV_CPU0 0x400
+#define E5433_DIV_CPU1 0x404
+#define E5433_DIV_STAT_CPU0 0x500
+#define E5433_DIV_STAT_CPU1 0x504
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK (0x7 << 4)
+#define E4210_DIV1_COPY_MASK (0x7 << 0)
+#define E4210_MUX_HPM_MASK (1 << 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV 8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0xffffffff
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) & mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ if (!(readl(div_reg) & mask))
+ return;
+
+ pr_err("%s: timeout in divider stablization\n", __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+ return;
+ } while (time_before(jiffies, timeout));
+
+ if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+ return;
+
+ pr_err("%s: re-parenting mux timed-out\n", __func__);
+}
+
+/* common round rate callback useable for all types of CPU clocks */
+static long exynos_cpuclk_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ *prate = clk_hw_round_rate(parent, drate);
+ return *prate;
+}
+
+/* common recalc rate callback useable for all types of CPU clocks */
+static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ /*
+ * The CPU clock output (armclk) rate is the same as its parent
+ * rate. Although there exist certain dividers inside the CPU
+ * clock block that could be used to divide the parent clock,
+ * the driver does not make use of them currently, except during
+ * frequency transitions.
+ */
+ return parent_rate;
+}
+
+static const struct clk_ops exynos_cpuclk_clk_ops = {
+ .recalc_rate = exynos_cpuclk_recalc_rate,
+ .round_rate = exynos_cpuclk_round_rate,
+};
+
+/*
+ * Helper function to set the 'safe' dividers for the CPU clock. The parameters
+ * div and mask contain the divider value and the register bit mask of the
+ * dividers to be programmed.
+ */
+static void exynos_set_safe_div(void __iomem *base, unsigned long div,
+ unsigned long mask)
+{
+ unsigned long div0;
+
+ div0 = readl(base + E4210_DIV_CPU0);
+ div0 = (div0 & ~mask) | (div & mask);
+ writel(div0, base + E4210_DIV_CPU0);
+ wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
+}
+
+/* handler for pre-rate change notification from parent clock */
+static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
+ unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
+ unsigned long div0, div1 = 0, mux_reg;
+ unsigned long flags;
+
+ /* find out the divider values to use for clock data */
+ while ((cfg_data->prate * 1000) != ndata->new_rate) {
+ if (cfg_data->prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+
+ spin_lock_irqsave(cpuclk->lock, flags);
+
+ /*
+ * For the selected PLL clock frequency, get the pre-defined divider
+ * values. If the clock for sclk_hpm is not sourced from apll, then
+ * the values for DIV_COPY and DIV_HPM dividers need not be set.
+ */
+ div0 = cfg_data->div0;
+ if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
+ div1 = cfg_data->div1;
+ if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
+ div1 = readl(base + E4210_DIV_CPU1) &
+ (E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
+ }
+
+ /*
+ * If the old parent clock speed is less than the clock speed of
+ * the alternate parent, then it should be ensured that at no point
+ * the armclk speed is more than the old_prate until the dividers are
+ * set. Also workaround the issue of the dividers being set to lower
+ * values before the parent clock speed is set to new lower speed
+ * (this can result in too high speed of armclk output clocks).
+ */
+ if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
+ unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
+
+ alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
+ WARN_ON(alt_div >= MAX_DIV);
+
+ if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
+ /*
+ * In Exynos4210, ATB clock parent is also mout_core. So
+ * ATB clock also needs to be mantained at safe speed.
+ */
+ alt_div |= E4210_DIV0_ATB_MASK;
+ alt_div_mask |= E4210_DIV0_ATB_MASK;
+ }
+ exynos_set_safe_div(base, alt_div, alt_div_mask);
+ div0 |= alt_div;
+ }
+
+ /* select sclk_mpll as the alternate parent */
+ mux_reg = readl(base + E4210_SRC_CPU);
+ writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
+ wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
+
+ /* alternate parent is active now. set the dividers */
+ writel(div0, base + E4210_DIV_CPU0);
+ wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
+
+ if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
+ writel(div1, base + E4210_DIV_CPU1);
+ wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
+ DIV_MASK_ALL);
+ }
+
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ return 0;
+}
+
+/* handler for post-rate change notification from parent clock */
+static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ unsigned long div = 0, div_mask = DIV_MASK;
+ unsigned long mux_reg;
+ unsigned long flags;
+
+ /* find out the divider values to use for clock data */
+ if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
+ while ((cfg_data->prate * 1000) != ndata->new_rate) {
+ if (cfg_data->prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+ }
+
+ spin_lock_irqsave(cpuclk->lock, flags);
+
+ /* select mout_apll as the alternate parent */
+ mux_reg = readl(base + E4210_SRC_CPU);
+ writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
+ wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
+
+ if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
+ div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
+ div_mask |= E4210_DIV0_ATB_MASK;
+ }
+
+ exynos_set_safe_div(base, div, div_mask);
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ return 0;
+}
+
+/*
+ * Helper function to set the 'safe' dividers for the CPU clock. The parameters
+ * div and mask contain the divider value and the register bit mask of the
+ * dividers to be programmed.
+ */
+static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
+ unsigned long mask)
+{
+ unsigned long div0;
+
+ div0 = readl(base + E5433_DIV_CPU0);
+ div0 = (div0 & ~mask) | (div & mask);
+ writel(div0, base + E5433_DIV_CPU0);
+ wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
+}
+
+/* handler for pre-rate change notification from parent clock */
+static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
+ unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
+ unsigned long div0, div1 = 0, mux_reg;
+ unsigned long flags;
+
+ /* find out the divider values to use for clock data */
+ while ((cfg_data->prate * 1000) != ndata->new_rate) {
+ if (cfg_data->prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+
+ spin_lock_irqsave(cpuclk->lock, flags);
+
+ /*
+ * For the selected PLL clock frequency, get the pre-defined divider
+ * values.
+ */
+ div0 = cfg_data->div0;
+ div1 = cfg_data->div1;
+
+ /*
+ * If the old parent clock speed is less than the clock speed of
+ * the alternate parent, then it should be ensured that at no point
+ * the armclk speed is more than the old_prate until the dividers are
+ * set. Also workaround the issue of the dividers being set to lower
+ * values before the parent clock speed is set to new lower speed
+ * (this can result in too high speed of armclk output clocks).
+ */
+ if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
+ unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
+
+ alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
+ WARN_ON(alt_div >= MAX_DIV);
+
+ exynos5433_set_safe_div(base, alt_div, alt_div_mask);
+ div0 |= alt_div;
+ }
+
+ /* select the alternate parent */
+ mux_reg = readl(base + E5433_MUX_SEL2);
+ writel(mux_reg | 1, base + E5433_MUX_SEL2);
+ wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
+
+ /* alternate parent is active now. set the dividers */
+ writel(div0, base + E5433_DIV_CPU0);
+ wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
+
+ writel(div1, base + E5433_DIV_CPU1);
+ wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
+
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ return 0;
+}
+
+/* handler for post-rate change notification from parent clock */
+static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk, void __iomem *base)
+{
+ unsigned long div = 0, div_mask = DIV_MASK;
+ unsigned long mux_reg;
+ unsigned long flags;
+
+ spin_lock_irqsave(cpuclk->lock, flags);
+
+ /* select apll as the alternate parent */
+ mux_reg = readl(base + E5433_MUX_SEL2);
+ writel(mux_reg & ~1, base + E5433_MUX_SEL2);
+ wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
+
+ exynos5433_set_safe_div(base, div, div_mask);
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ return 0;
+}
+
+/*
+ * This notifier function is called for the pre-rate and post-rate change
+ * notifications of the parent clock of cpuclk.
+ */
+static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct clk_notifier_data *ndata = data;
+ struct exynos_cpuclk *cpuclk;
+ void __iomem *base;
+ int err = 0;
+
+ cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
+ base = cpuclk->ctrl_base;
+
+ if (event == PRE_RATE_CHANGE)
+ err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
+ else if (event == POST_RATE_CHANGE)
+ err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
+
+ return notifier_from_errno(err);
+}
+
+/*
+ * This notifier function is called for the pre-rate and post-rate change
+ * notifications of the parent clock of cpuclk.
+ */
+static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct clk_notifier_data *ndata = data;
+ struct exynos_cpuclk *cpuclk;
+ void __iomem *base;
+ int err = 0;
+
+ cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
+ base = cpuclk->ctrl_base;
+
+ if (event == PRE_RATE_CHANGE)
+ err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
+ else if (event == POST_RATE_CHANGE)
+ err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
+
+ return notifier_from_errno(err);
+}
+
+/* helper function to register a CPU clock */
+int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
+ unsigned int lookup_id, const char *name, const char *parent,
+ const char *alt_parent, unsigned long offset,
+ const struct exynos_cpuclk_cfg_data *cfg,
+ unsigned long num_cfgs, unsigned long flags)
+{
+ struct exynos_cpuclk *cpuclk;
+ struct clk_init_data init;
+ struct clk *clk;
+ int ret = 0;
+
+ cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
+ if (!cpuclk)
+ return -ENOMEM;
+
+ init.name = name;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.parent_names = &parent;
+ init.num_parents = 1;
+ init.ops = &exynos_cpuclk_clk_ops;
+
+ cpuclk->hw.init = &init;
+ cpuclk->ctrl_base = ctx->reg_base + offset;
+ cpuclk->lock = &ctx->lock;
+ cpuclk->flags = flags;
+ if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
+ cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
+ else
+ cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
+
+ cpuclk->alt_parent = __clk_lookup(alt_parent);
+ if (!cpuclk->alt_parent) {
+ pr_err("%s: could not lookup alternate parent %s\n",
+ __func__, alt_parent);
+ ret = -EINVAL;
+ goto free_cpuclk;
+ }
+
+ clk = __clk_lookup(parent);
+ if (!clk) {
+ pr_err("%s: could not lookup parent clock %s\n",
+ __func__, parent);
+ ret = -EINVAL;
+ goto free_cpuclk;
+ }
+
+ ret = clk_notifier_register(clk, &cpuclk->clk_nb);
+ if (ret) {
+ pr_err("%s: failed to register clock notifier for %s\n",
+ __func__, name);
+ goto free_cpuclk;
+ }
+
+ cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
+ if (!cpuclk->cfg) {
+ pr_err("%s: could not allocate memory for cpuclk data\n",
+ __func__);
+ ret = -ENOMEM;
+ goto unregister_clk_nb;
+ }
+
+ clk = clk_register(NULL, &cpuclk->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: could not register cpuclk %s\n", __func__, name);
+ ret = PTR_ERR(clk);
+ goto free_cpuclk_data;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, lookup_id);
+ return 0;
+
+free_cpuclk_data:
+ kfree(cpuclk->cfg);
+unregister_clk_nb:
+ clk_notifier_unregister(__clk_lookup(parent), &cpuclk->clk_nb);
+free_cpuclk:
+ kfree(cpuclk);
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all PLL's in Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_CPU_H
+#define __SAMSUNG_CLK_CPU_H
+
+#include "clk.h"
+
+/**
+ * struct exynos_cpuclk_data: config data to setup cpu clocks.
+ * @prate: frequency of the primary parent clock (in KHz).
+ * @div0: value to be programmed in the div_cpu0 register.
+ * @div1: value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for dividers in the CPU
+ * clock domain. The parent frequency at which these divider values are valid is
+ * specified in @prate. The @prate is the frequency of the primary parent clock.
+ * For CPU clock domains that do not have a DIV1 register, the @div1 member
+ * value is not used.
+ */
+struct exynos_cpuclk_cfg_data {
+ unsigned long prate;
+ unsigned long div0;
+ unsigned long div1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw: handle between CCF and CPU clock.
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @lock: cpu clock domain register access lock.
+ * @cfg: cpu clock rate configuration data.
+ * @num_cfgs: number of array elements in @cfg array.
+ * @clk_nb: clock notifier registered for changes in clock speed of the
+ * primary parent clock.
+ * @flags: configuration flags for the CPU clock.
+ *
+ * This structure holds information required for programming the CPU clock for
+ * various clock speeds.
+ */
+struct exynos_cpuclk {
+ struct clk_hw hw;
+ struct clk *alt_parent;
+ void __iomem *ctrl_base;
+ spinlock_t *lock;
+ const struct exynos_cpuclk_cfg_data *cfg;
+ const unsigned long num_cfgs;
+ struct notifier_block clk_nb;
+ unsigned long flags;
+
+/* The CPU clock registers have DIV1 configuration register */
+#define CLK_CPU_HAS_DIV1 (1 << 0)
+/* When ALT parent is active, debug clocks need safe divider values */
+#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
+/* The CPU clock registers have Exynos5433-compatible layout */
+#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
+};
+
+extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
+ unsigned int lookup_id, const char *name,
+ const char *parent, const char *alt_parent,
+ unsigned long offset,
+ const struct exynos_cpuclk_cfg_data *cfg,
+ unsigned long num_cfgs, unsigned long flags);
+
+#endif /* __SAMSUNG_CLK_CPU_H */
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/syscore_ops.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/exynos-audss-clk.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+/*
+ * On Exynos5420 this will be a clock which has to be enabled before any
+ * access to audss registers. Typically a child of EPLL.
+ *
+ * On other platforms this will be -ENODEV.
+ */
+static struct clk *epll;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+#ifdef CONFIG_PM_SLEEP
+static unsigned long reg_save[][2] = {
+ { ASS_CLK_SRC, 0 },
+ { ASS_CLK_DIV, 0 },
+ { ASS_CLK_GATE, 0 },
+};
+
+static int exynos_audss_clk_suspend(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+ reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+ return 0;
+}
+
+static void exynos_audss_clk_resume(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+ writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops exynos_audss_clk_syscore_ops = {
+ .suspend = exynos_audss_clk_suspend,
+ .resume = exynos_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+struct exynos_audss_clk_drvdata {
+ unsigned int has_adma_clk:1;
+ unsigned int has_mst_clk:1;
+ unsigned int enable_epll:1;
+ unsigned int num_clks;
+};
+
+static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
+ .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
+};
+
+static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
+ .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
+ .has_mst_clk = 1,
+};
+
+static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
+ .num_clks = EXYNOS_AUDSS_MAX_CLKS,
+ .has_adma_clk = 1,
+ .enable_epll = 1,
+};
+
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ {
+ .compatible = "samsung,exynos4210-audss-clock",
+ .data = &exynos4210_drvdata,
+ }, {
+ .compatible = "samsung,exynos5250-audss-clock",
+ .data = &exynos4210_drvdata,
+ }, {
+ .compatible = "samsung,exynos5410-audss-clock",
+ .data = &exynos5410_drvdata,
+ }, {
+ .compatible = "samsung,exynos5420-audss-clock",
+ .data = &exynos5420_drvdata,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
+
+static void exynos_audss_clk_teardown(void)
+{
+ int i;
+
+ for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister_mux(clk_table[i]);
+ }
+
+ for (; i < EXYNOS_SRP_CLK; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister_divider(clk_table[i]);
+ }
+
+ for (; i < clk_data.clk_num; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister_gate(clk_table[i]);
+ }
+}
+
+/* register exynos_audss clocks */
+static int exynos_audss_clk_probe(struct platform_device *pdev)
+{
+ const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
+ const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
+ const char *sclk_pcm_p = "sclk_pcm0";
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
+ const struct exynos_audss_clk_drvdata *variant;
+ struct resource *res;
+ int i, ret = 0;
+
+ variant = of_device_get_match_data(&pdev->dev);
+ if (!variant)
+ return -EINVAL;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg_base)) {
+ dev_err(&pdev->dev, "failed to map audss registers\n");
+ return PTR_ERR(reg_base);
+ }
+
+ epll = ERR_PTR(-ENODEV);
+
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ GFP_KERNEL);
+ if (!clk_table)
+ return -ENOMEM;
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = variant->num_clks;
+
+ pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ pll_in = devm_clk_get(&pdev->dev, "pll_in");
+ if (!IS_ERR(pll_ref))
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ if (!IS_ERR(pll_in)) {
+ mout_audss_p[1] = __clk_get_name(pll_in);
+
+ if (variant->enable_epll) {
+ epll = pll_in;
+
+ ret = clk_prepare_enable(epll);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "failed to prepare the epll clock\n");
+ return ret;
+ }
+ }
+ }
+ clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ mout_audss_p, ARRAY_SIZE(mout_audss_p),
+ CLK_SET_RATE_NO_REPARENT,
+ reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
+ cdclk = devm_clk_get(&pdev->dev, "cdclk");
+ sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
+ if (!IS_ERR(cdclk))
+ mout_i2s_p[1] = __clk_get_name(cdclk);
+ if (!IS_ERR(sclk_audio))
+ mout_i2s_p[2] = __clk_get_name(sclk_audio);
+ clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+ mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
+ CLK_SET_RATE_NO_REPARENT,
+ reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+
+ clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+ "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
+ 0, &lock);
+
+ clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ "dout_aud_bus", "dout_srp", 0,
+ reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
+
+ clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+ "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
+ &lock);
+
+ clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+ clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+ "dout_aud_bus", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 2, 0, &lock);
+
+ clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+ "dout_i2s", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 3, 0, &lock);
+
+ clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+ "sclk_pcm", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 4, 0, &lock);
+
+ sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
+ if (!IS_ERR(sclk_pcm_in))
+ sclk_pcm_p = __clk_get_name(sclk_pcm_in);
+ clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+ sclk_pcm_p, CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 5, 0, &lock);
+
+ if (variant->has_adma_clk) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, &lock);
+ }
+
+ for (i = 0; i < clk_data.clk_num; i++) {
+ if (IS_ERR(clk_table[i])) {
+ dev_err(&pdev->dev, "failed to register clock %d\n", i);
+ ret = PTR_ERR(clk_table[i]);
+ goto unregister;
+ }
+ }
+
+ ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ &clk_data);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add clock provider\n");
+ goto unregister;
+ }
+
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+ return 0;
+
+unregister:
+ exynos_audss_clk_teardown();
+
+ if (!IS_ERR(epll))
+ clk_disable_unprepare(epll);
+
+ return ret;
+}
+
+static int exynos_audss_clk_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM_SLEEP
+ unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ exynos_audss_clk_teardown();
+
+ if (!IS_ERR(epll))
+ clk_disable_unprepare(epll);
+
+ return 0;
+}
+
+static struct platform_driver exynos_audss_clk_driver = {
+ .driver = {
+ .name = "exynos-audss-clk",
+ .of_match_table = exynos_audss_clk_of_match,
+ },
+ .probe = exynos_audss_clk_probe,
+ .remove = exynos_audss_clk_remove,
+};
+
+module_platform_driver(exynos_audss_clk_driver);
+
+MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
+MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:exynos-audss-clk");
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Clock driver for Exynos clock output
+ */
+
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#define EXYNOS_CLKOUT_NR_CLKS 1
+#define EXYNOS_CLKOUT_PARENTS 32
+
+#define EXYNOS_PMU_DEBUG_REG 0xa00
+#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
+#define EXYNOS_CLKOUT_MUX_SHIFT 8
+#define EXYNOS4_CLKOUT_MUX_MASK 0xf
+#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
+
+struct exynos_clkout {
+ struct clk_gate gate;
+ struct clk_mux mux;
+ spinlock_t slock;
+ struct clk_onecell_data data;
+ struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
+ void __iomem *reg;
+ u32 pmu_debug_save;
+};
+
+static struct exynos_clkout *clkout;
+
+static int exynos_clkout_suspend(void)
+{
+ clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
+
+ return 0;
+}
+
+static void exynos_clkout_resume(void)
+{
+ writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
+}
+
+static struct syscore_ops exynos_clkout_syscore_ops = {
+ .suspend = exynos_clkout_suspend,
+ .resume = exynos_clkout_resume,
+};
+
+static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
+{
+ const char *parent_names[EXYNOS_CLKOUT_PARENTS];
+ struct clk *parents[EXYNOS_CLKOUT_PARENTS];
+ int parent_count;
+ int ret;
+ int i;
+
+ clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
+ if (!clkout)
+ return;
+
+ spin_lock_init(&clkout->slock);
+
+ parent_count = 0;
+ for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
+ char name[] = "clkoutXX";
+
+ snprintf(name, sizeof(name), "clkout%d", i);
+ parents[i] = of_clk_get_by_name(node, name);
+ if (IS_ERR(parents[i])) {
+ parent_names[i] = "none";
+ continue;
+ }
+
+ parent_names[i] = __clk_get_name(parents[i]);
+ parent_count = i + 1;
+ }
+
+ if (!parent_count)
+ goto free_clkout;
+
+ clkout->reg = of_iomap(node, 0);
+ if (!clkout->reg)
+ goto clks_put;
+
+ clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
+ clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
+ clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
+ clkout->gate.lock = &clkout->slock;
+
+ clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
+ clkout->mux.mask = mux_mask;
+ clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
+ clkout->mux.lock = &clkout->slock;
+
+ clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
+ parent_names, parent_count, &clkout->mux.hw,
+ &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
+ &clk_gate_ops, CLK_SET_RATE_PARENT
+ | CLK_SET_RATE_NO_REPARENT);
+ if (IS_ERR(clkout->clk_table[0]))
+ goto err_unmap;
+
+ clkout->data.clks = clkout->clk_table;
+ clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
+ if (ret)
+ goto err_clk_unreg;
+
+ register_syscore_ops(&exynos_clkout_syscore_ops);
+
+ return;
+
+err_clk_unreg:
+ clk_unregister(clkout->clk_table[0]);
+err_unmap:
+ iounmap(clkout->reg);
+clks_put:
+ for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
+ if (!IS_ERR(parents[i]))
+ clk_put(parents[i]);
+free_clkout:
+ kfree(clkout);
+
+ pr_err("%s: failed to register clkout clock\n", __func__);
+}
+
+/*
+ * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting
+ * the OF_POPULATED flag on the pmu device tree node, so later the
+ * Exynos PMU platform device can be properly probed with PMU driver.
+ */
+
+static void __init exynos4_clkout_init(struct device_node *node)
+{
+ exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
+}
+CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
+ exynos4_clkout_init);
+CLK_OF_DECLARE_DRIVER(exynos4212_clkout, "samsung,exynos4212-pmu",
+ exynos4_clkout_init);
+CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
+ exynos4_clkout_init);
+CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
+ exynos4_clkout_init);
+
+static void __init exynos5_clkout_init(struct device_node *node)
+{
+ exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
+}
+CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu",
+ exynos5_clkout_init);
+CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu",
+ exynos5_clkout_init);
+CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu",
+ exynos5_clkout_init);
+CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu",
+ exynos5_clkout_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos3250 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/exynos3250.h>
+
+#include "clk.h"
+#include "clk-cpu.h"
+#include "clk-pll.h"
+
+#define SRC_LEFTBUS 0x4200
+#define DIV_LEFTBUS 0x4500
+#define GATE_IP_LEFTBUS 0x4800
+#define SRC_RIGHTBUS 0x8200
+#define DIV_RIGHTBUS 0x8500
+#define GATE_IP_RIGHTBUS 0x8800
+#define GATE_IP_PERIR 0x8960
+#define MPLL_LOCK 0xc010
+#define MPLL_CON0 0xc110
+#define VPLL_LOCK 0xc020
+#define VPLL_CON0 0xc120
+#define UPLL_LOCK 0xc030
+#define UPLL_CON0 0xc130
+#define SRC_TOP0 0xc210
+#define SRC_TOP1 0xc214
+#define SRC_CAM 0xc220
+#define SRC_MFC 0xc228
+#define SRC_G3D 0xc22c
+#define SRC_LCD 0xc234
+#define SRC_ISP 0xc238
+#define SRC_FSYS 0xc240
+#define SRC_PERIL0 0xc250
+#define SRC_PERIL1 0xc254
+#define SRC_MASK_TOP 0xc310
+#define SRC_MASK_CAM 0xc320
+#define SRC_MASK_LCD 0xc334
+#define SRC_MASK_ISP 0xc338
+#define SRC_MASK_FSYS 0xc340
+#define SRC_MASK_PERIL0 0xc350
+#define SRC_MASK_PERIL1 0xc354
+#define DIV_TOP 0xc510
+#define DIV_CAM 0xc520
+#define DIV_MFC 0xc528
+#define DIV_G3D 0xc52c
+#define DIV_LCD 0xc534
+#define DIV_ISP 0xc538
+#define DIV_FSYS0 0xc540
+#define DIV_FSYS1 0xc544
+#define DIV_FSYS2 0xc548
+#define DIV_PERIL0 0xc550
+#define DIV_PERIL1 0xc554
+#define DIV_PERIL3 0xc55c
+#define DIV_PERIL4 0xc560
+#define DIV_PERIL5 0xc564
+#define DIV_CAM1 0xc568
+#define CLKDIV2_RATIO 0xc580
+#define GATE_SCLK_CAM 0xc820
+#define GATE_SCLK_MFC 0xc828
+#define GATE_SCLK_G3D 0xc82c
+#define GATE_SCLK_LCD 0xc834
+#define GATE_SCLK_ISP_TOP 0xc838
+#define GATE_SCLK_FSYS 0xc840
+#define GATE_SCLK_PERIL 0xc850
+#define GATE_IP_CAM 0xc920
+#define GATE_IP_MFC 0xc928
+#define GATE_IP_G3D 0xc92c
+#define GATE_IP_LCD 0xc934
+#define GATE_IP_ISP 0xc938
+#define GATE_IP_FSYS 0xc940
+#define GATE_IP_PERIL 0xc950
+#define GATE_BLOCK 0xc970
+#define APLL_LOCK 0x14000
+#define APLL_CON0 0x14100
+#define SRC_CPU 0x14200
+#define DIV_CPU0 0x14500
+#define DIV_CPU1 0x14504
+#define PWR_CTRL1 0x15020
+#define PWR_CTRL2 0x15024
+
+/* Below definitions are used for PWR_CTRL settings */
+#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
+#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
+#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
+#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
+#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+
+static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
+ SRC_LEFTBUS,
+ DIV_LEFTBUS,
+ GATE_IP_LEFTBUS,
+ SRC_RIGHTBUS,
+ DIV_RIGHTBUS,
+ GATE_IP_RIGHTBUS,
+ GATE_IP_PERIR,
+ MPLL_LOCK,
+ MPLL_CON0,
+ VPLL_LOCK,
+ VPLL_CON0,
+ UPLL_LOCK,
+ UPLL_CON0,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_CAM,
+ SRC_MFC,
+ SRC_G3D,
+ SRC_LCD,
+ SRC_ISP,
+ SRC_FSYS,
+ SRC_PERIL0,
+ SRC_PERIL1,
+ SRC_MASK_TOP,
+ SRC_MASK_CAM,
+ SRC_MASK_LCD,
+ SRC_MASK_ISP,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIL0,
+ SRC_MASK_PERIL1,
+ DIV_TOP,
+ DIV_CAM,
+ DIV_MFC,
+ DIV_G3D,
+ DIV_LCD,
+ DIV_ISP,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIL0,
+ DIV_PERIL1,
+ DIV_PERIL3,
+ DIV_PERIL4,
+ DIV_PERIL5,
+ DIV_CAM1,
+ CLKDIV2_RATIO,
+ GATE_SCLK_CAM,
+ GATE_SCLK_MFC,
+ GATE_SCLK_G3D,
+ GATE_SCLK_LCD,
+ GATE_SCLK_ISP_TOP,
+ GATE_SCLK_FSYS,
+ GATE_SCLK_PERIL,
+ GATE_IP_CAM,
+ GATE_IP_MFC,
+ GATE_IP_G3D,
+ GATE_IP_LCD,
+ GATE_IP_ISP,
+ GATE_IP_FSYS,
+ GATE_IP_PERIL,
+ GATE_BLOCK,
+ APLL_LOCK,
+ SRC_CPU,
+ DIV_CPU0,
+ DIV_CPU1,
+ PWR_CTRL1,
+ PWR_CTRL2,
+};
+
+/* list of all parent clock list */
+PNAME(mout_vpllsrc_p) = { "fin_pll", };
+
+PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
+PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
+PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
+
+PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
+PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
+PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
+
+PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
+PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
+
+PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
+PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
+
+PNAME(mout_aclk_400_mcuisp_sub_p)
+ = { "fin_pll", "div_aclk_400_mcuisp", };
+PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
+PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
+PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
+PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
+
+PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
+PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
+PNAME(group_sclk_p) = { "xxti", "xusbxti",
+ "none", "none",
+ "none", "none", "div_mpll_pre",
+ "mout_epll_user", "mout_vpll", };
+PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
+ "none", "none",
+ "xxti", "xusbxti",
+ "div_mpll_pre", "mout_epll_user",
+ "mout_vpll", };
+PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
+ "none", "none", "none",
+ "none", "div_mpll_pre",
+ "mout_epll_user", "mout_vpll",
+ "none", "none", "none",
+ "div_cam_blk_320", };
+PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
+ "m_bitclkhsdiv4_2l", "none",
+ "none", "none", "div_mpll_pre",
+ "mout_epll_user", "mout_vpll",
+ "none", "none", "none",
+ "div_lcd_blk_145", };
+
+PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
+PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
+
+static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
+ FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
+ FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
+ FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
+ FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
+
+ /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
+ FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
+};
+
+static const struct samsung_mux_clock mux_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* SRC_LEFTBUS */
+ MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
+ SRC_LEFTBUS, 4, 1),
+ MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
+
+ /* SRC_RIGHTBUS */
+ MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
+ SRC_RIGHTBUS, 4, 1),
+ MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
+
+ /* SRC_TOP0 */
+ MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
+ MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
+ MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
+ MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
+ MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
+ MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
+ MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
+ MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
+ MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
+ MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
+
+ /* SRC_TOP1 */
+ MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
+ MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
+ SRC_TOP1, 24, 1),
+ MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
+ MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
+ MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
+ MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+
+ /* SRC_CAM */
+ MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
+ MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
+
+ /* SRC_MFC */
+ MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+ MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
+ MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
+
+ /* SRC_G3D */
+ MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+ MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
+ MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
+
+ /* SRC_LCD */
+ MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
+ MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
+
+ /* SRC_ISP */
+ MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
+ MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
+ MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
+
+ /* SRC_FSYS */
+ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+ MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
+ MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+ MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
+
+ /* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
+ MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
+ MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
+
+ /* SRC_PERIL1 */
+ MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
+ MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
+ MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
+
+ /* SRC_CPU */
+ MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
+ SRC_CPU, 24, 1),
+ MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
+ MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock div_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* DIV_LEFTBUS */
+ DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+ DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
+
+ /* DIV_RIGHTBUS */
+ DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+ DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
+
+ /* DIV_TOP */
+ DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
+ DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
+ "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
+ DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
+ DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
+ DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
+ DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
+ DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
+
+ /* DIV_CAM */
+ DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+ DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
+
+ /* DIV_MFC */
+ DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+
+ /* DIV_G3D */
+ DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+
+ /* DIV_LCD */
+ DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
+ DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
+
+ /* DIV_ISP */
+ DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
+ DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
+ DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
+ DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
+ DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
+
+ /* DIV_FSYS0 */
+ DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
+
+ /* DIV_FSYS1 */
+ DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+
+ /* DIV_FSYS2 */
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+ /* DIV_PERIL0 */
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+ DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+ DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+
+ /* DIV_PERIL1 */
+ DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+ DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+
+ /* DIV_PERIL4 */
+ DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
+ DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
+
+ /* DIV_PERIL5 */
+ DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
+
+ /* DIV_CPU0 */
+ DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
+ DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
+ DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
+ DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
+ DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
+ DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
+
+ /* DIV_CPU1 */
+ DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+ DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+};
+
+static const struct samsung_gate_clock gate_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* GATE_IP_LEFTBUS */
+ GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_IP_RIGHTBUS */
+ GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_IP_PERIR */
+ GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
+ GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
+ GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
+ GATE_IP_PERIR, 17, 0, 0),
+ GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
+ GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
+ GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
+ GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
+ GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_SCLK_CAM */
+ GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
+ GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
+ GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
+ GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
+ GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_MFC */
+ GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
+ GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_G3D */
+ GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
+ GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_LCD */
+ GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
+ GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
+ GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
+ GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_ISP_TOP */
+ GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+ GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
+ GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
+ GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
+ GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_FSYS */
+ GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
+ GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
+ GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
+ GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+ GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
+ GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
+ GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_PERIL */
+ GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
+ GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
+ GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
+ GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
+ GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_IP_CAM */
+ GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
+ GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
+ GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
+ GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
+ GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
+ GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
+ GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
+ GATE_IP_CAM, 11, 0, 0),
+ GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
+ GATE_IP_CAM, 9, 0, 0),
+ GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
+ GATE_IP_CAM, 8, 0, 0),
+ GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
+ GATE_IP_CAM, 7, 0, 0),
+ GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
+ GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
+ GATE_IP_CAM, 2, 0, 0),
+ GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
+ GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
+
+ /* GATE_IP_MFC */
+ GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
+ GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
+
+ /* GATE_IP_G3D */
+ GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
+ GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
+
+ /* GATE_IP_LCD */
+ GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
+ GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
+ GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
+ GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
+
+ /* GATE_IP_ISP */
+ GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
+ GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
+ GATE_IP_ISP, 3, 0, 0),
+ GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
+ GATE_IP_ISP, 2, 0, 0),
+ GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
+ GATE_IP_ISP, 1, 0, 0),
+
+ /* GATE_IP_FSYS */
+ GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
+ GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
+ GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
+ GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
+ GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
+ GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
+
+ /* GATE_IP_PERIL */
+ GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
+ GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
+ GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
+ GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
+ GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
+ GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
+ GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
+ GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
+ GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
+ GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
+ GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
+ GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
+ GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
+ GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
+ GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
+};
+
+/* APLL & MPLL & BPLL & UPLL */
+static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
+ PLL_35XX_RATE(1200000000, 400, 4, 1),
+ PLL_35XX_RATE(1100000000, 275, 3, 1),
+ PLL_35XX_RATE(1066000000, 533, 6, 1),
+ PLL_35XX_RATE(1000000000, 250, 3, 1),
+ PLL_35XX_RATE( 960000000, 320, 4, 1),
+ PLL_35XX_RATE( 900000000, 300, 4, 1),
+ PLL_35XX_RATE( 850000000, 425, 6, 1),
+ PLL_35XX_RATE( 800000000, 200, 3, 1),
+ PLL_35XX_RATE( 700000000, 175, 3, 1),
+ PLL_35XX_RATE( 667000000, 667, 12, 1),
+ PLL_35XX_RATE( 600000000, 400, 4, 2),
+ PLL_35XX_RATE( 533000000, 533, 6, 2),
+ PLL_35XX_RATE( 520000000, 260, 3, 2),
+ PLL_35XX_RATE( 500000000, 250, 3, 2),
+ PLL_35XX_RATE( 400000000, 200, 3, 2),
+ PLL_35XX_RATE( 200000000, 200, 3, 3),
+ PLL_35XX_RATE( 100000000, 200, 3, 4),
+ { /* sentinel */ }
+};
+
+/* EPLL */
+static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
+ PLL_36XX_RATE(800000000, 200, 3, 1, 0),
+ PLL_36XX_RATE(288000000, 96, 2, 2, 0),
+ PLL_36XX_RATE(192000000, 128, 2, 3, 0),
+ PLL_36XX_RATE(144000000, 96, 2, 3, 0),
+ PLL_36XX_RATE( 96000000, 128, 2, 4, 0),
+ PLL_36XX_RATE( 84000000, 112, 2, 4, 0),
+ PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
+ PLL_36XX_RATE( 73728000, 98, 2, 4, 19923),
+ PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
+ PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
+ PLL_36XX_RATE( 50000000, 200, 3, 5, 0),
+ PLL_36XX_RATE( 49152002, 131, 2, 5, 4719),
+ PLL_36XX_RATE( 48000000, 128, 2, 5, 0),
+ PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),
+ { /* sentinel */ }
+};
+
+/* VPLL */
+static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
+ PLL_36XX_RATE(600000000, 100, 2, 1, 0),
+ PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
+ PLL_36XX_RATE(519230987, 173, 2, 2, 5046),
+ PLL_36XX_RATE(500000000, 250, 3, 2, 0),
+ PLL_36XX_RATE(445500000, 148, 2, 2, 32768),
+ PLL_36XX_RATE(445055007, 148, 2, 2, 23047),
+ PLL_36XX_RATE(400000000, 200, 3, 2, 0),
+ PLL_36XX_RATE(371250000, 123, 2, 2, 49152),
+ PLL_36XX_RATE(370878997, 185, 3, 2, 28803),
+ PLL_36XX_RATE(340000000, 170, 3, 2, 0),
+ PLL_36XX_RATE(335000015, 111, 2, 2, 43691),
+ PLL_36XX_RATE(333000000, 111, 2, 2, 0),
+ PLL_36XX_RATE(330000000, 110, 2, 2, 0),
+ PLL_36XX_RATE(320000015, 106, 2, 2, 43691),
+ PLL_36XX_RATE(300000000, 100, 2, 2, 0),
+ PLL_36XX_RATE(275000000, 275, 3, 3, 0),
+ PLL_36XX_RATE(222750000, 148, 2, 3, 32768),
+ PLL_36XX_RATE(222528007, 148, 2, 3, 23069),
+ PLL_36XX_RATE(160000000, 160, 3, 3, 0),
+ PLL_36XX_RATE(148500000, 99, 2, 3, 0),
+ PLL_36XX_RATE(148352005, 98, 2, 3, 59070),
+ PLL_36XX_RATE(108000000, 144, 2, 4, 0),
+ PLL_36XX_RATE( 74250000, 99, 2, 4, 0),
+ PLL_36XX_RATE( 74176002, 98, 3, 4, 59070),
+ PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
+ PLL_36XX_RATE( 54000000, 144, 2, 5, 0),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
+ MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
+ PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
+ VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
+ PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
+ UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
+};
+
+static void __init exynos3_core_down_clock(void __iomem *reg_base)
+{
+ unsigned int tmp;
+
+ /*
+ * Enable arm clock down (in idle) and set arm divider
+ * ratios in WFI/WFE state.
+ */
+ tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
+ PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+ PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+ PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+ __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+ /*
+ * Disable the clock up feature on Exynos4x12, in case it was
+ * enabled by bootloader.
+ */
+ __raw_writel(0x0, reg_base + PWR_CTRL2);
+}
+
+static const struct samsung_cmu_info cmu_info __initconst = {
+ .pll_clks = exynos3250_plls,
+ .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
+ .mux_clks = mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mux_clks),
+ .div_clks = div_clks,
+ .nr_div_clks = ARRAY_SIZE(div_clks),
+ .gate_clks = gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(gate_clks),
+ .fixed_factor_clks = fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
+ .nr_clk_ids = CLK_NR_CLKS,
+ .clk_regs = exynos3250_cmu_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
+};
+
+#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
+ (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+ ((corem) << 4))
+#define E3250_CPU_DIV1(hpm, copy) \
+ (((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
+ { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
+ { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
+ { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
+ { 0 },
+};
+
+static void __init exynos3250_cmu_init(struct device_node *np)
+{
+ struct samsung_clk_provider *ctx;
+
+ ctx = samsung_cmu_register_one(np, &cmu_info);
+ if (!ctx)
+ return;
+
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p[0], mout_core_p[1], 0x14200,
+ e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
+ CLK_CPU_HAS_DIV1);
+
+ exynos3_core_down_clock(ctx->reg_base);
+}
+CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define BPLL_LOCK 0x0118
+#define BPLL_CON0 0x0218
+#define BPLL_CON1 0x021c
+#define BPLL_CON2 0x0220
+#define SRC_DMC 0x0300
+#define DIV_DMC1 0x0504
+#define GATE_BUS_DMC0 0x0700
+#define GATE_BUS_DMC1 0x0704
+#define GATE_BUS_DMC2 0x0708
+#define GATE_BUS_DMC3 0x070c
+#define GATE_SCLK_DMC 0x0800
+#define GATE_IP_DMC0 0x0900
+#define GATE_IP_DMC1 0x0904
+#define EPLL_LOCK 0x1110
+#define EPLL_CON0 0x1114
+#define EPLL_CON1 0x1118
+#define EPLL_CON2 0x111c
+#define SRC_EPLL 0x1120
+
+static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
+ BPLL_LOCK,
+ BPLL_CON0,
+ BPLL_CON1,
+ BPLL_CON2,
+ SRC_DMC,
+ DIV_DMC1,
+ GATE_BUS_DMC0,
+ GATE_BUS_DMC1,
+ GATE_BUS_DMC2,
+ GATE_BUS_DMC3,
+ GATE_SCLK_DMC,
+ GATE_IP_DMC0,
+ GATE_IP_DMC1,
+ EPLL_LOCK,
+ EPLL_CON0,
+ EPLL_CON1,
+ EPLL_CON2,
+ SRC_EPLL,
+};
+
+PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
+PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
+PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };
+
+static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* SRC_DMC */
+ MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
+ MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
+ MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
+ MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),
+
+ /* SRC_EPLL */
+ MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
+};
+
+static const struct samsung_div_clock dmc_div_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* DIV_DMC1 */
+ DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
+ DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
+ DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
+ DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
+ DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
+};
+
+static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
+ BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
+ PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
+};
+
+static const struct samsung_cmu_info dmc_cmu_info __initconst = {
+ .pll_clks = exynos3250_dmc_plls,
+ .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
+ .mux_clks = dmc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
+ .div_clks = dmc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(dmc_div_clks),
+ .nr_clk_ids = NR_CLKS_DMC,
+ .clk_regs = exynos3250_cmu_dmc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
+};
+
+static void __init exynos3250_cmu_dmc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &dmc_cmu_info);
+}
+CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
+ exynos3250_cmu_dmc_init);
+
+
+/*
+ * CMU ISP
+ */
+
+#define DIV_ISP0 0x300
+#define DIV_ISP1 0x304
+#define GATE_IP_ISP0 0x800
+#define GATE_IP_ISP1 0x804
+#define GATE_SCLK_ISP 0x900
+
+static const struct samsung_div_clock isp_div_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+ /* DIV_ISP0 */
+ DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
+ DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
+
+ /* DIV_ISP1 */
+ DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
+ DIV_ISP1, 8, 3),
+ DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
+ DIV_ISP1, 4, 3),
+ DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
+};
+
+static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* GATE_IP_ISP0 */
+ GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
+ GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_FD, "fd", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
+ GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_IP_ISP1 */
+ GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
+ GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
+ GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
+ GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
+ GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
+ GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
+ GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
+ GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
+ GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
+ GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
+ GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
+ GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_SCLK_ISP */
+ GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
+ GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info isp_cmu_info __initconst = {
+ .div_clks = isp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(isp_div_clks),
+ .gate_clks = isp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
+ .nr_clk_ids = NR_CLKS_ISP,
+};
+
+static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+
+ samsung_cmu_register_one(np, &isp_cmu_info);
+ return 0;
+}
+
+static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
+ { .compatible = "samsung,exynos3250-cmu-isp", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
+ .driver = {
+ .name = "exynos3250-cmu-isp",
+ .suppress_bind_attrs = true,
+ .of_match_table = exynos3250_cmu_isp_of_match,
+ },
+};
+
+static int __init exynos3250_cmu_platform_init(void)
+{
+ return platform_driver_probe(&exynos3250_cmu_isp_driver,
+ exynos3250_cmu_isp_probe);
+}
+subsys_initcall(exynos3250_cmu_platform_init);
+
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 SoCs.
+*/
+
+#include <dt-bindings/clock/exynos4.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include "clk.h"
+#include "clk-cpu.h"
+
+/* Exynos4 clock controller register offsets */
+#define SRC_LEFTBUS 0x4200
+#define DIV_LEFTBUS 0x4500
+#define GATE_IP_LEFTBUS 0x4800
+#define E4X12_GATE_IP_IMAGE 0x4930
+#define CLKOUT_CMU_LEFTBUS 0x4a00
+#define SRC_RIGHTBUS 0x8200
+#define DIV_RIGHTBUS 0x8500
+#define GATE_IP_RIGHTBUS 0x8800
+#define E4X12_GATE_IP_PERIR 0x8960
+#define CLKOUT_CMU_RIGHTBUS 0x8a00
+#define EPLL_LOCK 0xc010
+#define VPLL_LOCK 0xc020
+#define EPLL_CON0 0xc110
+#define EPLL_CON1 0xc114
+#define EPLL_CON2 0xc118
+#define VPLL_CON0 0xc120
+#define VPLL_CON1 0xc124
+#define VPLL_CON2 0xc128
+#define SRC_TOP0 0xc210
+#define SRC_TOP1 0xc214
+#define SRC_CAM 0xc220
+#define SRC_TV 0xc224
+#define SRC_MFC 0xc228
+#define SRC_G3D 0xc22c
+#define E4210_SRC_IMAGE 0xc230
+#define SRC_LCD0 0xc234
+#define E4210_SRC_LCD1 0xc238
+#define E4X12_SRC_ISP 0xc238
+#define SRC_MAUDIO 0xc23c
+#define SRC_FSYS 0xc240
+#define SRC_PERIL0 0xc250
+#define SRC_PERIL1 0xc254
+#define E4X12_SRC_CAM1 0xc258
+#define SRC_MASK_TOP 0xc310
+#define SRC_MASK_CAM 0xc320
+#define SRC_MASK_TV 0xc324
+#define SRC_MASK_LCD0 0xc334
+#define E4210_SRC_MASK_LCD1 0xc338
+#define E4X12_SRC_MASK_ISP 0xc338
+#define SRC_MASK_MAUDIO 0xc33c
+#define SRC_MASK_FSYS 0xc340
+#define SRC_MASK_PERIL0 0xc350
+#define SRC_MASK_PERIL1 0xc354
+#define DIV_TOP 0xc510
+#define DIV_CAM 0xc520
+#define DIV_TV 0xc524
+#define DIV_MFC 0xc528
+#define DIV_G3D 0xc52c
+#define DIV_IMAGE 0xc530
+#define DIV_LCD0 0xc534
+#define E4210_DIV_LCD1 0xc538
+#define E4X12_DIV_ISP 0xc538
+#define DIV_MAUDIO 0xc53c
+#define DIV_FSYS0 0xc540
+#define DIV_FSYS1 0xc544
+#define DIV_FSYS2 0xc548
+#define DIV_FSYS3 0xc54c
+#define DIV_PERIL0 0xc550
+#define DIV_PERIL1 0xc554
+#define DIV_PERIL2 0xc558
+#define DIV_PERIL3 0xc55c
+#define DIV_PERIL4 0xc560
+#define DIV_PERIL5 0xc564
+#define E4X12_DIV_CAM1 0xc568
+#define E4X12_GATE_BUS_FSYS1 0xc744
+#define GATE_SCLK_CAM 0xc820
+#define GATE_IP_CAM 0xc920
+#define GATE_IP_TV 0xc924
+#define GATE_IP_MFC 0xc928
+#define GATE_IP_G3D 0xc92c
+#define E4210_GATE_IP_IMAGE 0xc930
+#define GATE_IP_LCD0 0xc934
+#define E4210_GATE_IP_LCD1 0xc938
+#define E4X12_GATE_IP_ISP 0xc938
+#define E4X12_GATE_IP_MAUDIO 0xc93c
+#define GATE_IP_FSYS 0xc940
+#define GATE_IP_GPS 0xc94c
+#define GATE_IP_PERIL 0xc950
+#define E4210_GATE_IP_PERIR 0xc960
+#define GATE_BLOCK 0xc970
+#define CLKOUT_CMU_TOP 0xca00
+#define E4X12_MPLL_LOCK 0x10008
+#define E4X12_MPLL_CON0 0x10108
+#define SRC_DMC 0x10200
+#define SRC_MASK_DMC 0x10300
+#define DIV_DMC0 0x10500
+#define DIV_DMC1 0x10504
+#define GATE_IP_DMC 0x10900
+#define CLKOUT_CMU_DMC 0x10a00
+#define APLL_LOCK 0x14000
+#define E4210_MPLL_LOCK 0x14008
+#define APLL_CON0 0x14100
+#define E4210_MPLL_CON0 0x14108
+#define SRC_CPU 0x14200
+#define DIV_CPU0 0x14500
+#define DIV_CPU1 0x14504
+#define GATE_SCLK_CPU 0x14800
+#define GATE_IP_CPU 0x14900
+#define CLKOUT_CMU_CPU 0x14a00
+#define PWR_CTRL1 0x15020
+#define E4X12_PWR_CTRL2 0x15024
+#define E4X12_DIV_ISP0 0x18300
+#define E4X12_DIV_ISP1 0x18304
+#define E4X12_GATE_ISP0 0x18800
+#define E4X12_GATE_ISP1 0x18804
+
+/* Below definitions are used for PWR_CTRL settings */
+#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
+#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
+#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
+#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
+#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+
+/* the exynos4 soc type */
+enum exynos4_soc {
+ EXYNOS4210,
+ EXYNOS4X12,
+};
+
+/* list of PLLs to be registered */
+enum exynos4_plls {
+ apll, mpll, epll, vpll,
+ nr_plls /* number of PLLs */
+};
+
+static void __iomem *reg_base;
+static enum exynos4_soc exynos4_soc;
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4_save_common;
+static struct samsung_clk_reg_dump *exynos4_save_soc;
+static struct samsung_clk_reg_dump *exynos4_save_pll;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static const unsigned long exynos4210_clk_save[] __initconst = {
+ E4210_SRC_IMAGE,
+ E4210_SRC_LCD1,
+ E4210_SRC_MASK_LCD1,
+ E4210_DIV_LCD1,
+ E4210_GATE_IP_IMAGE,
+ E4210_GATE_IP_LCD1,
+ E4210_GATE_IP_PERIR,
+ E4210_MPLL_CON0,
+ PWR_CTRL1,
+};
+
+static const unsigned long exynos4x12_clk_save[] __initconst = {
+ E4X12_GATE_IP_IMAGE,
+ E4X12_GATE_IP_PERIR,
+ E4X12_SRC_CAM1,
+ E4X12_DIV_ISP,
+ E4X12_DIV_CAM1,
+ E4X12_MPLL_CON0,
+ PWR_CTRL1,
+ E4X12_PWR_CTRL2,
+};
+
+static const unsigned long exynos4_clk_pll_regs[] __initconst = {
+ EPLL_LOCK,
+ VPLL_LOCK,
+ EPLL_CON0,
+ EPLL_CON1,
+ EPLL_CON2,
+ VPLL_CON0,
+ VPLL_CON1,
+ VPLL_CON2,
+};
+
+static const unsigned long exynos4_clk_regs[] __initconst = {
+ SRC_LEFTBUS,
+ DIV_LEFTBUS,
+ GATE_IP_LEFTBUS,
+ SRC_RIGHTBUS,
+ DIV_RIGHTBUS,
+ GATE_IP_RIGHTBUS,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_CAM,
+ SRC_TV,
+ SRC_MFC,
+ SRC_G3D,
+ SRC_LCD0,
+ SRC_MAUDIO,
+ SRC_FSYS,
+ SRC_PERIL0,
+ SRC_PERIL1,
+ SRC_MASK_TOP,
+ SRC_MASK_CAM,
+ SRC_MASK_TV,
+ SRC_MASK_LCD0,
+ SRC_MASK_MAUDIO,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIL0,
+ SRC_MASK_PERIL1,
+ DIV_TOP,
+ DIV_CAM,
+ DIV_TV,
+ DIV_MFC,
+ DIV_G3D,
+ DIV_IMAGE,
+ DIV_LCD0,
+ DIV_MAUDIO,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_FSYS3,
+ DIV_PERIL0,
+ DIV_PERIL1,
+ DIV_PERIL2,
+ DIV_PERIL3,
+ DIV_PERIL4,
+ DIV_PERIL5,
+ GATE_SCLK_CAM,
+ GATE_IP_CAM,
+ GATE_IP_TV,
+ GATE_IP_MFC,
+ GATE_IP_G3D,
+ GATE_IP_LCD0,
+ GATE_IP_FSYS,
+ GATE_IP_GPS,
+ GATE_IP_PERIL,
+ GATE_BLOCK,
+ SRC_MASK_DMC,
+ SRC_DMC,
+ DIV_DMC0,
+ DIV_DMC1,
+ GATE_IP_DMC,
+ APLL_CON0,
+ SRC_CPU,
+ DIV_CPU0,
+ DIV_CPU1,
+ GATE_SCLK_CPU,
+ GATE_IP_CPU,
+ CLKOUT_CMU_LEFTBUS,
+ CLKOUT_CMU_RIGHTBUS,
+ CLKOUT_CMU_TOP,
+ CLKOUT_CMU_DMC,
+ CLKOUT_CMU_CPU,
+};
+
+static const struct samsung_clk_reg_dump src_mask_suspend[] = {
+ { .offset = SRC_MASK_TOP, .value = 0x00000001, },
+ { .offset = SRC_MASK_CAM, .value = 0x11111111, },
+ { .offset = SRC_MASK_TV, .value = 0x00000111, },
+ { .offset = SRC_MASK_LCD0, .value = 0x00001111, },
+ { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
+ { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
+ { .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
+ { .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
+ { .offset = SRC_MASK_DMC, .value = 0x00010000, },
+};
+
+static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
+ { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
+};
+
+#define PLL_ENABLED (1 << 31)
+#define PLL_LOCKED (1 << 29)
+
+static void exynos4_clk_wait_for_pll(u32 reg)
+{
+ u32 pll_con;
+
+ pll_con = readl(reg_base + reg);
+ if (!(pll_con & PLL_ENABLED))
+ return;
+
+ while (!(pll_con & PLL_LOCKED)) {
+ cpu_relax();
+ pll_con = readl(reg_base + reg);
+ }
+}
+
+static int exynos4_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, exynos4_save_common,
+ ARRAY_SIZE(exynos4_clk_regs));
+ samsung_clk_save(reg_base, exynos4_save_pll,
+ ARRAY_SIZE(exynos4_clk_pll_regs));
+
+ if (exynos4_soc == EXYNOS4210) {
+ samsung_clk_save(reg_base, exynos4_save_soc,
+ ARRAY_SIZE(exynos4210_clk_save));
+ samsung_clk_restore(reg_base, src_mask_suspend_e4210,
+ ARRAY_SIZE(src_mask_suspend_e4210));
+ } else {
+ samsung_clk_save(reg_base, exynos4_save_soc,
+ ARRAY_SIZE(exynos4x12_clk_save));
+ }
+
+ samsung_clk_restore(reg_base, src_mask_suspend,
+ ARRAY_SIZE(src_mask_suspend));
+
+ return 0;
+}
+
+static void exynos4_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, exynos4_save_pll,
+ ARRAY_SIZE(exynos4_clk_pll_regs));
+
+ exynos4_clk_wait_for_pll(EPLL_CON0);
+ exynos4_clk_wait_for_pll(VPLL_CON0);
+
+ samsung_clk_restore(reg_base, exynos4_save_common,
+ ARRAY_SIZE(exynos4_clk_regs));
+
+ if (exynos4_soc == EXYNOS4210)
+ samsung_clk_restore(reg_base, exynos4_save_soc,
+ ARRAY_SIZE(exynos4210_clk_save));
+ else
+ samsung_clk_restore(reg_base, exynos4_save_soc,
+ ARRAY_SIZE(exynos4x12_clk_save));
+}
+
+static struct syscore_ops exynos4_clk_syscore_ops = {
+ .suspend = exynos4_clk_suspend,
+ .resume = exynos4_clk_resume,
+};
+
+static void __init exynos4_clk_sleep_init(void)
+{
+ exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs,
+ ARRAY_SIZE(exynos4_clk_regs));
+ if (!exynos4_save_common)
+ goto err_warn;
+
+ if (exynos4_soc == EXYNOS4210)
+ exynos4_save_soc = samsung_clk_alloc_reg_dump(
+ exynos4210_clk_save,
+ ARRAY_SIZE(exynos4210_clk_save));
+ else
+ exynos4_save_soc = samsung_clk_alloc_reg_dump(
+ exynos4x12_clk_save,
+ ARRAY_SIZE(exynos4x12_clk_save));
+ if (!exynos4_save_soc)
+ goto err_common;
+
+ exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs,
+ ARRAY_SIZE(exynos4_clk_pll_regs));
+ if (!exynos4_save_pll)
+ goto err_soc;
+
+ register_syscore_ops(&exynos4_clk_syscore_ops);
+ return;
+
+err_soc:
+ kfree(exynos4_save_soc);
+err_common:
+ kfree(exynos4_save_common);
+err_warn:
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+}
+#else
+static void __init exynos4_clk_sleep_init(void) {}
+#endif
+
+/* list of all parent clock list */
+PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
+PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
+PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
+PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
+PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
+PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
+PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
+PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
+PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
+PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
+PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+ "spdif_extclk", };
+PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
+PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
+
+/* Exynos 4210-specific parent groups */
+PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
+PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
+PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
+PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
+ "sclk_usbphy0", "none", "sclk_hdmiphy",
+ "sclk_mpll", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
+ "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+ "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
+ "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+ "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
+ "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+ "sclk_epll", "sclk_vpll", };
+PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
+PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
+PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+ "sclk_usbphy1", "sclk_hdmiphy", "none",
+ "sclk_epll", "sclk_vpll" };
+PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
+ "div_gdl", "div_gpl" };
+PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
+ "div_gdr", "div_gpr" };
+PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
+ "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
+ "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
+ "aclk160", "aclk133", "aclk200", "aclk100",
+ "sclk_mfc", "sclk_g3d", "sclk_g2d",
+ "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
+ "s_rxbyteclkhs0_4l" };
+PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
+ "div_dphy", "none", "div_pwi" };
+PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
+ "none", "arm_clk_div_2", "div_corem0",
+ "div_corem1", "div_corem0", "div_atb",
+ "div_periph", "div_pclk_dbg", "div_hpm" };
+
+/* Exynos 4x12-specific parent groups */
+PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
+PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
+PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
+PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
+PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+ "none", "sclk_hdmiphy", "mout_mpll_user_t",
+ "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
+ "sclk_usbphy0", "xxti", "xusbxti",
+ "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
+ "sclk_usbphy0", "xxti", "xusbxti",
+ "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
+ "sclk_usbphy0", "xxti", "xusbxti",
+ "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
+PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
+PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
+PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
+PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+ "none", "sclk_hdmiphy", "sclk_mpll",
+ "sclk_epll", "sclk_vpll" };
+PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
+ "div_gdl", "div_gpl" };
+PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
+ "div_gdr", "div_gpr" };
+PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
+ "sclk_usbphy0", "none", "sclk_hdmiphy",
+ "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
+ "aclk160", "aclk133", "aclk200", "aclk100",
+ "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
+ "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
+ "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
+ "rx_half_byte_clk_csis1", "div_jpeg",
+ "sclk_pwm_isp", "sclk_spi0_isp",
+ "sclk_spi1_isp", "sclk_uart_isp",
+ "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
+ "sclk_pcm0" };
+PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
+ "div_dmc", "div_dphy", "fout_mpll_div_2",
+ "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
+PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
+ "arm_clk_div_2", "div_corem0", "div_corem1",
+ "div_cores", "div_atb", "div_periph",
+ "div_pclk_dbg", "div_hpm" };
+
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+ FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
+ FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
+ FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
+ FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
+};
+
+static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
+ FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
+};
+
+static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
+ FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
+ FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
+ FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
+};
+
+static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
+};
+
+static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
+ FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
+ FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
+ FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
+};
+
+/* list of mux clocks supported in all exynos4 soc's */
+static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
+ MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
+ "mout_apll"),
+ MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+ MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
+ MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+ MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
+ MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
+ MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
+ MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
+
+ MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
+ MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
+};
+
+/* list of mux clocks supported in exynos4210 soc */
+static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
+ MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+};
+
+static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
+ MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
+ MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
+ CLKOUT_CMU_LEFTBUS, 0, 5),
+
+ MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
+ MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
+ CLKOUT_CMU_RIGHTBUS, 0, 5),
+
+ MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
+ MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
+ MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
+ MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
+ MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
+ MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
+ MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
+ MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
+ MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
+ MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
+ MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
+ MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+ MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
+ MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
+ MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
+ MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
+ MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
+ MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
+ MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
+ MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
+ MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
+ MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
+ MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
+ MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
+ MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
+ MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
+ MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
+ MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
+ MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+ MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
+ MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
+ MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
+ MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
+ MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
+ MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
+ MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
+ MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
+ MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
+ MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
+ MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
+ MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
+
+ MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
+ MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
+
+ MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
+};
+
+/* list of mux clocks supported in exynos4x12 soc */
+static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
+ MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
+ MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
+ MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
+ CLKOUT_CMU_LEFTBUS, 0, 5),
+
+ MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
+ MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
+ MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
+ CLKOUT_CMU_RIGHTBUS, 0, 5),
+
+ MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
+ SRC_CPU, 24, 1),
+ MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
+
+ MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
+ MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
+ MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
+ SRC_TOP1, 12, 1),
+ MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
+ SRC_TOP1, 16, 1),
+ MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
+ MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
+ mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
+ MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
+ MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
+ MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
+ MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
+ MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
+ MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
+ MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
+ MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
+ MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
+ MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
+ MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
+ MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
+ MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
+ MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
+ MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
+ MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
+ MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
+ MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
+ MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
+ MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
+ MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
+ MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
+ MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
+ MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
+ MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
+ MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
+ MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
+ MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+ MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
+ MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
+ MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
+ MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
+ MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
+ MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
+ MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
+ MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
+ MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
+ MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
+ MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
+ MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
+ MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
+ MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
+ MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
+ MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
+
+ MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
+ MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
+ MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
+ MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
+ MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
+ MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
+};
+
+/* list of divider clocks supported in all exynos4 soc's */
+static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
+ DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
+ DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+ DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
+ CLKOUT_CMU_LEFTBUS, 8, 6),
+
+ DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
+ DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+ DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
+ CLKOUT_CMU_RIGHTBUS, 8, 6),
+
+ DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
+ DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
+ DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
+ DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
+ DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
+ DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
+ DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
+ DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+ DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+ DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
+
+ DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
+ DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
+ DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
+ DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
+ DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
+ DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+ DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+ DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+ DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
+ DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
+ DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
+ DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
+ DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+ DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+ DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+ DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+ DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
+ DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
+ DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
+ DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
+ DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
+ DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
+ DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
+ DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
+ DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
+ DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
+ DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
+ DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+ DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+ DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+ DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+ DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
+ DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+ DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
+ DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+ DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
+ DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+ DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
+ DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+ DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+ DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+ DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
+
+ DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
+ DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
+ DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
+ DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
+ DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
+ DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
+ DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
+ DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
+};
+
+/* list of divider clocks supported in exynos4210 soc */
+static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
+ DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+ DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
+ DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
+ DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
+ DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+ DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4x12 soc */
+static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
+ DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
+ DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
+ DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
+ DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
+ DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
+ DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+ DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
+ DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
+ DIV_TOP, 24, 3),
+ DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
+ DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
+ DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
+ DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
+ DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
+ DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
+ DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
+ CLK_GET_RATE_NOCACHE, 0),
+ DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
+ CLK_GET_RATE_NOCACHE, 0),
+ DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
+ DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
+ 4, 3, CLK_GET_RATE_NOCACHE, 0),
+ DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
+ 8, 3, CLK_GET_RATE_NOCACHE, 0),
+ DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
+ DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
+ DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
+};
+
+/* list of gate clocks supported in all exynos4 soc's */
+static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
+ /*
+ * After all Exynos4 based platforms are migrated to use device tree,
+ * the device name and clock alias names specified below for some
+ * of the clocks can be removed.
+ */
+ GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
+ GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
+ GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
+ 0),
+ GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
+ GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
+ GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
+ GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
+ GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
+ GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
+ GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
+ 0),
+ GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
+ GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
+ GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
+ GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
+ GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
+ GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
+ GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
+ GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
+ GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
+ GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
+ GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
+ SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
+ GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
+ GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
+ GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
+ GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
+ GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
+ GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
+ 0, 0),
+ GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
+ 0, 0),
+ GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
+ 0, 0),
+ GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
+ 0, 0),
+ GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
+ 0, 0),
+ GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
+ 0, 0),
+ GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
+ 0, 0),
+ GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
+ 0, 0),
+ GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
+ 0, 0),
+ GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
+ 0, 0),
+ GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
+ 0, 0),
+ GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
+ GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
+ GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
+ GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
+ 0, 0),
+ GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
+ GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
+ GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
+ 0, 0),
+ GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
+ 0, 0),
+ GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
+ GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
+ GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
+ 0, 0),
+ GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
+ 0, 0),
+ GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
+ 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
+ 0, 0),
+ GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
+ 0, 0),
+ GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
+ 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
+ 0, 0),
+ GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
+ 0, 0),
+ GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
+ GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
+ 0, 0),
+ GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
+ 0, 0),
+ GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
+ 0, 0),
+ GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
+ 0, 0),
+ GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
+ 0, 0),
+ GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
+ 0, 0),
+ GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
+ 0, 0),
+ GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
+ 0, 0),
+ GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
+ 0, 0),
+ GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
+ 0, 0),
+ GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
+ 0, 0),
+ GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
+ 0, 0),
+ GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
+ 0, 0),
+ GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
+ 0, 0),
+ GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
+ 0, 0),
+ GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
+ 0, 0),
+ GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
+ 0, 0),
+ GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
+ 0, 0),
+ GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
+ 0, 0),
+ GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
+ 0, 0),
+ GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
+ 0, 0),
+ GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
+ 0, 0),
+ GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
+ 0, 0),
+ GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
+ GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
+ GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
+ GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
+ GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
+
+ GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
+ CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
+ CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
+ CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
+ CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
+ CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of gate clocks supported in exynos4210 soc */
+static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
+ GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
+ GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
+ GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
+ GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
+ GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
+ GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
+ 0),
+ GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
+ 0),
+ GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
+ GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
+ GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
+ GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+ GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
+ GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
+ GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
+ GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+ GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
+ 0),
+ GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
+ E4210_GATE_IP_IMAGE, 4, 0, 0),
+ GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
+ E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+ GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
+ GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
+ 0, 0),
+ GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
+ 0, 0),
+ GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
+ 0, 0),
+ GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
+ 0, 0),
+ GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
+ 0, 0),
+ GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
+ 0),
+};
+
+/* list of gate clocks supported in exynos4x12 soc */
+static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
+ GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
+ GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
+ GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
+ GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+ GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
+ 0),
+ GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
+ 0),
+ GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
+ GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+ GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
+ GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
+ 0),
+ GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
+ SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
+ SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
+ E4X12_GATE_IP_IMAGE, 4, 0, 0),
+ GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
+ 0, 0),
+ GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
+ 0, 0),
+ GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
+ GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
+ E4X12_GATE_IP_ISP, 0, 0, 0),
+ GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
+ E4X12_GATE_IP_ISP, 1, 0, 0),
+ GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
+ E4X12_GATE_IP_ISP, 2, 0, 0),
+ GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
+ E4X12_GATE_IP_ISP, 3, 0, 0),
+ GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
+ GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
+ 0, 0),
+ GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
+ 0, 0),
+ GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
+ CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
+ GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
+ GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
+ GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
+ 0),
+};
+
+static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
+ ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
+ ALIAS(CLK_ARM_CLK, NULL, "armclk"),
+ ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
+};
+
+static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
+ ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
+};
+
+static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
+ ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
+};
+
+/*
+ * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
+ * resides in chipid register space, outside of the clock controller memory
+ * mapped space. So to determine the parent of fin_pll clock, the chipid
+ * controller is first remapped and the value of XOM[0] bit is read to
+ * determine the parent clock.
+ */
+static unsigned long __init exynos4_get_xom(void)
+{
+ unsigned long xom = 0;
+ void __iomem *chipid_base;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
+ if (np) {
+ chipid_base = of_iomap(np, 0);
+
+ if (chipid_base)
+ xom = readl(chipid_base + 8);
+
+ iounmap(chipid_base);
+ }
+
+ return xom;
+}
+
+static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
+{
+ struct samsung_fixed_rate_clock fclk;
+ struct clk *clk;
+ unsigned long finpll_f = 24000000;
+ char *parent_name;
+ unsigned int xom = exynos4_get_xom();
+
+ parent_name = xom & 1 ? "xusbxti" : "xxti";
+ clk = clk_get(NULL, parent_name);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to lookup parent clock %s, assuming "
+ "fin_pll clock frequency is 24MHz\n", __func__,
+ parent_name);
+ } else {
+ finpll_f = clk_get_rate(clk);
+ }
+
+ fclk.id = CLK_FIN_PLL;
+ fclk.name = "fin_pll";
+ fclk.parent_name = NULL;
+ fclk.flags = 0;
+ fclk.fixed_rate = finpll_f;
+ samsung_clk_register_fixed_rate(ctx, &fclk, 1);
+
+}
+
+static const struct of_device_id ext_clk_match[] __initconst = {
+ { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+ { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
+ {},
+};
+
+/* PLLs PMS values */
+static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
+ PLL_45XX_RATE(1200000000, 150, 3, 1, 28),
+ PLL_45XX_RATE(1000000000, 250, 6, 1, 28),
+ PLL_45XX_RATE( 800000000, 200, 6, 1, 28),
+ PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
+ PLL_45XX_RATE( 600000000, 100, 4, 1, 13),
+ PLL_45XX_RATE( 533000000, 533, 24, 1, 5),
+ PLL_45XX_RATE( 500000000, 250, 6, 2, 28),
+ PLL_45XX_RATE( 400000000, 200, 6, 2, 28),
+ PLL_45XX_RATE( 200000000, 200, 6, 3, 28),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
+ PLL_4600_RATE(192000000, 48, 3, 1, 0, 0),
+ PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
+ PLL_4600_RATE(180000000, 45, 3, 1, 0, 0),
+ PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
+ PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
+ PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0),
+ PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
+ PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),
+ PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1),
+ PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
+ PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),
+ PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
+ PLL_35XX_RATE(1500000000, 250, 4, 0),
+ PLL_35XX_RATE(1400000000, 175, 3, 0),
+ PLL_35XX_RATE(1300000000, 325, 6, 0),
+ PLL_35XX_RATE(1200000000, 200, 4, 0),
+ PLL_35XX_RATE(1100000000, 275, 6, 0),
+ PLL_35XX_RATE(1000000000, 125, 3, 0),
+ PLL_35XX_RATE( 900000000, 150, 4, 0),
+ PLL_35XX_RATE( 800000000, 100, 3, 0),
+ PLL_35XX_RATE( 700000000, 175, 3, 1),
+ PLL_35XX_RATE( 600000000, 200, 4, 1),
+ PLL_35XX_RATE( 500000000, 125, 3, 1),
+ PLL_35XX_RATE( 400000000, 100, 3, 1),
+ PLL_35XX_RATE( 300000000, 200, 4, 2),
+ PLL_35XX_RATE( 200000000, 100, 3, 2),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
+ PLL_36XX_RATE(192000000, 48, 3, 1, 0),
+ PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
+ PLL_36XX_RATE(180000000, 45, 3, 1, 0),
+ PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
+ PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
+ PLL_36XX_RATE( 49151992, 49, 3, 3, 9961),
+ PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
+ PLL_36XX_RATE(533000000, 133, 3, 1, 16384),
+ PLL_36XX_RATE(440000000, 110, 3, 1, 0),
+ PLL_36XX_RATE(350000000, 175, 3, 2, 0),
+ PLL_36XX_RATE(266000000, 133, 3, 2, 0),
+ PLL_36XX_RATE(160000000, 160, 3, 3, 0),
+ PLL_36XX_RATE(106031250, 53, 3, 2, 1024),
+ PLL_36XX_RATE( 53015625, 53, 3, 3, 1024),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
+ [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, "fout_apll", NULL),
+ [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
+ E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
+ [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
+ [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
+ VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
+};
+
+static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
+ E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
+ [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, NULL),
+ [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
+ VPLL_LOCK, VPLL_CON0, NULL),
+};
+
+static void __init exynos4x12_core_down_clock(void)
+{
+ unsigned int tmp;
+
+ /*
+ * Enable arm clock down (in idle) and set arm divider
+ * ratios in WFI/WFE state.
+ */
+ tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
+ PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+ PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+ PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+ /* On Exynos4412 enable it also on core 2 and 3 */
+ if (num_possible_cpus() == 4)
+ tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
+ PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
+ writel_relaxed(tmp, reg_base + PWR_CTRL1);
+
+ /*
+ * Disable the clock up feature in case it was enabled by bootloader.
+ */
+ writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
+}
+
+#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
+ (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+ ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4))
+#define E4210_CPU_DIV1(hpm, copy) \
+ (((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
+
+static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
+ { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
+ { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
+ { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
+ { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
+ { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
+ { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
+ { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
+ { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
+ { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
+ { 0 },
+};
+
+#define E4412_CPU_DIV1(cores, hpm, copy) \
+ (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
+ { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
+ { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
+ { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
+ { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
+ { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
+ { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
+ { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
+ { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
+ { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
+ { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
+ { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
+ { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
+ { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
+ { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
+ { 0 },
+};
+
+/* register exynos4 clocks */
+static void __init exynos4_clk_init(struct device_node *np,
+ enum exynos4_soc soc)
+{
+ struct samsung_clk_provider *ctx;
+ exynos4_soc = soc;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
+ ext_clk_match);
+
+ exynos4_clk_register_finpll(ctx);
+
+ if (exynos4_soc == EXYNOS4210) {
+ samsung_clk_register_mux(ctx, exynos4210_mux_early,
+ ARRAY_SIZE(exynos4210_mux_early));
+
+ if (_get_rate("fin_pll") == 24000000) {
+ exynos4210_plls[apll].rate_table =
+ exynos4210_apll_rates;
+ exynos4210_plls[epll].rate_table =
+ exynos4210_epll_rates;
+ }
+
+ if (_get_rate("mout_vpllsrc") == 24000000)
+ exynos4210_plls[vpll].rate_table =
+ exynos4210_vpll_rates;
+
+ samsung_clk_register_pll(ctx, exynos4210_plls,
+ ARRAY_SIZE(exynos4210_plls), reg_base);
+ } else {
+ if (_get_rate("fin_pll") == 24000000) {
+ exynos4x12_plls[apll].rate_table =
+ exynos4x12_apll_rates;
+ exynos4x12_plls[epll].rate_table =
+ exynos4x12_epll_rates;
+ exynos4x12_plls[vpll].rate_table =
+ exynos4x12_vpll_rates;
+ }
+
+ samsung_clk_register_pll(ctx, exynos4x12_plls,
+ ARRAY_SIZE(exynos4x12_plls), reg_base);
+ }
+
+ samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
+ ARRAY_SIZE(exynos4_fixed_rate_clks));
+ samsung_clk_register_mux(ctx, exynos4_mux_clks,
+ ARRAY_SIZE(exynos4_mux_clks));
+ samsung_clk_register_div(ctx, exynos4_div_clks,
+ ARRAY_SIZE(exynos4_div_clks));
+ samsung_clk_register_gate(ctx, exynos4_gate_clks,
+ ARRAY_SIZE(exynos4_gate_clks));
+ samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
+ ARRAY_SIZE(exynos4_fixed_factor_clks));
+
+ if (exynos4_soc == EXYNOS4210) {
+ samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
+ ARRAY_SIZE(exynos4210_fixed_rate_clks));
+ samsung_clk_register_mux(ctx, exynos4210_mux_clks,
+ ARRAY_SIZE(exynos4210_mux_clks));
+ samsung_clk_register_div(ctx, exynos4210_div_clks,
+ ARRAY_SIZE(exynos4210_div_clks));
+ samsung_clk_register_gate(ctx, exynos4210_gate_clks,
+ ARRAY_SIZE(exynos4210_gate_clks));
+ samsung_clk_register_alias(ctx, exynos4210_aliases,
+ ARRAY_SIZE(exynos4210_aliases));
+ samsung_clk_register_fixed_factor(ctx,
+ exynos4210_fixed_factor_clks,
+ ARRAY_SIZE(exynos4210_fixed_factor_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+ e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ } else {
+ samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
+ ARRAY_SIZE(exynos4x12_mux_clks));
+ samsung_clk_register_div(ctx, exynos4x12_div_clks,
+ ARRAY_SIZE(exynos4x12_div_clks));
+ samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
+ ARRAY_SIZE(exynos4x12_gate_clks));
+ samsung_clk_register_alias(ctx, exynos4x12_aliases,
+ ARRAY_SIZE(exynos4x12_aliases));
+ samsung_clk_register_fixed_factor(ctx,
+ exynos4x12_fixed_factor_clks,
+ ARRAY_SIZE(exynos4x12_fixed_factor_clks));
+ if (of_machine_is_compatible("samsung,exynos4412")) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+ e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+ e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ }
+ }
+
+ samsung_clk_register_alias(ctx, exynos4_aliases,
+ ARRAY_SIZE(exynos4_aliases));
+
+ if (soc == EXYNOS4X12)
+ exynos4x12_core_down_clock();
+ exynos4_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
+ "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
+ exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
+ _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
+ _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
+ _get_rate("div_core2"));
+}
+
+
+static void __init exynos4210_clk_init(struct device_node *np)
+{
+ exynos4_clk_init(np, EXYNOS4210);
+}
+CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
+
+static void __init exynos4412_clk_init(struct device_node *np)
+{
+ exynos4_clk_init(np, EXYNOS4X12);
+}
+CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos4415 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/exynos4415.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_LEFTBUS 0x4200
+#define DIV_LEFTBUS 0x4500
+#define GATE_IP_LEFTBUS 0x4800
+#define GATE_IP_IMAGE 0x4930
+#define SRC_RIGHTBUS 0x8200
+#define DIV_RIGHTBUS 0x8500
+#define GATE_IP_RIGHTBUS 0x8800
+#define GATE_IP_PERIR 0x8960
+#define EPLL_LOCK 0xc010
+#define G3D_PLL_LOCK 0xc020
+#define DISP_PLL_LOCK 0xc030
+#define ISP_PLL_LOCK 0xc040
+#define EPLL_CON0 0xc110
+#define EPLL_CON1 0xc114
+#define EPLL_CON2 0xc118
+#define G3D_PLL_CON0 0xc120
+#define G3D_PLL_CON1 0xc124
+#define G3D_PLL_CON2 0xc128
+#define ISP_PLL_CON0 0xc130
+#define ISP_PLL_CON1 0xc134
+#define ISP_PLL_CON2 0xc138
+#define DISP_PLL_CON0 0xc140
+#define DISP_PLL_CON1 0xc144
+#define DISP_PLL_CON2 0xc148
+#define SRC_TOP0 0xc210
+#define SRC_TOP1 0xc214
+#define SRC_CAM 0xc220
+#define SRC_TV 0xc224
+#define SRC_MFC 0xc228
+#define SRC_G3D 0xc22c
+#define SRC_LCD 0xc234
+#define SRC_ISP 0xc238
+#define SRC_MAUDIO 0xc23c
+#define SRC_FSYS 0xc240
+#define SRC_PERIL0 0xc250
+#define SRC_PERIL1 0xc254
+#define SRC_CAM1 0xc258
+#define SRC_TOP_ISP0 0xc25c
+#define SRC_TOP_ISP1 0xc260
+#define SRC_MASK_TOP 0xc310
+#define SRC_MASK_CAM 0xc320
+#define SRC_MASK_TV 0xc324
+#define SRC_MASK_LCD 0xc334
+#define SRC_MASK_ISP 0xc338
+#define SRC_MASK_MAUDIO 0xc33c
+#define SRC_MASK_FSYS 0xc340
+#define SRC_MASK_PERIL0 0xc350
+#define SRC_MASK_PERIL1 0xc354
+#define DIV_TOP 0xc510
+#define DIV_CAM 0xc520
+#define DIV_TV 0xc524
+#define DIV_MFC 0xc528
+#define DIV_G3D 0xc52c
+#define DIV_LCD 0xc534
+#define DIV_ISP 0xc538
+#define DIV_MAUDIO 0xc53c
+#define DIV_FSYS0 0xc540
+#define DIV_FSYS1 0xc544
+#define DIV_FSYS2 0xc548
+#define DIV_PERIL0 0xc550
+#define DIV_PERIL1 0xc554
+#define DIV_PERIL2 0xc558
+#define DIV_PERIL3 0xc55c
+#define DIV_PERIL4 0xc560
+#define DIV_PERIL5 0xc564
+#define DIV_CAM1 0xc568
+#define DIV_TOP_ISP1 0xc56c
+#define DIV_TOP_ISP0 0xc570
+#define CLKDIV2_RATIO 0xc580
+#define GATE_SCLK_CAM 0xc820
+#define GATE_SCLK_TV 0xc824
+#define GATE_SCLK_MFC 0xc828
+#define GATE_SCLK_G3D 0xc82c
+#define GATE_SCLK_LCD 0xc834
+#define GATE_SCLK_MAUDIO 0xc83c
+#define GATE_SCLK_FSYS 0xc840
+#define GATE_SCLK_PERIL 0xc850
+#define GATE_IP_CAM 0xc920
+#define GATE_IP_TV 0xc924
+#define GATE_IP_MFC 0xc928
+#define GATE_IP_G3D 0xc92c
+#define GATE_IP_LCD 0xc934
+#define GATE_IP_FSYS 0xc940
+#define GATE_IP_PERIL 0xc950
+#define GATE_BLOCK 0xc970
+#define APLL_LOCK 0x14000
+#define APLL_CON0 0x14100
+#define SRC_CPU 0x14200
+#define DIV_CPU0 0x14500
+#define DIV_CPU1 0x14504
+
+static const unsigned long exynos4415_cmu_clk_regs[] __initconst = {
+ SRC_LEFTBUS,
+ DIV_LEFTBUS,
+ GATE_IP_LEFTBUS,
+ GATE_IP_IMAGE,
+ SRC_RIGHTBUS,
+ DIV_RIGHTBUS,
+ GATE_IP_RIGHTBUS,
+ GATE_IP_PERIR,
+ EPLL_LOCK,
+ G3D_PLL_LOCK,
+ DISP_PLL_LOCK,
+ ISP_PLL_LOCK,
+ EPLL_CON0,
+ EPLL_CON1,
+ EPLL_CON2,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_CON2,
+ ISP_PLL_CON0,
+ ISP_PLL_CON1,
+ ISP_PLL_CON2,
+ DISP_PLL_CON0,
+ DISP_PLL_CON1,
+ DISP_PLL_CON2,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_CAM,
+ SRC_TV,
+ SRC_MFC,
+ SRC_G3D,
+ SRC_LCD,
+ SRC_ISP,
+ SRC_MAUDIO,
+ SRC_FSYS,
+ SRC_PERIL0,
+ SRC_PERIL1,
+ SRC_CAM1,
+ SRC_TOP_ISP0,
+ SRC_TOP_ISP1,
+ SRC_MASK_TOP,
+ SRC_MASK_CAM,
+ SRC_MASK_TV,
+ SRC_MASK_LCD,
+ SRC_MASK_ISP,
+ SRC_MASK_MAUDIO,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIL0,
+ SRC_MASK_PERIL1,
+ DIV_TOP,
+ DIV_CAM,
+ DIV_TV,
+ DIV_MFC,
+ DIV_G3D,
+ DIV_LCD,
+ DIV_ISP,
+ DIV_MAUDIO,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIL0,
+ DIV_PERIL1,
+ DIV_PERIL2,
+ DIV_PERIL3,
+ DIV_PERIL4,
+ DIV_PERIL5,
+ DIV_CAM1,
+ DIV_TOP_ISP1,
+ DIV_TOP_ISP0,
+ CLKDIV2_RATIO,
+ GATE_SCLK_CAM,
+ GATE_SCLK_TV,
+ GATE_SCLK_MFC,
+ GATE_SCLK_G3D,
+ GATE_SCLK_LCD,
+ GATE_SCLK_MAUDIO,
+ GATE_SCLK_FSYS,
+ GATE_SCLK_PERIL,
+ GATE_IP_CAM,
+ GATE_IP_TV,
+ GATE_IP_MFC,
+ GATE_IP_G3D,
+ GATE_IP_LCD,
+ GATE_IP_FSYS,
+ GATE_IP_PERIL,
+ GATE_BLOCK,
+ APLL_LOCK,
+ APLL_CON0,
+ SRC_CPU,
+ DIV_CPU0,
+ DIV_CPU1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
+
+PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
+PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
+PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
+PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
+
+PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
+PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
+PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
+
+PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
+PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_g3d_pll", };
+
+PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
+PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
+
+PNAME(mout_aclk_266_p) = { "mout_mpll_user_t", "mout_g3d_pll", };
+
+PNAME(group_epll_g3dpll_p) = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_sclk_p) = { "xxti", "xusbxti",
+ "none", "mout_isp_pll",
+ "none", "none", "div_mpll_pre",
+ "mout_epll", "mout_g3d_pll", };
+PNAME(group_spdif_p) = { "mout_audio0", "mout_audio1",
+ "mout_audio2", "spdif_extclk", };
+PNAME(group_sclk_audio2_p) = { "audiocdclk2", "none",
+ "none", "mout_isp_pll",
+ "mout_disp_pll", "xusbxti",
+ "div_mpll_pre", "mout_epll",
+ "mout_g3d_pll", };
+PNAME(group_sclk_audio1_p) = { "audiocdclk1", "none",
+ "none", "mout_isp_pll",
+ "mout_disp_pll", "xusbxti",
+ "div_mpll_pre", "mout_epll",
+ "mout_g3d_pll", };
+PNAME(group_sclk_audio0_p) = { "audiocdclk0", "none",
+ "none", "mout_isp_pll",
+ "mout_disp_pll", "xusbxti",
+ "div_mpll_pre", "mout_epll",
+ "mout_g3d_pll", };
+PNAME(group_fimc_lclk_p) = { "xxti", "xusbxti",
+ "none", "mout_isp_pll",
+ "none", "mout_disp_pll",
+ "mout_mpll_user_t", "mout_epll",
+ "mout_g3d_pll", };
+PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
+ "m_bitclkhsdiv4_4l", "mout_isp_pll",
+ "mout_disp_pll", "sclk_hdmiphy",
+ "div_mpll_pre", "mout_epll",
+ "mout_g3d_pll", };
+PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy" };
+PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
+PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
+PNAME(mout_jpeg_p) = { "mout_jpeg_0", "mout_jpeg_1" };
+PNAME(mout_jpeg1_p) = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_aclk_isp0_300_p) = { "mout_isp_pll", "div_mpll_pre" };
+PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
+PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
+PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
+PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
+
+static const struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initconst = {
+ /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
+ FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
+};
+
+static const struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initconst = {
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
+};
+
+static const struct samsung_mux_clock exynos4415_mux_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* SRC_LEFTBUS */
+ MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
+ SRC_LEFTBUS, 4, 1),
+ MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
+
+ /* SRC_RIGHTBUS */
+ MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
+ SRC_RIGHTBUS, 4, 1),
+ MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
+
+ /* SRC_TOP0 */
+ MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
+ MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
+ SRC_TOP0, 24, 1),
+ MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
+ SRC_TOP0, 20, 1),
+ MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
+ SRC_TOP0, 16, 1),
+ MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
+ SRC_TOP0, 12, 1),
+ MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+ SRC_TOP0, 8, 1),
+ MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
+ MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
+
+ /* SRC_TOP1 */
+ MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
+ SRC_TOP1, 28, 1),
+ MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+ SRC_TOP1, 16, 1),
+ MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
+ SRC_TOP1, 12, 1),
+ MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
+ group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
+ MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
+ SRC_TOP1, 0, 1),
+
+ /* SRC_CAM */
+ MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
+ MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
+ MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
+ MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
+ 12, 4),
+ MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
+ 8, 4),
+ MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
+ 4, 4),
+ MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
+ 0, 4),
+
+ /* SRC_TV */
+ MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+
+ /* SRC_MFC */
+ MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+ MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
+ MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
+ 1),
+
+ /* SRC_G3D */
+ MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+ MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
+ MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
+ 1),
+
+ /* SRC_LCD */
+ MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
+ MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
+
+ /* SRC_ISP */
+ MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
+ 16, 4),
+ MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
+ 12, 4),
+ MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
+ 8, 4),
+ MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
+ 4, 4),
+ MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
+ 0, 4),
+
+ /* SRC_MAUDIO */
+ MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
+ 0, 4),
+
+ /* SRC_FSYS */
+ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+ MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
+ MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+ MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
+
+ /* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
+ MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
+ MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
+
+ /* SRC_PERIL1 */
+ MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
+ MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
+ MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
+ MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
+ MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
+ 4, 4),
+ MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
+ 0, 4),
+
+ /* SRC_CPU */
+ MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
+ SRC_CPU, 24, 1),
+ MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
+ MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
+ MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
+
+ /* SRC_CAM1 */
+ MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
+ group_fimc_lclk_p, SRC_CAM1, 20, 1),
+ MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
+ group_fimc_lclk_p, SRC_CAM1, 16, 1),
+ MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
+ MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
+ MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
+ 0, 1),
+
+ /* SRC_TOP_ISP0 */
+ MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
+ group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
+ MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
+ group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
+ MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
+ group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
+
+ /* SRC_TOP_ISP1 */
+ MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
+ group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
+ MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
+ group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
+};
+
+static const struct samsung_div_clock exynos4415_div_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* DIV_LEFTBUS */
+ DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+ DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
+
+ /* DIV_RIGHTBUS */
+ DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+ DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
+
+ /* DIV_TOP */
+ DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
+ "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
+ DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
+ DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
+ DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
+ DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
+ DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
+
+ /* DIV_CAM */
+ DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+ DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+ DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+ DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
+ 12, 4),
+ DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
+ 8, 4),
+ DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
+ 4, 4),
+ DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
+ 0, 4),
+
+ /* DIV_TV */
+ DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
+
+ /* DIV_MFC */
+ DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+
+ /* DIV_G3D */
+ DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+
+ /* DIV_LCD */
+ DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
+ DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
+
+ /* DIV_ISP */
+ DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
+ DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
+ DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
+ DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
+ DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
+ DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
+
+ /* DIV_MAUDIO */
+ DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
+ DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+
+ /* DIV_FSYS0 */
+ DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
+
+ /* DIV_FSYS1 */
+ DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+
+ /* DIV_FSYS2 */
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
+ CLK_SET_RATE_PARENT, 0),
+
+ /* DIV_PERIL0 */
+ DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+ DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+ DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+
+ /* DIV_PERIL1 */
+ DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+ DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+
+ /* DIV_PERIL2 */
+ DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+
+ /* DIV_PERIL4 */
+ DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
+ DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+ DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
+ DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+
+ /* DIV_PERIL5 */
+ DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
+
+ /* DIV_CAM1 */
+ DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
+ "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
+ DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
+ "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
+ DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
+
+ /* DIV_CPU0 */
+ DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
+ DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
+ DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
+ DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
+ DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
+ DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
+ DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+
+ /* DIV_CPU1 */
+ DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+ DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+};
+
+static const struct samsung_gate_clock exynos4415_gate_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by register address in ascending
+ * order and then bitfield shift in descending order, as it is done
+ * in the User's Manual. When adding new entries, please make sure
+ * that the order is preserved, to avoid merge conflicts and make
+ * further work with defined data easier.
+ */
+
+ /* GATE_IP_LEFTBUS */
+ GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_IP_IMAGE */
+ GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
+ 9, 0, 0),
+ GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
+ 8, 0, 0),
+ GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
+ 7, 0, 0),
+ GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
+ 5, 0, 0),
+ GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
+ 4, 0, 0),
+ GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
+ GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
+
+ /* GATE_IP_RIGHTBUS */
+ GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
+ GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_IP_PERIR */
+ GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
+ GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
+ GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
+ GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
+ GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
+ GATE_IP_PERIR, 17, 0, 0),
+ GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
+ GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
+ GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
+ GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
+ GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* GATE_SCLK_CAM - non-completed */
+ GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
+ "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
+ "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
+ 10, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
+ GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
+ GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
+ GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+ GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
+ GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
+ GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
+ GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
+ GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_TV */
+ GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
+ GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
+ GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
+ GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_MFC */
+ GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
+ GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_G3D */
+ GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
+ GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_LCD */
+ GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
+ GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
+ GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
+ GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
+ GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_MAUDIO */
+ GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
+ GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
+ GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_FSYS */
+ GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
+ GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
+ GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+ GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
+ GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
+ GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_SCLK_PERIL */
+ GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
+ GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
+ GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
+ GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
+ GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
+ GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
+ GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
+ GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
+ GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
+ GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+ GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* GATE_IP_CAM */
+ GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
+ 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
+ GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
+ GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
+ GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
+ GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
+ GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
+ GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
+ GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
+ GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
+ GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
+ GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
+ GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
+
+ /* GATE_IP_TV */
+ GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
+ GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
+ GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
+ GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
+ GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
+
+ /* GATE_IP_MFC */
+ GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
+ GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
+ GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
+
+ /* GATE_IP_G3D */
+ GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
+
+ /* GATE_IP_LCD */
+ GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
+ GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
+ GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
+ GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
+ GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
+
+ /* GATE_IP_FSYS */
+ GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
+ GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
+ GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
+ 0, 0),
+ GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
+ GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
+ GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
+ GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
+
+ /* GATE_IP_PERIL */
+ GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
+ GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
+ GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
+ GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
+ GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
+ GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
+ GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
+ GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
+ GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
+ GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
+ GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
+ GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
+ GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
+ GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
+ GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
+ GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
+ GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
+ GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
+ GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
+};
+
+/*
+ * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
+ */
+static const struct samsung_pll_rate_table exynos4415_pll_rates[] __initconst = {
+ PLL_35XX_RATE(1600000000, 400, 3, 1),
+ PLL_35XX_RATE(1500000000, 250, 2, 1),
+ PLL_35XX_RATE(1400000000, 175, 3, 0),
+ PLL_35XX_RATE(1300000000, 325, 3, 1),
+ PLL_35XX_RATE(1200000000, 400, 4, 1),
+ PLL_35XX_RATE(1100000000, 275, 3, 1),
+ PLL_35XX_RATE(1066000000, 533, 6, 1),
+ PLL_35XX_RATE(1000000000, 250, 3, 1),
+ PLL_35XX_RATE(960000000, 320, 4, 1),
+ PLL_35XX_RATE(900000000, 300, 4, 1),
+ PLL_35XX_RATE(850000000, 425, 6, 1),
+ PLL_35XX_RATE(800000000, 200, 3, 1),
+ PLL_35XX_RATE(700000000, 175, 3, 1),
+ PLL_35XX_RATE(667000000, 667, 12, 1),
+ PLL_35XX_RATE(600000000, 400, 4, 2),
+ PLL_35XX_RATE(550000000, 275, 3, 2),
+ PLL_35XX_RATE(533000000, 533, 6, 2),
+ PLL_35XX_RATE(520000000, 260, 3, 2),
+ PLL_35XX_RATE(500000000, 250, 3, 2),
+ PLL_35XX_RATE(440000000, 220, 3, 2),
+ PLL_35XX_RATE(400000000, 200, 3, 2),
+ PLL_35XX_RATE(350000000, 175, 3, 2),
+ PLL_35XX_RATE(300000000, 300, 3, 3),
+ PLL_35XX_RATE(266000000, 266, 3, 3),
+ PLL_35XX_RATE(200000000, 200, 3, 3),
+ PLL_35XX_RATE(160000000, 160, 3, 3),
+ PLL_35XX_RATE(100000000, 200, 3, 4),
+ { /* sentinel */ }
+};
+
+/* EPLL */
+static const struct samsung_pll_rate_table exynos4415_epll_rates[] __initconst = {
+ PLL_36XX_RATE(800000000, 200, 3, 1, 0),
+ PLL_36XX_RATE(288000000, 96, 2, 2, 0),
+ PLL_36XX_RATE(192000000, 128, 2, 3, 0),
+ PLL_36XX_RATE(144000000, 96, 2, 3, 0),
+ PLL_36XX_RATE(96000000, 128, 2, 4, 0),
+ PLL_36XX_RATE(84000000, 112, 2, 4, 0),
+ PLL_36XX_RATE(80750011, 107, 2, 4, 43691),
+ PLL_36XX_RATE(73728004, 98, 2, 4, 19923),
+ PLL_36XX_RATE(67987602, 271, 3, 5, 62285),
+ PLL_36XX_RATE(65911004, 175, 2, 5, 49982),
+ PLL_36XX_RATE(50000000, 200, 3, 5, 0),
+ PLL_36XX_RATE(49152003, 131, 2, 5, 4719),
+ PLL_36XX_RATE(48000000, 128, 2, 5, 0),
+ PLL_36XX_RATE(45250000, 181, 3, 5, 0),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_clock exynos4415_plls[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
+ PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates),
+ PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
+ G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
+ ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
+ "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
+};
+
+static const struct samsung_cmu_info cmu_info __initconst = {
+ .pll_clks = exynos4415_plls,
+ .nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
+ .mux_clks = exynos4415_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
+ .div_clks = exynos4415_div_clks,
+ .nr_div_clks = ARRAY_SIZE(exynos4415_div_clks),
+ .gate_clks = exynos4415_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks),
+ .fixed_clks = exynos4415_fixed_rate_clks,
+ .nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks),
+ .fixed_factor_clks = exynos4415_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks),
+ .nr_clk_ids = CLK_NR_CLKS,
+ .clk_regs = exynos4415_cmu_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs),
+};
+
+static void __init exynos4415_cmu_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cmu_info);
+}
+CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define MPLL_LOCK 0x008
+#define MPLL_CON0 0x108
+#define MPLL_CON1 0x10c
+#define MPLL_CON2 0x110
+#define BPLL_LOCK 0x118
+#define BPLL_CON0 0x218
+#define BPLL_CON1 0x21c
+#define BPLL_CON2 0x220
+#define SRC_DMC 0x300
+#define DIV_DMC1 0x504
+
+static const unsigned long exynos4415_cmu_dmc_clk_regs[] __initconst = {
+ MPLL_LOCK,
+ MPLL_CON0,
+ MPLL_CON1,
+ MPLL_CON2,
+ BPLL_LOCK,
+ BPLL_CON0,
+ BPLL_CON1,
+ BPLL_CON2,
+ SRC_DMC,
+ DIV_DMC1,
+};
+
+PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
+
+static const struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initconst = {
+ MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
+ MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
+ MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
+ MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
+};
+
+static const struct samsung_div_clock exynos4415_dmc_div_clks[] __initconst = {
+ DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
+ DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
+ DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
+ DIV_DMC1, 19, 2),
+ DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
+ DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
+ DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
+};
+
+static const struct samsung_pll_clock exynos4415_dmc_plls[] __initconst = {
+ PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
+ MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
+ PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
+ BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
+};
+
+static const struct samsung_cmu_info cmu_dmc_info __initconst = {
+ .pll_clks = exynos4415_dmc_plls,
+ .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
+ .mux_clks = exynos4415_dmc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks),
+ .div_clks = exynos4415_dmc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks),
+ .nr_clk_ids = NR_CLKS_DMC,
+ .clk_regs = exynos4415_cmu_dmc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs),
+};
+
+static void __init exynos4415_cmu_dmc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cmu_dmc_info);
+}
+CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
+ exynos4415_cmu_dmc_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5250 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5250.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include "clk.h"
+#include "clk-cpu.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define PWR_CTRL1 0x1020
+#define PWR_CTRL2 0x1024
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define SRC_CORE1 0x4204
+#define GATE_IP_ACP 0x8800
+#define GATE_IP_ISP0 0xc800
+#define GATE_IP_ISP1 0xc804
+#define CPLL_LOCK 0x10020
+#define EPLL_LOCK 0x10030
+#define VPLL_LOCK 0x10040
+#define GPLL_LOCK 0x10050
+#define CPLL_CON0 0x10120
+#define EPLL_CON0 0x10130
+#define VPLL_CON0 0x10140
+#define GPLL_CON0 0x10150
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_TOP3 0x1021c
+#define SRC_GSCL 0x10220
+#define SRC_DISP1_0 0x1022c
+#define SRC_MAU 0x10240
+#define SRC_FSYS 0x10244
+#define SRC_GEN 0x10248
+#define SRC_PERIC0 0x10250
+#define SRC_PERIC1 0x10254
+#define SRC_MASK_GSCL 0x10320
+#define SRC_MASK_DISP1_0 0x1032c
+#define SRC_MASK_MAU 0x10334
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_GEN 0x10344
+#define SRC_MASK_PERIC0 0x10350
+#define SRC_MASK_PERIC1 0x10354
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_GSCL 0x10520
+#define DIV_DISP1_0 0x1052c
+#define DIV_GEN 0x1053c
+#define DIV_MAU 0x10544
+#define DIV_FSYS0 0x10548
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define DIV_PERIC1 0x1055c
+#define DIV_PERIC2 0x10560
+#define DIV_PERIC3 0x10564
+#define DIV_PERIC4 0x10568
+#define DIV_PERIC5 0x1056c
+#define GATE_IP_GSCL 0x10920
+#define GATE_IP_DISP1 0x10928
+#define GATE_IP_MFC 0x1092c
+#define GATE_IP_G3D 0x10930
+#define GATE_IP_GEN 0x10934
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define SRC_CDREX 0x20200
+#define PLL_DIV2_SEL 0x20a24
+
+/*Below definitions are used for PWR_CTRL settings*/
+#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
+
+/* list of PLLs to be registered */
+enum exynos5250_plls {
+ apll, mpll, cpll, epll, vpll, gpll, bpll,
+ nr_plls /* number of PLLs */
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos5250_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static const unsigned long exynos5250_clk_regs[] __initconst = {
+ SRC_CPU,
+ DIV_CPU0,
+ PWR_CTRL1,
+ PWR_CTRL2,
+ SRC_CORE1,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_TOP3,
+ SRC_GSCL,
+ SRC_DISP1_0,
+ SRC_MAU,
+ SRC_FSYS,
+ SRC_GEN,
+ SRC_PERIC0,
+ SRC_PERIC1,
+ SRC_MASK_GSCL,
+ SRC_MASK_DISP1_0,
+ SRC_MASK_MAU,
+ SRC_MASK_FSYS,
+ SRC_MASK_GEN,
+ SRC_MASK_PERIC0,
+ SRC_MASK_PERIC1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_GSCL,
+ DIV_DISP1_0,
+ DIV_GEN,
+ DIV_MAU,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ DIV_PERIC1,
+ DIV_PERIC2,
+ DIV_PERIC3,
+ DIV_PERIC4,
+ DIV_PERIC5,
+ GATE_IP_GSCL,
+ GATE_IP_MFC,
+ GATE_IP_G3D,
+ GATE_IP_GEN,
+ GATE_IP_FSYS,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+ SRC_CDREX,
+ PLL_DIV2_SEL,
+ GATE_IP_DISP1,
+ GATE_IP_ACP,
+ GATE_IP_ISP0,
+ GATE_IP_ISP1,
+};
+
+static int exynos5250_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, exynos5250_save,
+ ARRAY_SIZE(exynos5250_clk_regs));
+
+ return 0;
+}
+
+static void exynos5250_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, exynos5250_save,
+ ARRAY_SIZE(exynos5250_clk_regs));
+}
+
+static struct syscore_ops exynos5250_clk_syscore_ops = {
+ .suspend = exynos5250_clk_suspend,
+ .resume = exynos5250_clk_resume,
+};
+
+static void __init exynos5250_clk_sleep_init(void)
+{
+ exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
+ ARRAY_SIZE(exynos5250_clk_regs));
+ if (!exynos5250_save) {
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+ return;
+ }
+
+ register_syscore_ops(&exynos5250_clk_syscore_ops);
+}
+#else
+static void __init exynos5250_clk_sleep_init(void) {}
+#endif
+
+/* list of all parent clock list */
+PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
+PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
+PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
+PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
+PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
+PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
+PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
+PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
+PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
+PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
+PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
+PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
+PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
+PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
+PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
+PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid",
+ "mout_aclk300_disp1_mid1" };
+PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
+PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
+PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
+PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
+PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
+PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
+PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
+PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
+PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
+PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
+ "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
+ "mout_mpll_user", "mout_epll", "mout_vpll",
+ "mout_cpll", "none", "none",
+ "none", "none", "none",
+ "none" };
+PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+ "sclk_uhostphy", "fin_pll",
+ "mout_mpll_user", "mout_epll", "mout_vpll",
+ "mout_cpll", "none", "none",
+ "none", "none", "none",
+ "none" };
+PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+ "sclk_uhostphy", "fin_pll",
+ "mout_mpll_user", "mout_epll", "mout_vpll",
+ "mout_cpll", "none", "none",
+ "none", "none", "none",
+ "none" };
+PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+ "sclk_uhostphy", "fin_pll",
+ "mout_mpll_user", "mout_epll", "mout_vpll",
+ "mout_cpll", "none", "none",
+ "none", "none", "none",
+ "none" };
+PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+ "spdif_extclk" };
+
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+ FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
+ FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
+ FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
+ FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
+};
+
+static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
+ FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
+};
+
+static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
+ MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
+};
+
+static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by (clock domain, register address,
+ * bitfield shift) triplet in ascending order. When adding new entries,
+ * please make sure that the order is kept, to avoid merge conflicts
+ * and make further work with defined data easier.
+ */
+
+ /*
+ * CMU_CPU
+ */
+ MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT, 0, "mout_apll"),
+ MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
+
+ /*
+ * CMU_CORE
+ */
+ MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
+
+ /*
+ * CMU_TOP
+ */
+ MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
+ MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
+ MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
+ MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
+ MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
+
+ MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
+ 8, 1),
+ MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
+ MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
+
+ MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
+ MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
+ MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
+ MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
+ MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
+ MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
+
+ MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
+ mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+ MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
+ mout_aclk300_sub_p, SRC_TOP3, 6, 1),
+ MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
+ MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
+ MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
+ SRC_TOP3, 20, 1),
+ MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
+
+ MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
+ MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
+ MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
+ MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
+ MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
+
+ MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
+ MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
+ MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
+ MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+
+ MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
+
+ MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
+ MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
+ MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
+ MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
+
+ MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
+
+ MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
+ MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
+ MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
+ MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
+ MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
+
+ MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
+ MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
+ MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
+ MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
+ MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
+ MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
+
+ /*
+ * CMU_CDREX
+ */
+ MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
+
+ MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
+ MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
+};
+
+static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by (clock domain, register address,
+ * bitfield shift) triplet in ascending order. When adding new entries,
+ * please make sure that the order is kept, to avoid merge conflicts
+ * and make further work with defined data easier.
+ */
+
+ /*
+ * CMU_CPU
+ */
+ DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
+ DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+
+ /*
+ * CMU_TOP
+ */
+ DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
+ DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
+ DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+ DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
+ DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
+ DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
+ 24, 3),
+ DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
+
+ DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
+ DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
+
+ DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
+ DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
+ DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
+ DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
+ DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
+
+ DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
+ DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
+ DIV_F(0, "div_mipi1_pre", "div_mipi1",
+ DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
+ DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
+ DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
+
+ DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
+
+ DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
+ DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+
+ DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+ DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
+
+ DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV_F(0, "div_mmc_pre0", "div_mmc0",
+ DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV_F(0, "div_mmc_pre1", "div_mmc1",
+ DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+ DIV_F(0, "div_mmc_pre2", "div_mmc2",
+ DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+ DIV_F(0, "div_mmc_pre3", "div_mmc3",
+ DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+ DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+ DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+ DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+ DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
+ DIV_F(0, "div_spi_pre0", "div_spi0",
+ DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
+ DIV_F(0, "div_spi_pre1", "div_spi1",
+ DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
+ DIV_F(0, "div_spi_pre2", "div_spi2",
+ DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+
+ DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
+ DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
+ DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
+ DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
+
+ DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
+ DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
+};
+
+static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
+ /*
+ * NOTE: Following table is sorted by (clock domain, register address,
+ * bitfield shift) triplet in ascending order. When adding new entries,
+ * please make sure that the order is kept, to avoid merge conflicts
+ * and make further work with defined data easier.
+ */
+
+ /*
+ * CMU_ACP
+ */
+ GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
+ GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
+ GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
+ GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
+
+ /*
+ * CMU_TOP
+ */
+ GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
+ SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
+ SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+ SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
+ SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
+ SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
+ SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
+ SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
+ SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
+ SRC_MASK_DISP1_0, 20, 0, 0),
+
+ GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
+ SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
+ SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
+ SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
+ SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+ SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
+ SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
+ SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
+ SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
+ SRC_MASK_PERIC1, 4, 0, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
+ SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
+ SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
+ SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
+ 0),
+ GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
+ 0),
+ GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
+ 0),
+ GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
+ 0),
+ GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
+ GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
+ GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
+ GATE_IP_GSCL, 7, 0, 0),
+ GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
+ GATE_IP_GSCL, 8, 0, 0),
+ GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
+ GATE_IP_GSCL, 9, 0, 0),
+ GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
+ GATE_IP_GSCL, 10, 0, 0),
+
+ GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
+ 0),
+ GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
+ 0),
+ GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
+ 0),
+ GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
+ GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
+ 0),
+ GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
+ 0),
+
+ GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
+ GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
+ 0),
+ GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
+ 0),
+ GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
+ GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
+ GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
+ GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
+ 0),
+ GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
+ GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
+
+ GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
+ GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
+ GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
+ GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
+ GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
+ GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
+ GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
+ GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
+ GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
+ GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
+ GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
+ GATE_IP_FSYS, 24, 0, 0),
+ GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
+ 0),
+
+ GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
+ GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
+ GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
+ GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
+ GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
+ GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
+ GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
+ GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
+ GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
+ GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
+ GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
+ GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
+ GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
+ GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
+ GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
+ GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
+ GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
+ GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
+ GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
+ GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
+ GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
+ GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
+ GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
+ GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
+ GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
+ GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
+ GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
+ GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
+
+ GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
+ GATE(CLK_SYSREG, "sysreg", "div_aclk66",
+ GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
+ 0),
+ GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
+ GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
+ GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
+ GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
+ GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
+ GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
+ GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
+ GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
+ GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
+ GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
+ GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
+ GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
+ GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
+ GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
+ GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
+ GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
+ GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
+ GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
+ GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
+ GATE_IP_DISP1, 9, 0, 0),
+ GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
+ GATE_IP_DISP1, 8, 0, 0),
+ GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
+ GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP0, 8, 0, 0),
+ GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP0, 9, 0, 0),
+ GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP0, 10, 0, 0),
+ GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP0, 11, 0, 0),
+ GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP0, 12, 0, 0),
+ GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
+ GATE_IP_ISP0, 13, 0, 0),
+ GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP1, 4, 0, 0),
+ GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP1, 5, 0, 0),
+ GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP1, 6, 0, 0),
+ GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
+ GATE_IP_ISP1, 7, 0, 0),
+};
+
+static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+ /* Not in UM, but need for eDP on snow */
+ PLL_36XX_RATE(70500000, 94, 2, 4, 0),
+ { },
+};
+
+static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(192000000, 64, 2, 2, 0),
+ PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
+ PLL_36XX_RATE(180000000, 90, 3, 2, 0),
+ PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
+ PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
+ PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
+ PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
+ PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+ { },
+};
+
+static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(1700000000, 425, 6, 0),
+ PLL_35XX_RATE(1600000000, 200, 3, 0),
+ PLL_35XX_RATE(1500000000, 250, 4, 0),
+ PLL_35XX_RATE(1400000000, 175, 3, 0),
+ PLL_35XX_RATE(1300000000, 325, 6, 0),
+ PLL_35XX_RATE(1200000000, 200, 4, 0),
+ PLL_35XX_RATE(1100000000, 275, 6, 0),
+ PLL_35XX_RATE(1000000000, 125, 3, 0),
+ PLL_35XX_RATE(900000000, 150, 4, 0),
+ PLL_35XX_RATE(800000000, 100, 3, 0),
+ PLL_35XX_RATE(700000000, 175, 3, 1),
+ PLL_35XX_RATE(600000000, 200, 4, 1),
+ PLL_35XX_RATE(500000000, 125, 3, 1),
+ PLL_35XX_RATE(400000000, 100, 3, 1),
+ PLL_35XX_RATE(300000000, 200, 4, 2),
+ PLL_35XX_RATE(200000000, 100, 3, 2),
+};
+
+static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
+ [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, "fout_apll", NULL),
+ [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
+ MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
+ GPLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
+ EPLL_CON0, NULL),
+ [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
+ VPLL_LOCK, VPLL_CON0, NULL),
+};
+
+#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
+ ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+ ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
+#define E5250_CPU_DIV1(hpm, copy) \
+ (((hpm) << 4) | (copy))
+
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
+ { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 0 },
+};
+
+static const struct of_device_id ext_clk_match[] __initconst = {
+ { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+ { },
+};
+
+/* register exynox5250 clocks */
+static void __init exynos5250_clk_init(struct device_node *np)
+{
+ struct samsung_clk_provider *ctx;
+ unsigned int tmp;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
+ ext_clk_match);
+ samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
+ ARRAY_SIZE(exynos5250_pll_pmux_clks));
+
+ if (_get_rate("fin_pll") == 24 * MHZ) {
+ exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
+ exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
+ }
+
+ if (_get_rate("mout_vpllsrc") == 24 * MHZ)
+ exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
+
+ samsung_clk_register_pll(ctx, exynos5250_plls,
+ ARRAY_SIZE(exynos5250_plls),
+ reg_base);
+ samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
+ ARRAY_SIZE(exynos5250_fixed_rate_clks));
+ samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
+ ARRAY_SIZE(exynos5250_fixed_factor_clks));
+ samsung_clk_register_mux(ctx, exynos5250_mux_clks,
+ ARRAY_SIZE(exynos5250_mux_clks));
+ samsung_clk_register_div(ctx, exynos5250_div_clks,
+ ARRAY_SIZE(exynos5250_div_clks));
+ samsung_clk_register_gate(ctx, exynos5250_gate_clks,
+ ARRAY_SIZE(exynos5250_gate_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
+ CLK_CPU_HAS_DIV1);
+
+ /*
+ * Enable arm clock down (in idle) and set arm divider
+ * ratios in WFI/WFE state.
+ */
+ tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
+ PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+ PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+ PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+ __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+ /*
+ * Enable arm clock up (on exiting idle). Set arm divider
+ * ratios when not in idle along with the standby duration
+ * ratios.
+ */
+ tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
+ PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
+ PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
+ __raw_writel(tmp, reg_base + PWR_CTRL2);
+
+ exynos5250_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
+ _get_rate("div_arm2"));
+}
+CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Rahul Sharma <rahul.sharma@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5260 SoC.
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk-exynos5260.h"
+#include "clk.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clock/exynos5260-clk.h>
+
+/*
+ * Applicable for all 2550 Type PLLS for Exynos5260, listed below
+ * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
+ */
+static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
+ PLL_35XX_RATE(1700000000, 425, 6, 0),
+ PLL_35XX_RATE(1600000000, 200, 3, 0),
+ PLL_35XX_RATE(1500000000, 250, 4, 0),
+ PLL_35XX_RATE(1400000000, 175, 3, 0),
+ PLL_35XX_RATE(1300000000, 325, 6, 0),
+ PLL_35XX_RATE(1200000000, 400, 4, 1),
+ PLL_35XX_RATE(1100000000, 275, 3, 1),
+ PLL_35XX_RATE(1000000000, 250, 3, 1),
+ PLL_35XX_RATE(933000000, 311, 4, 1),
+ PLL_35XX_RATE(900000000, 300, 4, 1),
+ PLL_35XX_RATE(800000000, 200, 3, 1),
+ PLL_35XX_RATE(733000000, 733, 12, 1),
+ PLL_35XX_RATE(700000000, 175, 3, 1),
+ PLL_35XX_RATE(667000000, 667, 12, 1),
+ PLL_35XX_RATE(633000000, 211, 4, 1),
+ PLL_35XX_RATE(620000000, 310, 3, 2),
+ PLL_35XX_RATE(600000000, 400, 4, 2),
+ PLL_35XX_RATE(543000000, 362, 4, 2),
+ PLL_35XX_RATE(533000000, 533, 6, 2),
+ PLL_35XX_RATE(500000000, 250, 3, 2),
+ PLL_35XX_RATE(450000000, 300, 4, 2),
+ PLL_35XX_RATE(400000000, 200, 3, 2),
+ PLL_35XX_RATE(350000000, 175, 3, 2),
+ PLL_35XX_RATE(300000000, 400, 4, 3),
+ PLL_35XX_RATE(266000000, 266, 3, 3),
+ PLL_35XX_RATE(200000000, 200, 3, 3),
+ PLL_35XX_RATE(160000000, 160, 3, 3),
+};
+
+/*
+ * Applicable for 2650 Type PLL for AUD_PLL.
+ */
+static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
+ PLL_36XX_RATE(1600000000, 200, 3, 0, 0),
+ PLL_36XX_RATE(1200000000, 100, 2, 0, 0),
+ PLL_36XX_RATE(1000000000, 250, 3, 1, 0),
+ PLL_36XX_RATE(800000000, 200, 3, 1, 0),
+ PLL_36XX_RATE(600000000, 100, 2, 1, 0),
+ PLL_36XX_RATE(532000000, 266, 3, 2, 0),
+ PLL_36XX_RATE(480000000, 160, 2, 2, 0),
+ PLL_36XX_RATE(432000000, 144, 2, 2, 0),
+ PLL_36XX_RATE(400000000, 200, 3, 2, 0),
+ PLL_36XX_RATE(394073130, 459, 7, 2, 49282),
+ PLL_36XX_RATE(333000000, 111, 2, 2, 0),
+ PLL_36XX_RATE(300000000, 100, 2, 2, 0),
+ PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+ PLL_36XX_RATE(200000000, 200, 3, 3, 0),
+ PLL_36XX_RATE(166000000, 166, 3, 3, 0),
+ PLL_36XX_RATE(133000000, 266, 3, 4, 0),
+ PLL_36XX_RATE(100000000, 200, 3, 4, 0),
+ PLL_36XX_RATE(66000000, 176, 2, 5, 0),
+};
+
+/* CMU_AUD */
+
+static const unsigned long aud_clk_regs[] __initconst = {
+ MUX_SEL_AUD,
+ DIV_AUD0,
+ DIV_AUD1,
+ EN_ACLK_AUD,
+ EN_PCLK_AUD,
+ EN_SCLK_AUD,
+ EN_IP_AUD,
+};
+
+PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
+PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
+PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
+
+static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
+ MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
+ MUX_SEL_AUD, 0, 1),
+ MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
+ MUX_SEL_AUD, 4, 1),
+ MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD, 8, 1),
+};
+
+static const struct samsung_div_clock aud_div_clks[] __initconst = {
+ DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
+ DIV_AUD0, 0, 4),
+
+ DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
+ DIV_AUD1, 0, 4),
+ DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
+ DIV_AUD1, 4, 8),
+ DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
+ DIV_AUD1, 12, 4),
+};
+
+static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
+ GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
+ EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
+ EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
+ EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
+
+ GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
+ 0, 0, 0),
+ GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
+ EN_IP_AUD, 1, 0, 0),
+ GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
+ GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
+ GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
+ EN_IP_AUD, 4, 0, 0),
+};
+
+static const struct samsung_cmu_info aud_cmu __initconst = {
+ .mux_clks = aud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
+ .div_clks = aud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(aud_div_clks),
+ .gate_clks = aud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
+ .nr_clk_ids = AUD_NR_CLK,
+ .clk_regs = aud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos5260_clk_aud_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &aud_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
+ exynos5260_clk_aud_init);
+
+
+/* CMU_DISP */
+
+static const unsigned long disp_clk_regs[] __initconst = {
+ MUX_SEL_DISP0,
+ MUX_SEL_DISP1,
+ MUX_SEL_DISP2,
+ MUX_SEL_DISP3,
+ MUX_SEL_DISP4,
+ DIV_DISP,
+ EN_ACLK_DISP,
+ EN_PCLK_DISP,
+ EN_SCLK_DISP0,
+ EN_SCLK_DISP1,
+ EN_IP_DISP,
+ EN_IP_DISP_BUS,
+};
+
+PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
+ "phyclk_dptx_phy_ch3_txd_clk"};
+PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
+ "phyclk_dptx_phy_ch2_txd_clk"};
+PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
+ "phyclk_dptx_phy_ch1_txd_clk"};
+PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
+ "phyclk_dptx_phy_ch0_txd_clk"};
+PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
+PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
+PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
+PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
+ "phyclk_hdmi_phy_tmds_clko"};
+PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
+ "phyclk_hdmi_phy_ref_clko"};
+PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
+ "phyclk_hdmi_phy_pixel_clko"};
+PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
+ "phyclk_hdmi_link_o_tmds_clkhi"};
+PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
+ "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
+PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
+ "phyclk_dptx_phy_o_ref_clk_24m"};
+PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
+ "phyclk_dptx_phy_clk_div2"};
+PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
+ "mout_aclk_disp_222_user"};
+PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
+ "phyclk_mipi_dphy_4l_m_rxclkesc0"};
+PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
+ "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
+
+static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
+ MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
+ mout_aclk_disp_333_user_p,
+ MUX_SEL_DISP0, 0, 1),
+ MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
+ mout_sclk_disp_pixel_user_p,
+ MUX_SEL_DISP0, 4, 1),
+ MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
+ mout_aclk_disp_222_user_p,
+ MUX_SEL_DISP0, 8, 1),
+ MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
+ "mout_phyclk_dptx_phy_ch0_txd_clk_user",
+ mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
+ MUX_SEL_DISP0, 16, 1),
+ MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
+ "mout_phyclk_dptx_phy_ch1_txd_clk_user",
+ mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
+ MUX_SEL_DISP0, 20, 1),
+ MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
+ "mout_phyclk_dptx_phy_ch2_txd_clk_user",
+ mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
+ MUX_SEL_DISP0, 24, 1),
+ MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
+ "mout_phyclk_dptx_phy_ch3_txd_clk_user",
+ mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
+ MUX_SEL_DISP0, 28, 1),
+
+ MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
+ "mout_phyclk_dptx_phy_clk_div2_user",
+ mout_phyclk_dptx_phy_clk_div2_user_p,
+ MUX_SEL_DISP1, 0, 1),
+ MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
+ "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
+ mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
+ MUX_SEL_DISP1, 4, 1),
+ MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
+ "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
+ mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
+ MUX_SEL_DISP1, 8, 1),
+ MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
+ "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
+ mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
+ MUX_SEL_DISP1, 16, 1),
+ MUX(DISP_MOUT_HDMI_PHY_PIXEL,
+ "mout_phyclk_hdmi_phy_pixel_clko_user",
+ mout_phyclk_hdmi_phy_pixel_clko_user_p,
+ MUX_SEL_DISP1, 20, 1),
+ MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
+ "mout_phyclk_hdmi_phy_ref_clko_user",
+ mout_phyclk_hdmi_phy_ref_clko_user_p,
+ MUX_SEL_DISP1, 24, 1),
+ MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
+ "mout_phyclk_hdmi_phy_tmds_clko_user",
+ mout_phyclk_hdmi_phy_tmds_clko_user_p,
+ MUX_SEL_DISP1, 28, 1),
+
+ MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
+ "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
+ mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
+ MUX_SEL_DISP2, 0, 1),
+ MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
+ mout_sclk_hdmi_pixel_p,
+ MUX_SEL_DISP2, 4, 1),
+
+ MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
+ mout_sclk_hdmi_spdif_p,
+ MUX_SEL_DISP4, 4, 2),
+};
+
+static const struct samsung_div_clock disp_div_clks[] __initconst = {
+ DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
+ "mout_aclk_disp_222_user",
+ DIV_DISP, 8, 4),
+ DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
+ "mout_sclk_disp_pixel_user",
+ DIV_DISP, 12, 4),
+ DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
+ "dout_sclk_hdmi_phy_pixel_clki",
+ "mout_sclk_hdmi_pixel",
+ DIV_DISP, 16, 4),
+};
+
+static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
+ GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
+ "mout_phyclk_hdmi_phy_pixel_clko_user",
+ EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
+ GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
+ "dout_sclk_hdmi_phy_pixel_clki",
+ EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
+
+ GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 4, 0, 0),
+ GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 5, 0, 0),
+ GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 6, 0, 0),
+ GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 7, 0, 0),
+ GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 8, 0, 0),
+ GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 9, 0, 0),
+ GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 10, 0, 0),
+ GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 11, 0, 0),
+ GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
+ "mout_aclk_disp_222_user",
+ EN_IP_DISP, 22, 0, 0),
+ GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
+ "mout_aclk_disp_222_user",
+ EN_IP_DISP, 23, 0, 0),
+ GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
+ EN_IP_DISP, 25, 0, 0),
+};
+
+static const struct samsung_cmu_info disp_cmu __initconst = {
+ .mux_clks = disp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
+ .div_clks = disp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(disp_div_clks),
+ .gate_clks = disp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
+ .nr_clk_ids = DISP_NR_CLK,
+ .clk_regs = disp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
+};
+
+static void __init exynos5260_clk_disp_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &disp_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
+ exynos5260_clk_disp_init);
+
+
+/* CMU_EGL */
+
+static const unsigned long egl_clk_regs[] __initconst = {
+ EGL_PLL_LOCK,
+ EGL_PLL_CON0,
+ EGL_PLL_CON1,
+ EGL_PLL_FREQ_DET,
+ MUX_SEL_EGL,
+ MUX_ENABLE_EGL,
+ DIV_EGL,
+ DIV_EGL_PLL_FDET,
+ EN_ACLK_EGL,
+ EN_PCLK_EGL,
+ EN_SCLK_EGL,
+};
+
+PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
+PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
+
+static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
+ MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
+ MUX_SEL_EGL, 4, 1),
+ MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
+};
+
+static const struct samsung_div_clock egl_div_clks[] __initconst = {
+ DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
+ DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
+ DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
+ DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
+ DIV_EGL, 12, 3),
+ DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
+ DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
+ DIV_EGL, 20, 3),
+ DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
+};
+
+static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
+ PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
+ EGL_PLL_LOCK, EGL_PLL_CON0,
+ pll2550_24mhz_tbl),
+};
+
+static const struct samsung_cmu_info egl_cmu __initconst = {
+ .pll_clks = egl_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(egl_pll_clks),
+ .mux_clks = egl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
+ .div_clks = egl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(egl_div_clks),
+ .nr_clk_ids = EGL_NR_CLK,
+ .clk_regs = egl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
+};
+
+static void __init exynos5260_clk_egl_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &egl_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
+ exynos5260_clk_egl_init);
+
+
+/* CMU_FSYS */
+
+static const unsigned long fsys_clk_regs[] __initconst = {
+ MUX_SEL_FSYS0,
+ MUX_SEL_FSYS1,
+ EN_ACLK_FSYS,
+ EN_ACLK_FSYS_SECURE_RTIC,
+ EN_ACLK_FSYS_SECURE_SMMU_RTIC,
+ EN_SCLK_FSYS,
+ EN_IP_FSYS,
+ EN_IP_FSYS_SECURE_RTIC,
+ EN_IP_FSYS_SECURE_SMMU_RTIC,
+};
+
+PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
+ "phyclk_usbhost20_phy_phyclock"};
+PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
+ "phyclk_usbhost20_phy_freeclk"};
+PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
+ "phyclk_usbhost20_phy_clk48mohci"};
+PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
+ "phyclk_usbdrd30_udrd30_pipe_pclk"};
+PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
+ "phyclk_usbdrd30_udrd30_phyclock"};
+
+static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
+ MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
+ "mout_phyclk_usbdrd30_phyclock_user",
+ mout_phyclk_usbdrd30_phyclock_user_p,
+ MUX_SEL_FSYS1, 0, 1),
+ MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
+ "mout_phyclk_usbdrd30_pipe_pclk_user",
+ mout_phyclk_usbdrd30_pipe_pclk_user_p,
+ MUX_SEL_FSYS1, 4, 1),
+ MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
+ "mout_phyclk_usbhost20_clk48mohci_user",
+ mout_phyclk_usbhost20_clk48mohci_user_p,
+ MUX_SEL_FSYS1, 8, 1),
+ MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
+ "mout_phyclk_usbhost20_freeclk_user",
+ mout_phyclk_usbhost20_freeclk_user_p,
+ MUX_SEL_FSYS1, 12, 1),
+ MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
+ "mout_phyclk_usbhost20_phyclk_user",
+ mout_phyclk_usbhost20_phyclk_user_p,
+ MUX_SEL_FSYS1, 16, 1),
+};
+
+static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
+ GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
+ "mout_phyclk_usbdrd30_phyclock_user",
+ EN_SCLK_FSYS, 1, 0, 0),
+ GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
+ "mout_phyclk_usbdrd30_phyclock_user",
+ EN_SCLK_FSYS, 7, 0, 0),
+
+ GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 6, 0, 0),
+ GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 7, 0, 0),
+ GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 8, 0, 0),
+ GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 9, 0, 0),
+ GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 13, 0, 0),
+ GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 14, 0, 0),
+ GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 15, 0, 0),
+ GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 18, 0, 0),
+ GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
+ EN_IP_FSYS, 20, 0, 0),
+
+ GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
+ EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
+ GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
+ EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys_cmu __initconst = {
+ .mux_clks = fsys_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
+ .gate_clks = fsys_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
+ .nr_clk_ids = FSYS_NR_CLK,
+ .clk_regs = fsys_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
+};
+
+static void __init exynos5260_clk_fsys_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &fsys_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
+ exynos5260_clk_fsys_init);
+
+
+/* CMU_G2D */
+
+static const unsigned long g2d_clk_regs[] __initconst = {
+ MUX_SEL_G2D,
+ MUX_STAT_G2D,
+ DIV_G2D,
+ EN_ACLK_G2D,
+ EN_ACLK_G2D_SECURE_SSS,
+ EN_ACLK_G2D_SECURE_SLIM_SSS,
+ EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
+ EN_ACLK_G2D_SECURE_SMMU_SSS,
+ EN_ACLK_G2D_SECURE_SMMU_MDMA,
+ EN_ACLK_G2D_SECURE_SMMU_G2D,
+ EN_PCLK_G2D,
+ EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
+ EN_PCLK_G2D_SECURE_SMMU_SSS,
+ EN_PCLK_G2D_SECURE_SMMU_MDMA,
+ EN_PCLK_G2D_SECURE_SMMU_G2D,
+ EN_IP_G2D,
+ EN_IP_G2D_SECURE_SSS,
+ EN_IP_G2D_SECURE_SLIM_SSS,
+ EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
+ EN_IP_G2D_SECURE_SMMU_SSS,
+ EN_IP_G2D_SECURE_SMMU_MDMA,
+ EN_IP_G2D_SECURE_SMMU_G2D,
+};
+
+PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
+
+static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
+ MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
+ mout_aclk_g2d_333_user_p,
+ MUX_SEL_G2D, 0, 1),
+};
+
+static const struct samsung_div_clock g2d_div_clks[] __initconst = {
+ DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
+ DIV_G2D, 0, 3),
+};
+
+static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
+ GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
+ EN_IP_G2D, 4, 0, 0),
+ GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
+ EN_IP_G2D, 5, 0, 0),
+ GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
+ EN_IP_G2D, 6, 0, 0),
+ GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
+ EN_IP_G2D, 16, 0, 0),
+
+ GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
+ EN_IP_G2D_SECURE_SSS, 17, 0, 0),
+
+ GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
+ EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
+
+ GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
+ "mout_aclk_g2d_333_user",
+ EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
+
+ GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
+ EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
+
+ GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
+ EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
+
+ GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
+ EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
+};
+
+static const struct samsung_cmu_info g2d_cmu __initconst = {
+ .mux_clks = g2d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
+ .div_clks = g2d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
+ .gate_clks = g2d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
+ .nr_clk_ids = G2D_NR_CLK,
+ .clk_regs = g2d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
+};
+
+static void __init exynos5260_clk_g2d_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &g2d_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
+ exynos5260_clk_g2d_init);
+
+
+/* CMU_G3D */
+
+static const unsigned long g3d_clk_regs[] __initconst = {
+ G3D_PLL_LOCK,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_FDET,
+ MUX_SEL_G3D,
+ DIV_G3D,
+ DIV_G3D_PLL_FDET,
+ EN_ACLK_G3D,
+ EN_PCLK_G3D,
+ EN_SCLK_G3D,
+ EN_IP_G3D,
+};
+
+PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
+
+static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
+ MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+ MUX_SEL_G3D, 0, 1),
+};
+
+static const struct samsung_div_clock g3d_div_clks[] __initconst = {
+ DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
+ DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
+};
+
+static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
+ GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
+ GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
+ EN_IP_G3D, 3, 0, 0),
+};
+
+static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
+ PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
+ G3D_PLL_LOCK, G3D_PLL_CON0,
+ pll2550_24mhz_tbl),
+};
+
+static const struct samsung_cmu_info g3d_cmu __initconst = {
+ .pll_clks = g3d_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
+ .mux_clks = g3d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
+ .div_clks = g3d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
+ .gate_clks = g3d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
+ .nr_clk_ids = G3D_NR_CLK,
+ .clk_regs = g3d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
+};
+
+static void __init exynos5260_clk_g3d_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &g3d_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
+ exynos5260_clk_g3d_init);
+
+
+/* CMU_GSCL */
+
+static const unsigned long gscl_clk_regs[] __initconst = {
+ MUX_SEL_GSCL,
+ DIV_GSCL,
+ EN_ACLK_GSCL,
+ EN_ACLK_GSCL_FIMC,
+ EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
+ EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
+ EN_PCLK_GSCL,
+ EN_PCLK_GSCL_FIMC,
+ EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
+ EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
+ EN_SCLK_GSCL,
+ EN_SCLK_GSCL_FIMC,
+ EN_IP_GSCL,
+ EN_IP_GSCL_FIMC,
+ EN_IP_GSCL_SECURE_SMMU_GSCL0,
+ EN_IP_GSCL_SECURE_SMMU_GSCL1,
+ EN_IP_GSCL_SECURE_SMMU_MSCL0,
+ EN_IP_GSCL_SECURE_SMMU_MSCL1,
+};
+
+PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
+PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
+PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
+PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
+
+static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
+ MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
+ mout_aclk_gscl_333_user_p,
+ MUX_SEL_GSCL, 0, 1),
+ MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
+ mout_aclk_m2m_400_user_p,
+ MUX_SEL_GSCL, 4, 1),
+ MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
+ mout_aclk_gscl_fimc_user_p,
+ MUX_SEL_GSCL, 8, 1),
+ MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
+ MUX_SEL_GSCL, 24, 1),
+};
+
+static const struct samsung_div_clock gscl_div_clks[] __initconst = {
+ DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
+ "mout_aclk_m2m_400_user",
+ DIV_GSCL, 0, 3),
+ DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
+ "mout_aclk_m2m_400_user",
+ DIV_GSCL, 4, 3),
+};
+
+static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
+ GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
+ EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
+ EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
+
+ GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
+ EN_IP_GSCL, 2, 0, 0),
+ GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
+ EN_IP_GSCL, 3, 0, 0),
+ GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
+ EN_IP_GSCL, 4, 0, 0),
+ GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
+ EN_IP_GSCL, 5, 0, 0),
+ GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
+ "mout_aclk_gscl_333_user",
+ EN_IP_GSCL, 8, 0, 0),
+ GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
+ "mout_aclk_gscl_333_user",
+ EN_IP_GSCL, 9, 0, 0),
+
+ GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
+ "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 5, 0, 0),
+ GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
+ "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 6, 0, 0),
+ GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
+ "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 7, 0, 0),
+ GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 8, 0, 0),
+ GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 9, 0, 0),
+ GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
+ "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 10, 0, 0),
+ GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
+ "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 11, 0, 0),
+ GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
+ "mout_aclk_gscl_fimc_user",
+ EN_IP_GSCL_FIMC, 12, 0, 0),
+
+ GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
+ "mout_aclk_gscl_333_user",
+ EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
+ GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
+ EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
+ GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
+ "mout_aclk_m2m_400_user",
+ EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
+ GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
+ "mout_aclk_m2m_400_user",
+ EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
+};
+
+static const struct samsung_cmu_info gscl_cmu __initconst = {
+ .mux_clks = gscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
+ .div_clks = gscl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(gscl_div_clks),
+ .gate_clks = gscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
+ .nr_clk_ids = GSCL_NR_CLK,
+ .clk_regs = gscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
+};
+
+static void __init exynos5260_clk_gscl_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &gscl_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
+ exynos5260_clk_gscl_init);
+
+
+/* CMU_ISP */
+
+static const unsigned long isp_clk_regs[] __initconst = {
+ MUX_SEL_ISP0,
+ MUX_SEL_ISP1,
+ DIV_ISP,
+ EN_ACLK_ISP0,
+ EN_ACLK_ISP1,
+ EN_PCLK_ISP0,
+ EN_PCLK_ISP1,
+ EN_SCLK_ISP,
+ EN_IP_ISP0,
+ EN_IP_ISP1,
+};
+
+PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
+PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
+
+static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
+ MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
+ MUX_SEL_ISP0, 0, 1),
+ MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
+ MUX_SEL_ISP0, 4, 1),
+};
+
+static const struct samsung_div_clock isp_div_clks[] __initconst = {
+ DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
+ DIV_ISP, 0, 3),
+ DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
+ DIV_ISP, 4, 4),
+ DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
+ DIV_ISP, 12, 3),
+ DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
+ DIV_ISP, 16, 4),
+ DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
+};
+
+static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
+ GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
+ EN_IP_ISP0, 15, 0, 0),
+
+ GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 1, 0, 0),
+ GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 2, 0, 0),
+ GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 3, 0, 0),
+ GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 4, 0, 0),
+ GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
+ "mout_aclk_isp1_266",
+ EN_IP_ISP1, 5, 0, 0),
+ GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
+ "mout_aclk_isp1_266",
+ EN_IP_ISP1, 6, 0, 0),
+ GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 7, 0, 0),
+ GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 8, 0, 0),
+ GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 9, 0, 0),
+ GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 10, 0, 0),
+ GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 11, 0, 0),
+ GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 14, 0, 0),
+ GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 21, 0, 0),
+ GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 22, 0, 0),
+ GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 23, 0, 0),
+ GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 24, 0, 0),
+ GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
+ "mout_aclk_isp1_266",
+ EN_IP_ISP1, 25, 0, 0),
+ GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
+ "mout_aclk_isp1_266",
+ EN_IP_ISP1, 26, 0, 0),
+ GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 27, 0, 0),
+ GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 28, 0, 0),
+ GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 31, 0, 0),
+ GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
+ EN_IP_ISP1, 30, 0, 0),
+
+ GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
+ EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
+ EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
+ EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info isp_cmu __initconst = {
+ .mux_clks = isp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
+ .div_clks = isp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(isp_div_clks),
+ .gate_clks = isp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
+ .nr_clk_ids = ISP_NR_CLK,
+ .clk_regs = isp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
+};
+
+static void __init exynos5260_clk_isp_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &isp_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
+ exynos5260_clk_isp_init);
+
+
+/* CMU_KFC */
+
+static const unsigned long kfc_clk_regs[] __initconst = {
+ KFC_PLL_LOCK,
+ KFC_PLL_CON0,
+ KFC_PLL_CON1,
+ KFC_PLL_FDET,
+ MUX_SEL_KFC0,
+ MUX_SEL_KFC2,
+ DIV_KFC,
+ DIV_KFC_PLL_FDET,
+ EN_ACLK_KFC,
+ EN_PCLK_KFC,
+ EN_SCLK_KFC,
+ EN_IP_KFC,
+};
+
+PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
+PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
+
+static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
+ MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
+ MUX_SEL_KFC0, 0, 1),
+ MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
+};
+
+static const struct samsung_div_clock kfc_div_clks[] __initconst = {
+ DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
+ DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
+ DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
+ DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
+ DIV_KFC, 12, 3),
+ DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
+ DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
+ DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
+};
+
+static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
+ PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
+ KFC_PLL_LOCK, KFC_PLL_CON0,
+ pll2550_24mhz_tbl),
+};
+
+static const struct samsung_cmu_info kfc_cmu __initconst = {
+ .pll_clks = kfc_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(kfc_pll_clks),
+ .mux_clks = kfc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
+ .div_clks = kfc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(kfc_div_clks),
+ .nr_clk_ids = KFC_NR_CLK,
+ .clk_regs = kfc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
+};
+
+static void __init exynos5260_clk_kfc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &kfc_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
+ exynos5260_clk_kfc_init);
+
+
+/* CMU_MFC */
+
+static const unsigned long mfc_clk_regs[] __initconst = {
+ MUX_SEL_MFC,
+ DIV_MFC,
+ EN_ACLK_MFC,
+ EN_ACLK_SECURE_SMMU2_MFC,
+ EN_PCLK_MFC,
+ EN_PCLK_SECURE_SMMU2_MFC,
+ EN_IP_MFC,
+ EN_IP_MFC_SECURE_SMMU2_MFC,
+};
+
+PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
+
+static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
+ MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
+ mout_aclk_mfc_333_user_p,
+ MUX_SEL_MFC, 0, 1),
+};
+
+static const struct samsung_div_clock mfc_div_clks[] __initconst = {
+ DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
+ DIV_MFC, 0, 3),
+};
+
+static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
+ GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
+ EN_IP_MFC, 1, 0, 0),
+ GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
+ EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
+ GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
+ EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
+};
+
+static const struct samsung_cmu_info mfc_cmu __initconst = {
+ .mux_clks = mfc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
+ .div_clks = mfc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
+ .gate_clks = mfc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
+ .nr_clk_ids = MFC_NR_CLK,
+ .clk_regs = mfc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
+};
+
+static void __init exynos5260_clk_mfc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mfc_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
+ exynos5260_clk_mfc_init);
+
+
+/* CMU_MIF */
+
+static const unsigned long mif_clk_regs[] __initconst = {
+ MEM_PLL_LOCK,
+ BUS_PLL_LOCK,
+ MEDIA_PLL_LOCK,
+ MEM_PLL_CON0,
+ MEM_PLL_CON1,
+ MEM_PLL_FDET,
+ BUS_PLL_CON0,
+ BUS_PLL_CON1,
+ BUS_PLL_FDET,
+ MEDIA_PLL_CON0,
+ MEDIA_PLL_CON1,
+ MEDIA_PLL_FDET,
+ MUX_SEL_MIF,
+ DIV_MIF,
+ DIV_MIF_PLL_FDET,
+ EN_ACLK_MIF,
+ EN_ACLK_MIF_SECURE_DREX1_TZ,
+ EN_ACLK_MIF_SECURE_DREX0_TZ,
+ EN_ACLK_MIF_SECURE_INTMEM,
+ EN_PCLK_MIF,
+ EN_PCLK_MIF_SECURE_MONOCNT,
+ EN_PCLK_MIF_SECURE_RTC_APBIF,
+ EN_PCLK_MIF_SECURE_DREX1_TZ,
+ EN_PCLK_MIF_SECURE_DREX0_TZ,
+ EN_SCLK_MIF,
+ EN_IP_MIF,
+ EN_IP_MIF_SECURE_MONOCNT,
+ EN_IP_MIF_SECURE_RTC_APBIF,
+ EN_IP_MIF_SECURE_DREX1_TZ,
+ EN_IP_MIF_SECURE_DREX0_TZ,
+ EN_IP_MIF_SECURE_INTEMEM,
+};
+
+PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
+PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
+PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
+PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
+PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
+PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
+PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
+
+static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
+ MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
+ MUX_SEL_MIF, 0, 1),
+ MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
+ MUX_SEL_MIF, 4, 1),
+ MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
+ MUX_SEL_MIF, 8, 1),
+ MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
+ MUX_SEL_MIF, 12, 1),
+ MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
+ MUX_SEL_MIF, 16, 1),
+ MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
+ MUX_SEL_MIF, 20, 1),
+ MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
+ MUX_SEL_MIF, 24, 1),
+};
+
+static const struct samsung_div_clock mif_div_clks[] __initconst = {
+ DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
+ DIV_MIF, 0, 3),
+ DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
+ DIV_MIF, 4, 3),
+ DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
+ DIV_MIF, 8, 3),
+ DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
+ DIV_MIF, 12, 3),
+ DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
+ DIV_MIF, 16, 4),
+ DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
+ DIV_MIF, 20, 3),
+ DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
+ DIV_MIF, 24, 3),
+ DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
+ DIV_MIF, 28, 4),
+};
+
+static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
+ GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
+ EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
+ EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
+
+ GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
+ EN_IP_MIF_SECURE_MONOCNT, 22,
+ CLK_IGNORE_UNUSED, 0),
+
+ GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
+ EN_IP_MIF_SECURE_RTC_APBIF, 23,
+ CLK_IGNORE_UNUSED, 0),
+
+ GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
+ EN_IP_MIF_SECURE_DREX1_TZ, 9,
+ CLK_IGNORE_UNUSED, 0),
+
+ GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
+ EN_IP_MIF_SECURE_DREX0_TZ, 9,
+ CLK_IGNORE_UNUSED, 0),
+
+ GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
+ EN_IP_MIF_SECURE_INTEMEM, 11,
+ CLK_IGNORE_UNUSED, 0),
+
+ GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
+ "dout_clkm_phy", EN_SCLK_MIF, 0,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
+ "dout_clkm_phy", EN_SCLK_MIF, 1,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
+ PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
+ MEM_PLL_LOCK, MEM_PLL_CON0,
+ pll2550_24mhz_tbl),
+ PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
+ BUS_PLL_LOCK, BUS_PLL_CON0,
+ pll2550_24mhz_tbl),
+ PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
+ MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
+ pll2550_24mhz_tbl),
+};
+
+static const struct samsung_cmu_info mif_cmu __initconst = {
+ .pll_clks = mif_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
+ .mux_clks = mif_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
+ .div_clks = mif_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mif_div_clks),
+ .gate_clks = mif_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
+ .nr_clk_ids = MIF_NR_CLK,
+ .clk_regs = mif_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
+};
+
+static void __init exynos5260_clk_mif_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mif_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
+ exynos5260_clk_mif_init);
+
+
+/* CMU_PERI */
+
+static const unsigned long peri_clk_regs[] __initconst = {
+ MUX_SEL_PERI,
+ MUX_SEL_PERI1,
+ DIV_PERI,
+ EN_PCLK_PERI0,
+ EN_PCLK_PERI1,
+ EN_PCLK_PERI2,
+ EN_PCLK_PERI3,
+ EN_PCLK_PERI_SECURE_CHIPID,
+ EN_PCLK_PERI_SECURE_PROVKEY0,
+ EN_PCLK_PERI_SECURE_PROVKEY1,
+ EN_PCLK_PERI_SECURE_SECKEY,
+ EN_PCLK_PERI_SECURE_ANTIRBKCNT,
+ EN_PCLK_PERI_SECURE_TOP_RTC,
+ EN_PCLK_PERI_SECURE_TZPC,
+ EN_SCLK_PERI,
+ EN_SCLK_PERI_SECURE_TOP_RTC,
+ EN_IP_PERI0,
+ EN_IP_PERI1,
+ EN_IP_PERI2,
+ EN_IP_PERI_SECURE_CHIPID,
+ EN_IP_PERI_SECURE_PROVKEY0,
+ EN_IP_PERI_SECURE_PROVKEY1,
+ EN_IP_PERI_SECURE_SECKEY,
+ EN_IP_PERI_SECURE_ANTIRBKCNT,
+ EN_IP_PERI_SECURE_TOP_RTC,
+ EN_IP_PERI_SECURE_TZPC,
+};
+
+PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
+ "phyclk_hdmi_phy_ref_cko"};
+PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
+ "phyclk_hdmi_phy_ref_cko"};
+PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
+ "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
+
+static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
+ MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
+ MUX_SEL_PERI1, 4, 2),
+ MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
+ MUX_SEL_PERI1, 12, 2),
+ MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
+ MUX_SEL_PERI1, 20, 2),
+};
+
+static const struct samsung_div_clock peri_div_clks[] __initconst = {
+ DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
+ DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
+};
+
+static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
+ GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
+ EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
+ EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
+ EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
+ EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
+ EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
+ EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
+ EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
+
+ GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
+ EN_IP_PERI0, 1, 0, 0),
+ GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
+ EN_IP_PERI0, 5, 0, 0),
+ GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
+ EN_IP_PERI0, 6, 0, 0),
+ GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
+ EN_IP_PERI0, 7, 0, 0),
+ GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
+ EN_IP_PERI0, 8, 0, 0),
+ GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
+ EN_IP_PERI0, 9, 0, 0),
+ GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
+ EN_IP_PERI0, 10, 0, 0),
+ GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
+ EN_IP_PERI0, 11, 0, 0),
+ GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
+ EN_IP_PERI0, 12, 0, 0),
+ GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
+ EN_IP_PERI0, 13, 0, 0),
+ GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
+ EN_IP_PERI0, 14, 0, 0),
+ GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
+ EN_IP_PERI0, 15, 0, 0),
+ GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
+ EN_IP_PERI0, 16, 0, 0),
+ GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
+ EN_IP_PERI0, 17, 0, 0),
+ GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
+ EN_IP_PERI0, 18, 0, 0),
+ GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
+ EN_IP_PERI0, 20, 0, 0),
+ GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
+ EN_IP_PERI0, 21, 0, 0),
+ GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
+ EN_IP_PERI0, 22, 0, 0),
+ GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
+ EN_IP_PERI0, 23, 0, 0),
+ GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
+ EN_IP_PERI0, 24, 0, 0),
+ GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
+ EN_IP_PERI0, 25, 0, 0),
+
+ GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
+ EN_IP_PERI2, 0, 0, 0),
+ GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
+ EN_IP_PERI2, 3, 0, 0),
+ GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
+ EN_IP_PERI2, 6, 0, 0),
+ GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
+ EN_IP_PERI2, 7, 0, 0),
+ GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
+ EN_IP_PERI2, 8, 0, 0),
+ GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
+ EN_IP_PERI2, 9, 0, 0),
+ GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
+ EN_IP_PERI2, 10, 0, 0),
+ GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
+ EN_IP_PERI2, 11, 0, 0),
+ GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
+ EN_IP_PERI2, 12, 0, 0),
+ GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
+ EN_IP_PERI2, 13, 0, 0),
+ GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
+ EN_IP_PERI2, 14, 0, 0),
+ GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
+ EN_IP_PERI2, 18, 0, 0),
+ GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
+ EN_IP_PERI2, 19, 0, 0),
+ GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
+ EN_IP_PERI2, 20, 0, 0),
+ GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
+ EN_IP_PERI2, 21, 0, 0),
+
+ GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
+
+ GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
+
+ GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
+
+ GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
+
+ GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
+
+ GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
+ GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
+ GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
+ GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
+ GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
+ GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
+ GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
+ GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
+ GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
+ GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
+ GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
+ EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
+};
+
+static const struct samsung_cmu_info peri_cmu __initconst = {
+ .mux_clks = peri_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
+ .div_clks = peri_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peri_div_clks),
+ .gate_clks = peri_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
+ .nr_clk_ids = PERI_NR_CLK,
+ .clk_regs = peri_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
+};
+
+static void __init exynos5260_clk_peri_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peri_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
+ exynos5260_clk_peri_init);
+
+
+/* CMU_TOP */
+
+static const unsigned long top_clk_regs[] __initconst = {
+ DISP_PLL_LOCK,
+ AUD_PLL_LOCK,
+ DISP_PLL_CON0,
+ DISP_PLL_CON1,
+ DISP_PLL_FDET,
+ AUD_PLL_CON0,
+ AUD_PLL_CON1,
+ AUD_PLL_CON2,
+ AUD_PLL_FDET,
+ MUX_SEL_TOP_PLL0,
+ MUX_SEL_TOP_MFC,
+ MUX_SEL_TOP_G2D,
+ MUX_SEL_TOP_GSCL,
+ MUX_SEL_TOP_ISP10,
+ MUX_SEL_TOP_ISP11,
+ MUX_SEL_TOP_DISP0,
+ MUX_SEL_TOP_DISP1,
+ MUX_SEL_TOP_BUS,
+ MUX_SEL_TOP_PERI0,
+ MUX_SEL_TOP_PERI1,
+ MUX_SEL_TOP_FSYS,
+ DIV_TOP_G2D_MFC,
+ DIV_TOP_GSCL_ISP0,
+ DIV_TOP_ISP10,
+ DIV_TOP_ISP11,
+ DIV_TOP_DISP,
+ DIV_TOP_BUS,
+ DIV_TOP_PERI0,
+ DIV_TOP_PERI1,
+ DIV_TOP_PERI2,
+ DIV_TOP_FSYS0,
+ DIV_TOP_FSYS1,
+ DIV_TOP_HPM,
+ DIV_TOP_PLL_FDET,
+ EN_ACLK_TOP,
+ EN_SCLK_TOP,
+ EN_IP_TOP,
+};
+
+/* fixed rate clocks generated inside the soc */
+static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
+ FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
+ 0, 270000000),
+ FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
+ 0, 270000000),
+ FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
+ 0, 270000000),
+ FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
+ 0, 270000000),
+ FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
+ 0, 250000000),
+ FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
+ 0, 1660000000),
+ FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
+ NULL, 0, 125000000),
+ FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
+ "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
+ 0, 187500000),
+ FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
+ NULL, 0, 24000000),
+ FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
+ 0, 135000000),
+ FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
+ "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),
+ FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
+ NULL, 0, 60000000),
+ FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
+ NULL, 0, 60000000),
+ FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
+ "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),
+ FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
+ "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),
+ FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
+ "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),
+};
+
+PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
+PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
+PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
+PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
+PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
+PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
+PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
+PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
+PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
+ "mout_gscl_bustop_333"};
+PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
+ "mout_m2m_mediatop_400"};
+PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
+ "mout_gscl_bustop_fimc"};
+PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
+ "mout_memtop_pll_user"};
+PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
+PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
+PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
+PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
+PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
+PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
+PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
+PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
+ "mout_bustop_pll_user"};
+PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
+PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
+PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
+PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
+PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
+ "mout_mediatop_pll_user"};
+PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
+ "mout_mediatop_pll_user"};
+PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
+ "mout_mediatop_pll_user"};
+
+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
+ MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
+ mout_mediatop_pll_user_p,
+ MUX_SEL_TOP_PLL0, 0, 1),
+ MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
+ mout_memtop_pll_user_p,
+ MUX_SEL_TOP_PLL0, 4, 1),
+ MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
+ mout_bustop_pll_user_p,
+ MUX_SEL_TOP_PLL0, 8, 1),
+ MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+ MUX_SEL_TOP_PLL0, 12, 1),
+ MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
+ MUX_SEL_TOP_PLL0, 16, 1),
+ MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
+ mout_audtop_pll_user_p,
+ MUX_SEL_TOP_PLL0, 24, 1),
+
+ MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
+ MUX_SEL_TOP_DISP0, 0, 1),
+ MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
+ MUX_SEL_TOP_DISP0, 8, 1),
+ MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
+ MUX_SEL_TOP_DISP0, 12, 1),
+ MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
+ MUX_SEL_TOP_DISP0, 20, 1),
+
+ MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
+ MUX_SEL_TOP_DISP1, 0, 1),
+ MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
+ mout_disp_media_pixel_p,
+ MUX_SEL_TOP_DISP1, 8, 1),
+
+ MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
+ mout_sclk_peri_spi_clk_p,
+ MUX_SEL_TOP_PERI1, 0, 1),
+ MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
+ mout_sclk_peri_spi_clk_p,
+ MUX_SEL_TOP_PERI1, 4, 1),
+ MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
+ mout_sclk_peri_spi_clk_p,
+ MUX_SEL_TOP_PERI1, 8, 1),
+ MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
+ mout_sclk_peri_uart_uclk_p,
+ MUX_SEL_TOP_PERI1, 12, 1),
+ MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
+ mout_sclk_peri_uart_uclk_p,
+ MUX_SEL_TOP_PERI1, 16, 1),
+ MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
+ mout_sclk_peri_uart_uclk_p,
+ MUX_SEL_TOP_PERI1, 20, 1),
+
+
+ MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
+ mout_bus_bustop_400_p,
+ MUX_SEL_TOP_BUS, 0, 1),
+ MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
+ mout_bus_bustop_100_p,
+ MUX_SEL_TOP_BUS, 4, 1),
+ MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
+ mout_bus_bustop_100_p,
+ MUX_SEL_TOP_BUS, 8, 1),
+ MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
+ mout_bus_bustop_400_p,
+ MUX_SEL_TOP_BUS, 12, 1),
+ MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
+ mout_bus_bustop_400_p,
+ MUX_SEL_TOP_BUS, 16, 1),
+ MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
+ mout_bus_bustop_100_p,
+ MUX_SEL_TOP_BUS, 20, 1),
+ MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
+ mout_bus_bustop_400_p,
+ MUX_SEL_TOP_BUS, 24, 1),
+ MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
+ mout_bus_bustop_100_p,
+ MUX_SEL_TOP_BUS, 28, 1),
+
+ MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
+ mout_sclk_fsys_usb_p,
+ MUX_SEL_TOP_FSYS, 0, 1),
+ MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
+ mout_sclk_fsys_mmc_sdclkin_a_p,
+ MUX_SEL_TOP_FSYS, 4, 1),
+ MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
+ mout_sclk_fsys_mmc2_sdclkin_b_p,
+ MUX_SEL_TOP_FSYS, 8, 1),
+ MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
+ mout_sclk_fsys_mmc_sdclkin_a_p,
+ MUX_SEL_TOP_FSYS, 12, 1),
+ MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
+ mout_sclk_fsys_mmc1_sdclkin_b_p,
+ MUX_SEL_TOP_FSYS, 16, 1),
+ MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
+ mout_sclk_fsys_mmc_sdclkin_a_p,
+ MUX_SEL_TOP_FSYS, 20, 1),
+ MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
+ mout_sclk_fsys_mmc0_sdclkin_b_p,
+ MUX_SEL_TOP_FSYS, 24, 1),
+
+ MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
+ mout_isp1_media_400_p,
+ MUX_SEL_TOP_ISP10, 4, 1),
+ MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
+ MUX_SEL_TOP_ISP10, 8 , 1),
+ MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
+ mout_isp1_media_266_p,
+ MUX_SEL_TOP_ISP10, 16, 1),
+ MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
+ MUX_SEL_TOP_ISP10, 20, 1),
+
+ MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
+ MUX_SEL_TOP_ISP11, 4, 1),
+ MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
+ MUX_SEL_TOP_ISP11, 8, 1),
+ MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
+ mout_sclk_isp_uart_p,
+ MUX_SEL_TOP_ISP11, 12, 1),
+ MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
+ mout_sclk_isp_sensor_p,
+ MUX_SEL_TOP_ISP11, 16, 1),
+ MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
+ mout_sclk_isp_sensor_p,
+ MUX_SEL_TOP_ISP11, 20, 1),
+ MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
+ mout_sclk_isp_sensor_p,
+ MUX_SEL_TOP_ISP11, 24, 1),
+
+ MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
+ mout_mfc_bustop_333_p,
+ MUX_SEL_TOP_MFC, 4, 1),
+ MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
+ MUX_SEL_TOP_MFC, 8, 1),
+
+ MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
+ mout_g2d_bustop_333_p,
+ MUX_SEL_TOP_G2D, 4, 1),
+ MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
+ MUX_SEL_TOP_G2D, 8, 1),
+
+ MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
+ mout_m2m_mediatop_400_p,
+ MUX_SEL_TOP_GSCL, 0, 1),
+ MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
+ mout_aclk_gscl_400_p,
+ MUX_SEL_TOP_GSCL, 4, 1),
+ MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
+ mout_gscl_bustop_333_p,
+ MUX_SEL_TOP_GSCL, 8, 1),
+ MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
+ mout_aclk_gscl_333_p,
+ MUX_SEL_TOP_GSCL, 12, 1),
+ MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
+ mout_gscl_bustop_fimc_p,
+ MUX_SEL_TOP_GSCL, 16, 1),
+ MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
+ mout_aclk_gscl_fimc_p,
+ MUX_SEL_TOP_GSCL, 20, 1),
+};
+
+static const struct samsung_div_clock top_div_clks[] __initconst = {
+ DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
+ DIV_TOP_G2D_MFC, 0, 3),
+ DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
+ DIV_TOP_G2D_MFC, 4, 3),
+
+ DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
+ DIV_TOP_GSCL_ISP0, 0, 3),
+ DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
+ DIV_TOP_GSCL_ISP0, 4, 3),
+ DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
+ "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
+ DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
+ "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
+ "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
+ "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
+
+ DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
+ DIV_TOP_ISP10, 0, 3),
+ DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
+ DIV_TOP_ISP10, 4, 3),
+ DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
+ "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
+ "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
+
+ DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
+ "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
+ "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
+ DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
+ "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
+ "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
+ "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
+ DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
+ "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
+
+ DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
+ "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
+
+ DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
+ DIV_TOP_DISP, 0, 3),
+ DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
+ DIV_TOP_DISP, 4, 3),
+ DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
+ "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
+
+ DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
+ "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
+ DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
+ "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
+ DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
+ "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
+ DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
+ "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
+ DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
+ "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
+ DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
+ "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
+ DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
+ "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
+ DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
+ "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
+
+ DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
+ "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
+ DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
+ "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
+ DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
+ "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
+ DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
+ "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
+
+ DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
+ "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
+ DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
+ "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
+ DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
+ "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
+ DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
+ "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
+ DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
+ "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
+
+ DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
+ DIV_TOP_PERI2, 20, 4),
+ DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
+ "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
+
+ DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
+ "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
+ DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
+ "dout_sclk_fsys_usbdrd30_suspend_clk",
+ "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
+ DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
+ "mout_sclk_fsys_mmc0_sdclkin_b",
+ DIV_TOP_FSYS0, 12, 4),
+ DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
+ "dout_sclk_fsys_mmc0_sdclkin_a",
+ DIV_TOP_FSYS0, 16, 8),
+
+
+ DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
+ "mout_sclk_fsys_mmc1_sdclkin_b",
+ DIV_TOP_FSYS1, 0, 4),
+ DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
+ "dout_sclk_fsys_mmc1_sdclkin_a",
+ DIV_TOP_FSYS1, 4, 8),
+ DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
+ "mout_sclk_fsys_mmc2_sdclkin_b",
+ DIV_TOP_FSYS1, 12, 4),
+ DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
+ "dout_sclk_fsys_mmc2_sdclkin_a",
+ DIV_TOP_FSYS1, 16, 8),
+
+};
+
+static const struct samsung_gate_clock top_gate_clks[] __initconst = {
+ GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
+ "dout_sclk_fsys_mmc0_sdclkin_b",
+ EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
+ "dout_sclk_fsys_mmc1_sdclkin_b",
+ EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
+ "dout_sclk_fsys_mmc2_sdclkin_b",
+ EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
+ EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
+ CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
+ PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
+ DISP_PLL_LOCK, DISP_PLL_CON0,
+ pll2550_24mhz_tbl),
+ PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
+ AUD_PLL_LOCK, AUD_PLL_CON0,
+ pll2650_24mhz_tbl),
+};
+
+static const struct samsung_cmu_info top_cmu __initconst = {
+ .pll_clks = top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
+ .mux_clks = top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
+ .div_clks = top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .gate_clks = top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
+ .fixed_clks = fixed_rate_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
+ .nr_clk_ids = TOP_NR_CLK,
+ .clk_regs = top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos5260_clk_top_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &top_cmu);
+}
+
+CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
+ exynos5260_clk_top_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Rahul Sharma <rahul.sharma@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5260 SoC.
+ */
+
+#ifndef __CLK_EXYNOS5260_H
+#define __CLK_EXYNOS5260_H
+
+/*
+*Registers for CMU_AUD
+*/
+#define MUX_SEL_AUD 0x0200
+#define MUX_ENABLE_AUD 0x0300
+#define MUX_STAT_AUD 0x0400
+#define MUX_IGNORE_AUD 0x0500
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define EN_ACLK_AUD 0x0800
+#define EN_PCLK_AUD 0x0900
+#define EN_SCLK_AUD 0x0a00
+#define EN_IP_AUD 0x0b00
+
+/*
+*Registers for CMU_DISP
+*/
+#define MUX_SEL_DISP0 0x0200
+#define MUX_SEL_DISP1 0x0204
+#define MUX_SEL_DISP2 0x0208
+#define MUX_SEL_DISP3 0x020C
+#define MUX_SEL_DISP4 0x0210
+#define MUX_ENABLE_DISP0 0x0300
+#define MUX_ENABLE_DISP1 0x0304
+#define MUX_ENABLE_DISP2 0x0308
+#define MUX_ENABLE_DISP3 0x030c
+#define MUX_ENABLE_DISP4 0x0310
+#define MUX_STAT_DISP0 0x0400
+#define MUX_STAT_DISP1 0x0404
+#define MUX_STAT_DISP2 0x0408
+#define MUX_STAT_DISP3 0x040c
+#define MUX_STAT_DISP4 0x0410
+#define MUX_IGNORE_DISP0 0x0500
+#define MUX_IGNORE_DISP1 0x0504
+#define MUX_IGNORE_DISP2 0x0508
+#define MUX_IGNORE_DISP3 0x050c
+#define MUX_IGNORE_DISP4 0x0510
+#define DIV_DISP 0x0600
+#define DIV_STAT_DISP 0x0700
+#define EN_ACLK_DISP 0x0800
+#define EN_PCLK_DISP 0x0900
+#define EN_SCLK_DISP0 0x0a00
+#define EN_SCLK_DISP1 0x0a04
+#define EN_IP_DISP 0x0b00
+#define EN_IP_DISP_BUS 0x0b04
+
+
+/*
+*Registers for CMU_EGL
+*/
+#define EGL_PLL_LOCK 0x0000
+#define EGL_DPLL_LOCK 0x0004
+#define EGL_PLL_CON0 0x0100
+#define EGL_PLL_CON1 0x0104
+#define EGL_PLL_FREQ_DET 0x010c
+#define EGL_DPLL_CON0 0x0110
+#define EGL_DPLL_CON1 0x0114
+#define EGL_DPLL_FREQ_DET 0x011c
+#define MUX_SEL_EGL 0x0200
+#define MUX_ENABLE_EGL 0x0300
+#define MUX_STAT_EGL 0x0400
+#define DIV_EGL 0x0600
+#define DIV_EGL_PLL_FDET 0x0604
+#define DIV_STAT_EGL 0x0700
+#define DIV_STAT_EGL_PLL_FDET 0x0704
+#define EN_ACLK_EGL 0x0800
+#define EN_PCLK_EGL 0x0900
+#define EN_SCLK_EGL 0x0a00
+#define EN_IP_EGL 0x0b00
+#define CLKOUT_CMU_EGL 0x0c00
+#define CLKOUT_CMU_EGL_DIV_STAT 0x0c04
+#define ARMCLK_STOPCTRL 0x1000
+#define EAGLE_EMA_CTRL 0x1008
+#define EAGLE_EMA_STATUS 0x100c
+#define PWR_CTRL 0x1020
+#define PWR_CTRL2 0x1024
+#define CLKSTOP_CTRL 0x1028
+#define INTR_SPREAD_EN 0x1080
+#define INTR_SPREAD_USE_STANDBYWFI 0x1084
+#define INTR_SPREAD_BLOCKING_DURATION 0x1088
+#define CMU_EGL_SPARE0 0x2000
+#define CMU_EGL_SPARE1 0x2004
+#define CMU_EGL_SPARE2 0x2008
+#define CMU_EGL_SPARE3 0x200c
+#define CMU_EGL_SPARE4 0x2010
+
+/*
+*Registers for CMU_FSYS
+*/
+
+#define MUX_SEL_FSYS0 0x0200
+#define MUX_SEL_FSYS1 0x0204
+#define MUX_ENABLE_FSYS0 0x0300
+#define MUX_ENABLE_FSYS1 0x0304
+#define MUX_STAT_FSYS0 0x0400
+#define MUX_STAT_FSYS1 0x0404
+#define MUX_IGNORE_FSYS0 0x0500
+#define MUX_IGNORE_FSYS1 0x0504
+#define EN_ACLK_FSYS 0x0800
+#define EN_ACLK_FSYS_SECURE_RTIC 0x0804
+#define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808
+#define EN_PCLK_FSYS 0x0900
+#define EN_SCLK_FSYS 0x0a00
+#define EN_IP_FSYS 0x0b00
+#define EN_IP_FSYS_SECURE_RTIC 0x0b04
+#define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08
+
+/*
+*Registers for CMU_G2D
+*/
+
+#define MUX_SEL_G2D 0x0200
+#define MUX_ENABLE_G2D 0x0300
+#define MUX_STAT_G2D 0x0400
+#define DIV_G2D 0x0600
+#define DIV_STAT_G2D 0x0700
+#define EN_ACLK_G2D 0x0800
+#define EN_ACLK_G2D_SECURE_SSS 0x0804
+#define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808
+#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c
+#define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810
+#define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814
+#define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818
+#define EN_PCLK_G2D 0x0900
+#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904
+#define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908
+#define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c
+#define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910
+#define EN_IP_G2D 0x0b00
+#define EN_IP_G2D_SECURE_SSS 0x0b04
+#define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08
+#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c
+#define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10
+#define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14
+#define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18
+
+/*
+*Registers for CMU_G3D
+*/
+
+#define G3D_PLL_LOCK 0x0000
+#define G3D_PLL_CON0 0x0100
+#define G3D_PLL_CON1 0x0104
+#define G3D_PLL_FDET 0x010c
+#define MUX_SEL_G3D 0x0200
+#define MUX_EN_G3D 0x0300
+#define MUX_STAT_G3D 0x0400
+#define MUX_IGNORE_G3D 0x0500
+#define DIV_G3D 0x0600
+#define DIV_G3D_PLL_FDET 0x0604
+#define DIV_STAT_G3D 0x0700
+#define DIV_STAT_G3D_PLL_FDET 0x0704
+#define EN_ACLK_G3D 0x0800
+#define EN_PCLK_G3D 0x0900
+#define EN_SCLK_G3D 0x0a00
+#define EN_IP_G3D 0x0b00
+#define CLKOUT_CMU_G3D 0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
+#define G3DCLK_STOPCTRL 0x1000
+#define G3D_EMA_CTRL 0x1008
+#define G3D_EMA_STATUS 0x100c
+
+/*
+*Registers for CMU_GSCL
+*/
+
+#define MUX_SEL_GSCL 0x0200
+#define MUX_EN_GSCL 0x0300
+#define MUX_STAT_GSCL 0x0400
+#define MUX_IGNORE_GSCL 0x0500
+#define DIV_GSCL 0x0600
+#define DIV_STAT_GSCL 0x0700
+#define EN_ACLK_GSCL 0x0800
+#define EN_ACLK_GSCL_FIMC 0x0804
+#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808
+#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c
+#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810
+#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814
+#define EN_PCLK_GSCL 0x0900
+#define EN_PCLK_GSCL_FIMC 0x0904
+#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908
+#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c
+#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910
+#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914
+#define EN_SCLK_GSCL 0x0a00
+#define EN_SCLK_GSCL_FIMC 0x0a04
+#define EN_IP_GSCL 0x0b00
+#define EN_IP_GSCL_FIMC 0x0b04
+#define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
+#define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
+#define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10
+#define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14
+
+/*
+*Registers for CMU_ISP
+*/
+#define MUX_SEL_ISP0 0x0200
+#define MUX_SEL_ISP1 0x0204
+#define MUX_ENABLE_ISP0 0x0300
+#define MUX_ENABLE_ISP1 0x0304
+#define MUX_STAT_ISP0 0x0400
+#define MUX_STAT_ISP1 0x0404
+#define MUX_IGNORE_ISP0 0x0500
+#define MUX_IGNORE_ISP1 0x0504
+#define DIV_ISP 0x0600
+#define DIV_STAT_ISP 0x0700
+#define EN_ACLK_ISP0 0x0800
+#define EN_ACLK_ISP1 0x0804
+#define EN_PCLK_ISP0 0x0900
+#define EN_PCLK_ISP1 0x0904
+#define EN_SCLK_ISP 0x0a00
+#define EN_IP_ISP0 0x0b00
+#define EN_IP_ISP1 0x0b04
+
+/*
+*Registers for CMU_KFC
+*/
+#define KFC_PLL_LOCK 0x0000
+#define KFC_PLL_CON0 0x0100
+#define KFC_PLL_CON1 0x0104
+#define KFC_PLL_FDET 0x010c
+#define MUX_SEL_KFC0 0x0200
+#define MUX_SEL_KFC2 0x0208
+#define MUX_ENABLE_KFC0 0x0300
+#define MUX_ENABLE_KFC2 0x0308
+#define MUX_STAT_KFC0 0x0400
+#define MUX_STAT_KFC2 0x0408
+#define DIV_KFC 0x0600
+#define DIV_KFC_PLL_FDET 0x0604
+#define DIV_STAT_KFC 0x0700
+#define DIV_STAT_KFC_PLL_FDET 0x0704
+#define EN_ACLK_KFC 0x0800
+#define EN_PCLK_KFC 0x0900
+#define EN_SCLK_KFC 0x0a00
+#define EN_IP_KFC 0x0b00
+#define CLKOUT_CMU_KFC 0x0c00
+#define CLKOUT_CMU_KFC_DIV_STAT 0x0c04
+#define ARMCLK_STOPCTRL_KFC 0x1000
+#define ARM_EMA_CTRL 0x1008
+#define ARM_EMA_STATUS 0x100c
+#define PWR_CTRL_KFC 0x1020
+#define PWR_CTRL2_KFC 0x1024
+#define CLKSTOP_CTRL_KFC 0x1028
+#define INTR_SPREAD_ENABLE_KFC 0x1080
+#define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084
+#define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088
+#define CMU_KFC_SPARE0 0x2000
+#define CMU_KFC_SPARE1 0x2004
+#define CMU_KFC_SPARE2 0x2008
+#define CMU_KFC_SPARE3 0x200c
+#define CMU_KFC_SPARE4 0x2010
+
+/*
+*Registers for CMU_MFC
+*/
+#define MUX_SEL_MFC 0x0200
+#define MUX_ENABLE_MFC 0x0300
+#define MUX_STAT_MFC 0x0400
+#define DIV_MFC 0x0600
+#define DIV_STAT_MFC 0x0700
+#define EN_ACLK_MFC 0x0800
+#define EN_ACLK_SECURE_SMMU2_MFC 0x0804
+#define EN_PCLK_MFC 0x0900
+#define EN_PCLK_SECURE_SMMU2_MFC 0x0904
+#define EN_IP_MFC 0x0b00
+#define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04
+
+/*
+*Registers for CMU_MIF
+*/
+#define MEM_PLL_LOCK 0x0000
+#define BUS_PLL_LOCK 0x0004
+#define MEDIA_PLL_LOCK 0x0008
+#define MEM_PLL_CON0 0x0100
+#define MEM_PLL_CON1 0x0104
+#define MEM_PLL_FDET 0x010c
+#define BUS_PLL_CON0 0x0110
+#define BUS_PLL_CON1 0x0114
+#define BUS_PLL_FDET 0x011c
+#define MEDIA_PLL_CON0 0x0120
+#define MEDIA_PLL_CON1 0x0124
+#define MEDIA_PLL_FDET 0x012c
+#define MUX_SEL_MIF 0x0200
+#define MUX_ENABLE_MIF 0x0300
+#define MUX_STAT_MIF 0x0400
+#define MUX_IGNORE_MIF 0x0500
+#define DIV_MIF 0x0600
+#define DIV_MIF_PLL_FDET 0x0604
+#define DIV_STAT_MIF 0x0700
+#define DIV_STAT_MIF_PLL_FDET 0x0704
+#define EN_ACLK_MIF 0x0800
+#define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804
+#define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808
+#define EN_ACLK_MIF_SECURE_INTMEM 0x080c
+#define EN_PCLK_MIF 0x0900
+#define EN_PCLK_MIF_SECURE_MONOCNT 0x0904
+#define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908
+#define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c
+#define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910
+#define EN_SCLK_MIF 0x0a00
+#define EN_IP_MIF 0x0b00
+#define EN_IP_MIF_SECURE_MONOCNT 0x0b04
+#define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08
+#define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c
+#define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define EN_IP_MIF_SECURE_INTEMEM 0x0b14
+#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
+#define DREX_FREQ_CTRL 0x1000
+#define PAUSE 0x1004
+#define DDRPHY_LOCK_CTRL 0x1008
+#define CLKOUT_CMU_MIF 0xcb00
+
+/*
+*Registers for CMU_PERI
+*/
+#define MUX_SEL_PERI 0x0200
+#define MUX_SEL_PERI1 0x0204
+#define MUX_ENABLE_PERI 0x0300
+#define MUX_ENABLE_PERI1 0x0304
+#define MUX_STAT_PERI 0x0400
+#define MUX_STAT_PERI1 0x0404
+#define MUX_IGNORE_PERI 0x0500
+#define MUX_IGNORE_PERI1 0x0504
+#define DIV_PERI 0x0600
+#define DIV_STAT_PERI 0x0700
+#define EN_PCLK_PERI0 0x0800
+#define EN_PCLK_PERI1 0x0804
+#define EN_PCLK_PERI2 0x0808
+#define EN_PCLK_PERI3 0x080c
+#define EN_PCLK_PERI_SECURE_CHIPID 0x0810
+#define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814
+#define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818
+#define EN_PCLK_PERI_SECURE_SECKEY 0x081c
+#define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820
+#define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824
+#define EN_PCLK_PERI_SECURE_TZPC 0x0828
+#define EN_SCLK_PERI 0x0a00
+#define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04
+#define EN_IP_PERI0 0x0b00
+#define EN_IP_PERI1 0x0b04
+#define EN_IP_PERI2 0x0b08
+#define EN_IP_PERI_SECURE_CHIPID 0x0b0c
+#define EN_IP_PERI_SECURE_PROVKEY0 0x0b10
+#define EN_IP_PERI_SECURE_PROVKEY1 0x0b14
+#define EN_IP_PERI_SECURE_SECKEY 0x0b18
+#define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c
+#define EN_IP_PERI_SECURE_TOP_RTC 0x0b20
+#define EN_IP_PERI_SECURE_TZPC 0x0b24
+
+/*
+*Registers for CMU_TOP
+*/
+#define DISP_PLL_LOCK 0x0000
+#define AUD_PLL_LOCK 0x0004
+#define DISP_PLL_CON0 0x0100
+#define DISP_PLL_CON1 0x0104
+#define DISP_PLL_FDET 0x0108
+#define AUD_PLL_CON0 0x0110
+#define AUD_PLL_CON1 0x0114
+#define AUD_PLL_CON2 0x0118
+#define AUD_PLL_FDET 0x011c
+#define MUX_SEL_TOP_PLL0 0x0200
+#define MUX_SEL_TOP_MFC 0x0204
+#define MUX_SEL_TOP_G2D 0x0208
+#define MUX_SEL_TOP_GSCL 0x020c
+#define MUX_SEL_TOP_ISP10 0x0214
+#define MUX_SEL_TOP_ISP11 0x0218
+#define MUX_SEL_TOP_DISP0 0x021c
+#define MUX_SEL_TOP_DISP1 0x0220
+#define MUX_SEL_TOP_BUS 0x0224
+#define MUX_SEL_TOP_PERI0 0x0228
+#define MUX_SEL_TOP_PERI1 0x022c
+#define MUX_SEL_TOP_FSYS 0x0230
+#define MUX_ENABLE_TOP_PLL0 0x0300
+#define MUX_ENABLE_TOP_MFC 0x0304
+#define MUX_ENABLE_TOP_G2D 0x0308
+#define MUX_ENABLE_TOP_GSCL 0x030c
+#define MUX_ENABLE_TOP_ISP10 0x0314
+#define MUX_ENABLE_TOP_ISP11 0x0318
+#define MUX_ENABLE_TOP_DISP0 0x031c
+#define MUX_ENABLE_TOP_DISP1 0x0320
+#define MUX_ENABLE_TOP_BUS 0x0324
+#define MUX_ENABLE_TOP_PERI0 0x0328
+#define MUX_ENABLE_TOP_PERI1 0x032c
+#define MUX_ENABLE_TOP_FSYS 0x0330
+#define MUX_STAT_TOP_PLL0 0x0400
+#define MUX_STAT_TOP_MFC 0x0404
+#define MUX_STAT_TOP_G2D 0x0408
+#define MUX_STAT_TOP_GSCL 0x040c
+#define MUX_STAT_TOP_ISP10 0x0414
+#define MUX_STAT_TOP_ISP11 0x0418
+#define MUX_STAT_TOP_DISP0 0x041c
+#define MUX_STAT_TOP_DISP1 0x0420
+#define MUX_STAT_TOP_BUS 0x0424
+#define MUX_STAT_TOP_PERI0 0x0428
+#define MUX_STAT_TOP_PERI1 0x042c
+#define MUX_STAT_TOP_FSYS 0x0430
+#define MUX_IGNORE_TOP_PLL0 0x0500
+#define MUX_IGNORE_TOP_MFC 0x0504
+#define MUX_IGNORE_TOP_G2D 0x0508
+#define MUX_IGNORE_TOP_GSCL 0x050c
+#define MUX_IGNORE_TOP_ISP10 0x0514
+#define MUX_IGNORE_TOP_ISP11 0x0518
+#define MUX_IGNORE_TOP_DISP0 0x051c
+#define MUX_IGNORE_TOP_DISP1 0x0520
+#define MUX_IGNORE_TOP_BUS 0x0524
+#define MUX_IGNORE_TOP_PERI0 0x0528
+#define MUX_IGNORE_TOP_PERI1 0x052c
+#define MUX_IGNORE_TOP_FSYS 0x0530
+#define DIV_TOP_G2D_MFC 0x0600
+#define DIV_TOP_GSCL_ISP0 0x0604
+#define DIV_TOP_ISP10 0x0608
+#define DIV_TOP_ISP11 0x060c
+#define DIV_TOP_DISP 0x0610
+#define DIV_TOP_BUS 0x0614
+#define DIV_TOP_PERI0 0x0618
+#define DIV_TOP_PERI1 0x061c
+#define DIV_TOP_PERI2 0x0620
+#define DIV_TOP_FSYS0 0x0624
+#define DIV_TOP_FSYS1 0x0628
+#define DIV_TOP_HPM 0x062c
+#define DIV_TOP_PLL_FDET 0x0630
+#define DIV_STAT_TOP_G2D_MFC 0x0700
+#define DIV_STAT_TOP_GSCL_ISP0 0x0704
+#define DIV_STAT_TOP_ISP10 0x0708
+#define DIV_STAT_TOP_ISP11 0x070c
+#define DIV_STAT_TOP_DISP 0x0710
+#define DIV_STAT_TOP_BUS 0x0714
+#define DIV_STAT_TOP_PERI0 0x0718
+#define DIV_STAT_TOP_PERI1 0x071c
+#define DIV_STAT_TOP_PERI2 0x0720
+#define DIV_STAT_TOP_FSYS0 0x0724
+#define DIV_STAT_TOP_FSYS1 0x0728
+#define DIV_STAT_TOP_HPM 0x072c
+#define DIV_STAT_TOP_PLL_FDET 0x0730
+#define EN_ACLK_TOP 0x0800
+#define EN_SCLK_TOP 0x0a00
+#define EN_IP_TOP 0x0b00
+#define CLKOUT_CMU_TOP 0x0c00
+#define CLKOUT_CMU_TOP_DIV_STAT 0x0c04
+
+#endif /*__CLK_EXYNOS5260_H */
+
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5410.h>
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define EPLL_LOCK 0x10040
+#define EPLL_CON0 0x10130
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define GATE_IP_G2D 0x8800
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS0 0x10548
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define DIV_PERIC3 0x10564
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC0 0x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_TOP_SCLK_FSYS 0x10840
+#define GATE_TOP_SCLK_PERIC 0x10850
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC 0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, epll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+/* list of all parent clocks */
+PNAME(apll_p) = { "fin_pll", "fout_apll", };
+PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
+PNAME(epll_p) = { "fin_pll", "fout_epll" };
+PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
+
+PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
+PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
+
+PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
+PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
+
+PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
+ "none", "none", "sclk_mpll_bpll",
+ "none", "none", "sclk_cpll" };
+
+static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = {
+ MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+ MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+
+ MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+ MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+ MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
+ MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
+
+ MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+ MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
+
+ MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
+
+ MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
+
+ MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
+
+ MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+ MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
+ MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
+
+ MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
+ MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
+ MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+ MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
+ MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
+
+ MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
+};
+
+static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
+ DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
+
+ DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
+ DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
+ DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
+ DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
+
+ DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+ DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
+ DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
+
+ DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
+ DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+
+ DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+ DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
+ DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+ DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
+
+ DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+ DIV_F(0, "div_mmc_pre0", "div_mmc0",
+ DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre1", "div_mmc1",
+ DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre2", "div_mmc2",
+ DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+ DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+ DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+ DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+ DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+
+ DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+ DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
+ DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
+};
+
+static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
+ GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
+ GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+ GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
+ GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
+ GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
+
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
+ GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
+ GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
+
+ GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
+ GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
+ GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
+ GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
+ GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
+ GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+ GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+ GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+ GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+ GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
+ GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
+ GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
+ GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
+ GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
+ GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
+ GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
+ GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
+ GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
+
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+ SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+ GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+ GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {
+ PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
+ PLL_36XX_RATE(333000000U, 111, 2, 2, 0),
+ PLL_36XX_RATE(300000000U, 100, 2, 2, 0),
+ PLL_36XX_RATE(266000000U, 266, 3, 3, 0),
+ PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
+ PLL_36XX_RATE(192000000U, 192, 3, 3, 0),
+ PLL_36XX_RATE(166000000U, 166, 3, 3, 0),
+ PLL_36XX_RATE(133000000U, 266, 3, 4, 0),
+ PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
+ PLL_36XX_RATE(66000000U, 176, 2, 5, 0),
+};
+
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
+ EPLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
+};
+
+static const struct samsung_cmu_info cmu __initconst = {
+ .pll_clks = exynos5410_plls,
+ .nr_pll_clks = ARRAY_SIZE(exynos5410_plls),
+ .mux_clks = exynos5410_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(exynos5410_mux_clks),
+ .div_clks = exynos5410_div_clks,
+ .nr_div_clks = ARRAY_SIZE(exynos5410_div_clks),
+ .gate_clks = exynos5410_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks),
+ .nr_clk_ids = CLK_NR_CLKS,
+};
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+ struct clk *xxti = of_clk_get(np, 0);
+
+ if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)
+ exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl;
+
+ samsung_cmu_register_one(np, &cmu);
+
+ pr_debug("Exynos5410: clock setup completed.\n");
+}
+CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Thomas Abraham <thomas.ab@samsung.com>
+ * Chander Kashyap <k.chander@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5420 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5420.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include "clk.h"
+#include "clk-cpu.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define DIV_CPU1 0x504
+#define GATE_BUS_CPU 0x700
+#define GATE_SCLK_CPU 0x800
+#define CLKOUT_CMU_CPU 0xa00
+#define SRC_MASK_CPERI 0x4300
+#define GATE_IP_G2D 0x8800
+#define CPLL_LOCK 0x10020
+#define DPLL_LOCK 0x10030
+#define EPLL_LOCK 0x10040
+#define RPLL_LOCK 0x10050
+#define IPLL_LOCK 0x10060
+#define SPLL_LOCK 0x10070
+#define VPLL_LOCK 0x10080
+#define MPLL_LOCK 0x10090
+#define CPLL_CON0 0x10120
+#define DPLL_CON0 0x10128
+#define EPLL_CON0 0x10130
+#define EPLL_CON1 0x10134
+#define EPLL_CON2 0x10138
+#define RPLL_CON0 0x10140
+#define RPLL_CON1 0x10144
+#define RPLL_CON2 0x10148
+#define IPLL_CON0 0x10150
+#define SPLL_CON0 0x10160
+#define VPLL_CON0 0x10170
+#define MPLL_CON0 0x10180
+#define SRC_TOP0 0x10200
+#define SRC_TOP1 0x10204
+#define SRC_TOP2 0x10208
+#define SRC_TOP3 0x1020c
+#define SRC_TOP4 0x10210
+#define SRC_TOP5 0x10214
+#define SRC_TOP6 0x10218
+#define SRC_TOP7 0x1021c
+#define SRC_TOP8 0x10220 /* 5800 specific */
+#define SRC_TOP9 0x10224 /* 5800 specific */
+#define SRC_DISP10 0x1022c
+#define SRC_MAU 0x10240
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_PERIC1 0x10254
+#define SRC_ISP 0x10270
+#define SRC_CAM 0x10274 /* 5800 specific */
+#define SRC_TOP10 0x10280
+#define SRC_TOP11 0x10284
+#define SRC_TOP12 0x10288
+#define SRC_TOP13 0x1028c /* 5800 specific */
+#define SRC_MASK_TOP0 0x10300
+#define SRC_MASK_TOP1 0x10304
+#define SRC_MASK_TOP2 0x10308
+#define SRC_MASK_TOP7 0x1031c
+#define SRC_MASK_DISP10 0x1032c
+#define SRC_MASK_MAU 0x10334
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC0 0x10350
+#define SRC_MASK_PERIC1 0x10354
+#define SRC_MASK_ISP 0x10370
+#define DIV_TOP0 0x10500
+#define DIV_TOP1 0x10504
+#define DIV_TOP2 0x10508
+#define DIV_TOP8 0x10520 /* 5800 specific */
+#define DIV_TOP9 0x10524 /* 5800 specific */
+#define DIV_DISP10 0x1052c
+#define DIV_MAU 0x10544
+#define DIV_FSYS0 0x10548
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define DIV_PERIC1 0x1055c
+#define DIV_PERIC2 0x10560
+#define DIV_PERIC3 0x10564
+#define DIV_PERIC4 0x10568
+#define DIV_CAM 0x10574 /* 5800 specific */
+#define SCLK_DIV_ISP0 0x10580
+#define SCLK_DIV_ISP1 0x10584
+#define DIV2_RATIO0 0x10590
+#define DIV4_RATIO 0x105a0
+#define GATE_BUS_TOP 0x10700
+#define GATE_BUS_DISP1 0x10728
+#define GATE_BUS_GEN 0x1073c
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_BUS_FSYS2 0x10748
+#define GATE_BUS_PERIC 0x10750
+#define GATE_BUS_PERIC1 0x10754
+#define GATE_BUS_PERIS0 0x10760
+#define GATE_BUS_PERIS1 0x10764
+#define GATE_BUS_NOC 0x10770
+#define GATE_TOP_SCLK_ISP 0x10870
+#define GATE_IP_GSCL0 0x10910
+#define GATE_IP_GSCL1 0x10920
+#define GATE_IP_CAM 0x10924 /* 5800 specific */
+#define GATE_IP_MFC 0x1092c
+#define GATE_IP_DISP1 0x10928
+#define GATE_IP_G3D 0x10930
+#define GATE_IP_GEN 0x10934
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define GATE_IP_MSCL 0x10970
+#define GATE_TOP_SCLK_GSCL 0x10820
+#define GATE_TOP_SCLK_DISP1 0x10828
+#define GATE_TOP_SCLK_MAU 0x1083c
+#define GATE_TOP_SCLK_FSYS 0x10840
+#define GATE_TOP_SCLK_PERIC 0x10850
+#define TOP_SPARE2 0x10b08
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define SRC_CDREX 0x20200
+#define DIV_CDREX0 0x20500
+#define DIV_CDREX1 0x20504
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+#define SRC_KFC 0x28200
+#define DIV_KFC0 0x28500
+
+/* Exynos5x SoC type */
+enum exynos5x_soc {
+ EXYNOS5420,
+ EXYNOS5800,
+};
+
+/* list of PLLs */
+enum exynos5x_plls {
+ apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+static void __iomem *reg_base;
+static enum exynos5x_soc exynos5x_soc;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos5x_save;
+static struct samsung_clk_reg_dump *exynos5800_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static const unsigned long exynos5x_clk_regs[] __initconst = {
+ SRC_CPU,
+ DIV_CPU0,
+ DIV_CPU1,
+ GATE_BUS_CPU,
+ GATE_SCLK_CPU,
+ CLKOUT_CMU_CPU,
+ EPLL_CON0,
+ EPLL_CON1,
+ EPLL_CON2,
+ RPLL_CON0,
+ RPLL_CON1,
+ RPLL_CON2,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_TOP3,
+ SRC_TOP4,
+ SRC_TOP5,
+ SRC_TOP6,
+ SRC_TOP7,
+ SRC_DISP10,
+ SRC_MAU,
+ SRC_FSYS,
+ SRC_PERIC0,
+ SRC_PERIC1,
+ SRC_TOP10,
+ SRC_TOP11,
+ SRC_TOP12,
+ SRC_MASK_TOP2,
+ SRC_MASK_TOP7,
+ SRC_MASK_DISP10,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIC0,
+ SRC_MASK_PERIC1,
+ SRC_MASK_TOP0,
+ SRC_MASK_TOP1,
+ SRC_MASK_MAU,
+ SRC_MASK_ISP,
+ SRC_ISP,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_TOP2,
+ DIV_DISP10,
+ DIV_MAU,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ DIV_PERIC1,
+ DIV_PERIC2,
+ DIV_PERIC3,
+ DIV_PERIC4,
+ SCLK_DIV_ISP0,
+ SCLK_DIV_ISP1,
+ DIV2_RATIO0,
+ DIV4_RATIO,
+ GATE_BUS_DISP1,
+ GATE_BUS_TOP,
+ GATE_BUS_GEN,
+ GATE_BUS_FSYS0,
+ GATE_BUS_FSYS2,
+ GATE_BUS_PERIC,
+ GATE_BUS_PERIC1,
+ GATE_BUS_PERIS0,
+ GATE_BUS_PERIS1,
+ GATE_BUS_NOC,
+ GATE_TOP_SCLK_ISP,
+ GATE_IP_GSCL0,
+ GATE_IP_GSCL1,
+ GATE_IP_MFC,
+ GATE_IP_DISP1,
+ GATE_IP_G3D,
+ GATE_IP_GEN,
+ GATE_IP_FSYS,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+ GATE_IP_MSCL,
+ GATE_TOP_SCLK_GSCL,
+ GATE_TOP_SCLK_DISP1,
+ GATE_TOP_SCLK_MAU,
+ GATE_TOP_SCLK_FSYS,
+ GATE_TOP_SCLK_PERIC,
+ TOP_SPARE2,
+ SRC_CDREX,
+ DIV_CDREX0,
+ DIV_CDREX1,
+ SRC_KFC,
+ DIV_KFC0,
+};
+
+static const unsigned long exynos5800_clk_regs[] __initconst = {
+ SRC_TOP8,
+ SRC_TOP9,
+ SRC_CAM,
+ SRC_TOP1,
+ DIV_TOP8,
+ DIV_TOP9,
+ DIV_CAM,
+ GATE_IP_CAM,
+};
+
+static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
+ { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
+ { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
+ { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
+ { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
+ { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
+ { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
+ { .offset = SRC_MASK_MAU, .value = 0x10000000, },
+ { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
+ { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
+ { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
+ { .offset = SRC_MASK_ISP, .value = 0x11111000, },
+ { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
+ { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
+ { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
+};
+
+static int exynos5420_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, exynos5x_save,
+ ARRAY_SIZE(exynos5x_clk_regs));
+
+ if (exynos5x_soc == EXYNOS5800)
+ samsung_clk_save(reg_base, exynos5800_save,
+ ARRAY_SIZE(exynos5800_clk_regs));
+
+ samsung_clk_restore(reg_base, exynos5420_set_clksrc,
+ ARRAY_SIZE(exynos5420_set_clksrc));
+
+ return 0;
+}
+
+static void exynos5420_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, exynos5x_save,
+ ARRAY_SIZE(exynos5x_clk_regs));
+
+ if (exynos5x_soc == EXYNOS5800)
+ samsung_clk_restore(reg_base, exynos5800_save,
+ ARRAY_SIZE(exynos5800_clk_regs));
+}
+
+static struct syscore_ops exynos5420_clk_syscore_ops = {
+ .suspend = exynos5420_clk_suspend,
+ .resume = exynos5420_clk_resume,
+};
+
+static void __init exynos5420_clk_sleep_init(void)
+{
+ exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
+ ARRAY_SIZE(exynos5x_clk_regs));
+ if (!exynos5x_save) {
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+ return;
+ }
+
+ if (exynos5x_soc == EXYNOS5800) {
+ exynos5800_save =
+ samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
+ ARRAY_SIZE(exynos5800_clk_regs));
+ if (!exynos5800_save)
+ goto err_soc;
+ }
+
+ register_syscore_ops(&exynos5420_clk_syscore_ops);
+ return;
+err_soc:
+ kfree(exynos5x_save);
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+ return;
+}
+#else
+static void __init exynos5420_clk_sleep_init(void) {}
+#endif
+
+/* list of all parent clocks */
+PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll"};
+PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
+PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
+PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
+PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
+PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
+PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
+PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
+PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
+PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
+PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
+PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
+PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
+PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
+
+PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll"};
+PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
+ "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
+ "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
+PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
+PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
+
+PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
+PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
+PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
+PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
+
+PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
+PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
+
+PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
+PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
+PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
+PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
+
+PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
+PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
+PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
+
+PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
+PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
+
+PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
+ "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
+
+PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
+
+PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
+PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
+
+PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
+
+PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
+
+PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
+PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
+
+PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
+PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
+PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
+
+PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
+
+PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
+
+PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
+PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
+PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
+
+PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
+
+PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
+PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
+
+PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
+PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
+
+PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
+
+PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
+ "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
+PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll"};
+PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
+
+/* List of parents specific to exynos5800 */
+PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
+PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "ff_dout_spll2" };
+PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "ff_dout_spll2",
+ "mout_epll2", "mout_sclk_ipll" };
+PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "ff_dout_spll2",
+ "mout_epll2" };
+PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll" };
+PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "ff_dout_spll2" };
+PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_spll",
+ "mout_epll2", "mout_sclk_ipll" };
+PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "ff_dout_spll2",
+ "mout_sclk_spll", "mout_sclk_epll"};
+PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
+ "mout_sclk_mpll",
+ "ff_dout_spll2" };
+PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
+PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
+PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
+PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
+PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
+PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
+PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
+PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
+
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock
+ exynos5x_fixed_rate_ext_clks[] __initdata = {
+ FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
+ FRATE(0, "sclk_pwi", NULL, 0, 24000000),
+ FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
+ FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
+ FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
+};
+
+static const struct samsung_fixed_factor_clock
+ exynos5x_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
+ FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
+};
+
+static const struct samsung_fixed_factor_clock
+ exynos5800_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
+ FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
+};
+
+static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
+ MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
+ MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
+ MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
+ MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
+
+ MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
+ MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
+ MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
+ MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
+ MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
+
+ MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
+ MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
+ MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
+ MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
+ MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
+ MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
+
+ MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
+ mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
+ MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
+ 20, 2),
+ MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
+ MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
+
+ MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
+ MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
+ MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
+ MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
+
+ MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
+ SRC_TOP9, 16, 1),
+ MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
+ SRC_TOP9, 20, 1),
+ MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
+ SRC_TOP9, 24, 1),
+ MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
+ SRC_TOP9, 28, 1),
+
+ MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
+ MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
+ SRC_TOP13, 20, 1),
+ MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
+ SRC_TOP13, 24, 1),
+ MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
+ SRC_TOP13, 28, 1),
+
+ MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
+};
+
+static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
+ DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
+ "mout_aclk400_wcore", DIV_TOP0, 16, 3),
+ DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
+ DIV_TOP8, 16, 3),
+ DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
+ DIV_TOP8, 20, 3),
+ DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
+ DIV_TOP8, 24, 3),
+ DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
+ DIV_TOP8, 28, 3),
+
+ DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
+ DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
+};
+
+static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
+ GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
+ GATE_BUS_TOP, 24, 0, 0),
+ GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
+ GATE_BUS_TOP, 27, 0, 0),
+};
+
+static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
+ MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
+ MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
+ TOP_SPARE2, 4, 1),
+
+ MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
+ MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
+ SRC_TOP0, 4, 2, "aclk400_mscl"),
+ MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
+ MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
+
+ MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
+ MUX(0, "mout_aclk333_432_isp", mout_group4_p,
+ SRC_TOP1, 4, 2),
+ MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
+ MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
+ MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
+
+ MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
+ MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
+ MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
+ MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
+ MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
+ MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
+
+ MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
+ mout_group5_5800_p, SRC_TOP7, 16, 2),
+ MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
+
+ MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
+};
+
+static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
+ DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
+ "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
+};
+
+static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
+ MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
+ SRC_TOP7, 4, 1),
+ MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
+ MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
+
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+ MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+ MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+ MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
+ MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
+ MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
+ MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
+
+ MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
+ MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
+
+ MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
+
+ MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
+ SRC_TOP3, 0, 1),
+ MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
+ SRC_TOP3, 4, 1),
+ MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
+ mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
+ MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
+ SRC_TOP3, 12, 1),
+ MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
+ SRC_TOP3, 16, 1),
+ MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
+ SRC_TOP3, 20, 1),
+ MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
+ SRC_TOP3, 24, 1),
+ MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
+ SRC_TOP3, 28, 1),
+
+ MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
+ SRC_TOP4, 0, 1),
+ MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
+ SRC_TOP4, 4, 1),
+ MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
+ SRC_TOP4, 8, 1),
+ MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
+ SRC_TOP4, 12, 1),
+ MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
+ SRC_TOP4, 16, 1),
+ MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
+ MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
+ MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+ SRC_TOP4, 28, 1),
+
+ MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
+ mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
+ MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
+ SRC_TOP5, 4, 1),
+ MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
+ SRC_TOP5, 8, 1),
+ MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
+ SRC_TOP5, 12, 1),
+ MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
+ SRC_TOP5, 16, 1),
+ MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
+ SRC_TOP5, 20, 1),
+ MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
+ mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
+ MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
+ mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
+
+ MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
+ MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
+ MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+ MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
+ MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
+ MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
+ MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+ MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
+
+ MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
+ SRC_TOP10, 0, 1),
+ MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
+ SRC_TOP10, 4, 1),
+ MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
+ SRC_TOP10, 8, 1),
+ MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
+ SRC_TOP10, 12, 1),
+ MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
+ SRC_TOP10, 16, 1),
+ MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
+ SRC_TOP10, 20, 1),
+ MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
+ SRC_TOP10, 24, 1),
+ MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
+ SRC_TOP10, 28, 1),
+
+ MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
+ SRC_TOP11, 0, 1),
+ MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
+ SRC_TOP11, 4, 1),
+ MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
+ MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
+ SRC_TOP11, 12, 1),
+ MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
+ MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
+ MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+ SRC_TOP11, 28, 1),
+
+ MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
+ mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
+ MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
+ SRC_TOP12, 8, 1),
+ MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
+ SRC_TOP12, 12, 1),
+ MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
+ MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
+ SRC_TOP12, 20, 1),
+ MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
+ mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
+ MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
+ mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
+
+ /* DISP1 Block */
+ MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
+ MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
+ MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
+ MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
+ MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
+
+ MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
+
+ /* CDREX block */
+ MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
+ SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
+ CLK_SET_RATE_PARENT, 0),
+
+ /* MAU Block */
+ MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
+
+ /* FSYS Block */
+ MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
+ MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
+ MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
+ MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
+ MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
+ MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
+ MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
+
+ /* PERIC Block */
+ MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+ MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+ MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+ MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+ MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+ MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
+ MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
+ MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
+ MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
+ MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
+ MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
+ MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
+
+ /* ISP Block */
+ MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
+ MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
+ MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
+ MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
+ MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
+};
+
+static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
+ DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+ DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
+ DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+ DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
+
+ DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
+ DIV_TOP0, 0, 3),
+ DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
+ DIV_TOP0, 4, 3),
+ DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
+ DIV_TOP0, 8, 3),
+ DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
+ DIV_TOP0, 12, 3),
+ DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
+ DIV_TOP0, 20, 3),
+ DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
+ DIV_TOP0, 24, 3),
+ DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
+ DIV_TOP0, 28, 3),
+ DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
+ "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
+ DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
+ "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
+ DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
+ DIV_TOP1, 8, 6),
+ DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
+ "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
+ DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
+ DIV_TOP1, 20, 3),
+ DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
+ DIV_TOP1, 24, 3),
+ DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
+ DIV_TOP1, 28, 3),
+
+ DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
+ DIV_TOP2, 8, 3),
+ DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
+ DIV_TOP2, 12, 3),
+ DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
+ 16, 3),
+ DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
+ DIV_TOP2, 20, 3),
+ DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
+ "mout_aclk300_disp1", DIV_TOP2, 24, 3),
+ DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
+ DIV_TOP2, 28, 3),
+
+ /* DISP1 Block */
+ DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
+ DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
+ DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
+ DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
+ DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
+ DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
+ "mout_aclk400_disp1", DIV_TOP2, 4, 3),
+
+ /* CDREX Block */
+ DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
+ DIV_CDREX0, 28, 3),
+ DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
+ DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
+ DIV_CDREX0, 16, 3),
+ DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
+ DIV_CDREX0, 8, 3),
+ DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
+ DIV_CDREX0, 3, 5),
+
+ DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
+ DIV_CDREX1, 8, 3),
+
+ /* Audio Block */
+ DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
+ DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
+
+ /* USB3.0 */
+ DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+ DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+ DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+ DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+
+ /* MMC */
+ DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
+ DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
+ DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
+
+ DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
+ DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
+
+ /* UART and PWM */
+ DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
+ DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
+ DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
+ DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
+ DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
+
+ /* SPI */
+ DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
+ DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
+ DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
+
+ /* Mfc Block */
+ DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
+
+ /* PCM */
+ DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
+ DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
+
+ /* Audio - I2S */
+ DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
+ DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
+ DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
+ DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
+ DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
+
+ /* SPI Pre-Ratio */
+ DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
+ DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
+ DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
+
+ /* GSCL Block */
+ DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
+ DIV2_RATIO0, 4, 2),
+ DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
+
+ /* MSCL Block */
+ DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
+
+ /* PSGEN */
+ DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
+ DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
+
+ /* ISP Block */
+ DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
+ DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
+ DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
+ DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
+ DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
+ DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
+ DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
+ DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
+ /* G2D */
+ GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
+ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
+ GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
+ GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
+ GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
+
+ GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
+ GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
+ GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
+
+ GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
+ GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
+ GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
+ GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
+ GATE_BUS_TOP, 5, 0, 0),
+ GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
+ GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
+ GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
+ GATE_BUS_TOP, 8, 0, 0),
+ GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
+ GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
+ GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
+ GATE_BUS_TOP, 13, 0, 0),
+ GATE(0, "aclk166", "mout_user_aclk166",
+ GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
+ GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
+ GATE_BUS_TOP, 16, 0, 0),
+ GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
+ GATE_BUS_TOP, 17, 0, 0),
+ GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
+ GATE_BUS_TOP, 18, 0, 0),
+ GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
+ GATE_BUS_TOP, 28, 0, 0),
+ GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
+ GATE_BUS_TOP, 29, 0, 0),
+
+ GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
+ SRC_MASK_TOP2, 24, 0, 0),
+
+ GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
+ SRC_MASK_TOP7, 20, 0, 0),
+
+ /* sclk */
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
+ GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
+ GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
+ GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
+ GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
+ GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
+ GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
+ GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
+ GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
+ GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
+ GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
+ GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
+ GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
+ GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
+ GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
+ GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
+ GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
+ GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
+ GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
+ GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
+ GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
+
+ /* Display */
+ GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
+ GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
+ GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
+ GATE_TOP_SCLK_DISP1, 9, 0, 0),
+ GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
+ GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
+ GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
+
+ /* Maudio Block */
+ GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
+ GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
+ GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
+
+ /* FSYS Block */
+ GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+ GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
+ GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
+ GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
+ GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
+ GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
+ GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
+ GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+ GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+ GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+ GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+
+ /* PERIC Block */
+ GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 0, 0, 0),
+ GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 1, 0, 0),
+ GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 2, 0, 0),
+ GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 3, 0, 0),
+ GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 6, 0, 0),
+ GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 7, 0, 0),
+ GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 8, 0, 0),
+ GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 9, 0, 0),
+ GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 10, 0, 0),
+ GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 11, 0, 0),
+ GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 12, 0, 0),
+ GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 13, 0, 0),
+ GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 14, 0, 0),
+ GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 15, 0, 0),
+ GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 16, 0, 0),
+ GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 17, 0, 0),
+ GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 18, 0, 0),
+ GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 20, 0, 0),
+ GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 21, 0, 0),
+ GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 22, 0, 0),
+ GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 23, 0, 0),
+ GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 24, 0, 0),
+ GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 26, 0, 0),
+ GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 28, 0, 0),
+ GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 30, 0, 0),
+ GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
+ GATE_IP_PERIC, 31, 0, 0),
+
+ GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
+ GATE_BUS_PERIC, 22, 0, 0),
+
+ /* PERIS Block */
+ GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
+ GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
+ GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
+ GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
+ GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
+ GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
+ GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
+ GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
+ GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
+ GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
+ GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
+ GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
+ GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
+ GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
+ GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
+ GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
+ GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
+ GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
+
+ GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
+
+ /* GEN Block */
+ GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
+ GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
+ GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
+ GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
+ GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
+ GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
+ GATE_IP_GEN, 6, 0, 0),
+ GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
+ GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
+ GATE_IP_GEN, 9, 0, 0),
+
+ /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
+ GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
+ GATE_BUS_GEN, 28, 0, 0),
+ GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
+
+ /* GSCL Block */
+ GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
+ GATE_TOP_SCLK_GSCL, 6, 0, 0),
+ GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
+ GATE_TOP_SCLK_GSCL, 7, 0, 0),
+
+ GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
+ GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
+ GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
+ GATE_IP_GSCL0, 4, 0, 0),
+ GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
+ GATE_IP_GSCL0, 5, 0, 0),
+ GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
+ GATE_IP_GSCL0, 6, 0, 0),
+
+ GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
+ GATE_IP_GSCL1, 2, 0, 0),
+ GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
+ GATE_IP_GSCL1, 3, 0, 0),
+ GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
+ GATE_IP_GSCL1, 4, 0, 0),
+ GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
+ GATE_IP_GSCL1, 6, 0, 0),
+ GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
+ GATE_IP_GSCL1, 7, 0, 0),
+ GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
+ GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
+ GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
+ GATE_IP_GSCL1, 16, 0, 0),
+ GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
+ GATE_IP_GSCL1, 17, 0, 0),
+
+ /* MSCL Block */
+ GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
+ GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
+ GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
+ GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
+ GATE_IP_MSCL, 8, 0, 0),
+ GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
+ GATE_IP_MSCL, 9, 0, 0),
+ GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
+ GATE_IP_MSCL, 10, 0, 0),
+
+ GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
+ GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
+ GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
+ GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
+ GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
+ GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
+ GATE_IP_DISP1, 7, 0, 0),
+ GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
+ GATE_IP_DISP1, 8, 0, 0),
+ GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
+ GATE_IP_DISP1, 9, 0, 0),
+
+ /* ISP */
+ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
+ GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
+ GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
+ GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
+ GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
+ GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
+ GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
+ GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
+ GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
+ GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
+
+ GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
+};
+
+static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
+ PLL_35XX_RATE(2000000000, 250, 3, 0),
+ PLL_35XX_RATE(1900000000, 475, 6, 0),
+ PLL_35XX_RATE(1800000000, 225, 3, 0),
+ PLL_35XX_RATE(1700000000, 425, 6, 0),
+ PLL_35XX_RATE(1600000000, 200, 3, 0),
+ PLL_35XX_RATE(1500000000, 250, 4, 0),
+ PLL_35XX_RATE(1400000000, 175, 3, 0),
+ PLL_35XX_RATE(1300000000, 325, 6, 0),
+ PLL_35XX_RATE(1200000000, 200, 2, 1),
+ PLL_35XX_RATE(1100000000, 275, 3, 1),
+ PLL_35XX_RATE(1000000000, 250, 3, 1),
+ PLL_35XX_RATE(900000000, 150, 2, 1),
+ PLL_35XX_RATE(800000000, 200, 3, 1),
+ PLL_35XX_RATE(700000000, 175, 3, 1),
+ PLL_35XX_RATE(600000000, 200, 2, 2),
+ PLL_35XX_RATE(500000000, 250, 3, 2),
+ PLL_35XX_RATE(400000000, 200, 3, 2),
+ PLL_35XX_RATE(300000000, 200, 2, 3),
+ PLL_35XX_RATE(200000000, 200, 3, 3),
+};
+
+static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
+ DPLL_CON0, NULL),
+ [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
+ EPLL_CON0, NULL),
+ [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
+ RPLL_CON0, NULL),
+ [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
+ IPLL_CON0, NULL),
+ [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
+ SPLL_CON0, NULL),
+ [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
+ VPLL_CON0, NULL),
+ [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
+};
+
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+ ((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+ { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk) \
+ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+ { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
+ { 1300000, E5420_KFC_DIV(3, 5, 2), },
+ { 1200000, E5420_KFC_DIV(3, 5, 2), },
+ { 1100000, E5420_KFC_DIV(3, 5, 2), },
+ { 1000000, E5420_KFC_DIV(3, 5, 2), },
+ { 900000, E5420_KFC_DIV(3, 5, 2), },
+ { 800000, E5420_KFC_DIV(3, 5, 2), },
+ { 700000, E5420_KFC_DIV(3, 4, 2), },
+ { 600000, E5420_KFC_DIV(3, 4, 2), },
+ { 500000, E5420_KFC_DIV(3, 4, 2), },
+ { 400000, E5420_KFC_DIV(3, 3, 2), },
+ { 300000, E5420_KFC_DIV(3, 3, 2), },
+ { 200000, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
+static const struct of_device_id ext_clk_match[] __initconst = {
+ { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
+ { },
+};
+
+/* register exynos5420 clocks */
+static void __init exynos5x_clk_init(struct device_node *np,
+ enum exynos5x_soc soc)
+{
+ struct samsung_clk_provider *ctx;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ exynos5x_soc = soc;
+
+ ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
+ ext_clk_match);
+
+ if (_get_rate("fin_pll") == 24 * MHZ) {
+ exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ }
+
+ samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
+ reg_base);
+ samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
+ ARRAY_SIZE(exynos5x_fixed_rate_clks));
+ samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
+ ARRAY_SIZE(exynos5x_fixed_factor_clks));
+ samsung_clk_register_mux(ctx, exynos5x_mux_clks,
+ ARRAY_SIZE(exynos5x_mux_clks));
+ samsung_clk_register_div(ctx, exynos5x_div_clks,
+ ARRAY_SIZE(exynos5x_div_clks));
+ samsung_clk_register_gate(ctx, exynos5x_gate_clks,
+ ARRAY_SIZE(exynos5x_gate_clks));
+
+ if (soc == EXYNOS5420) {
+ samsung_clk_register_mux(ctx, exynos5420_mux_clks,
+ ARRAY_SIZE(exynos5420_mux_clks));
+ samsung_clk_register_div(ctx, exynos5420_div_clks,
+ ARRAY_SIZE(exynos5420_div_clks));
+ } else {
+ samsung_clk_register_fixed_factor(
+ ctx, exynos5800_fixed_factor_clks,
+ ARRAY_SIZE(exynos5800_fixed_factor_clks));
+ samsung_clk_register_mux(ctx, exynos5800_mux_clks,
+ ARRAY_SIZE(exynos5800_mux_clks));
+ samsung_clk_register_div(ctx, exynos5800_div_clks,
+ ARRAY_SIZE(exynos5800_div_clks));
+ samsung_clk_register_gate(ctx, exynos5800_gate_clks,
+ ARRAY_SIZE(exynos5800_gate_clks));
+ }
+
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+ }
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
+ exynos5420_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+}
+
+static void __init exynos5420_clk_init(struct device_node *np)
+{
+ exynos5x_clk_init(np, EXYNOS5420);
+}
+CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
+
+static void __init exynos5800_clk_init(struct device_node *np)
+{
+ exynos5x_clk_init(np, EXYNOS5800);
+}
+CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5443 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/exynos5433.h>
+
+#include "clk.h"
+#include "clk-cpu.h"
+#include "clk-pll.h"
+
+/*
+ * Register offset definitions for CMU_TOP
+ */
+#define ISP_PLL_LOCK 0x0000
+#define AUD_PLL_LOCK 0x0004
+#define ISP_PLL_CON0 0x0100
+#define ISP_PLL_CON1 0x0104
+#define ISP_PLL_FREQ_DET 0x0108
+#define AUD_PLL_CON0 0x0110
+#define AUD_PLL_CON1 0x0114
+#define AUD_PLL_CON2 0x0118
+#define AUD_PLL_FREQ_DET 0x011c
+#define MUX_SEL_TOP0 0x0200
+#define MUX_SEL_TOP1 0x0204
+#define MUX_SEL_TOP2 0x0208
+#define MUX_SEL_TOP3 0x020c
+#define MUX_SEL_TOP4 0x0210
+#define MUX_SEL_TOP_MSCL 0x0220
+#define MUX_SEL_TOP_CAM1 0x0224
+#define MUX_SEL_TOP_DISP 0x0228
+#define MUX_SEL_TOP_FSYS0 0x0230
+#define MUX_SEL_TOP_FSYS1 0x0234
+#define MUX_SEL_TOP_PERIC0 0x0238
+#define MUX_SEL_TOP_PERIC1 0x023c
+#define MUX_ENABLE_TOP0 0x0300
+#define MUX_ENABLE_TOP1 0x0304
+#define MUX_ENABLE_TOP2 0x0308
+#define MUX_ENABLE_TOP3 0x030c
+#define MUX_ENABLE_TOP4 0x0310
+#define MUX_ENABLE_TOP_MSCL 0x0320
+#define MUX_ENABLE_TOP_CAM1 0x0324
+#define MUX_ENABLE_TOP_DISP 0x0328
+#define MUX_ENABLE_TOP_FSYS0 0x0330
+#define MUX_ENABLE_TOP_FSYS1 0x0334
+#define MUX_ENABLE_TOP_PERIC0 0x0338
+#define MUX_ENABLE_TOP_PERIC1 0x033c
+#define MUX_STAT_TOP0 0x0400
+#define MUX_STAT_TOP1 0x0404
+#define MUX_STAT_TOP2 0x0408
+#define MUX_STAT_TOP3 0x040c
+#define MUX_STAT_TOP4 0x0410
+#define MUX_STAT_TOP_MSCL 0x0420
+#define MUX_STAT_TOP_CAM1 0x0424
+#define MUX_STAT_TOP_FSYS0 0x0430
+#define MUX_STAT_TOP_FSYS1 0x0434
+#define MUX_STAT_TOP_PERIC0 0x0438
+#define MUX_STAT_TOP_PERIC1 0x043c
+#define DIV_TOP0 0x0600
+#define DIV_TOP1 0x0604
+#define DIV_TOP2 0x0608
+#define DIV_TOP3 0x060c
+#define DIV_TOP4 0x0610
+#define DIV_TOP_MSCL 0x0618
+#define DIV_TOP_CAM10 0x061c
+#define DIV_TOP_CAM11 0x0620
+#define DIV_TOP_FSYS0 0x062c
+#define DIV_TOP_FSYS1 0x0630
+#define DIV_TOP_FSYS2 0x0634
+#define DIV_TOP_PERIC0 0x0638
+#define DIV_TOP_PERIC1 0x063c
+#define DIV_TOP_PERIC2 0x0640
+#define DIV_TOP_PERIC3 0x0644
+#define DIV_TOP_PERIC4 0x0648
+#define DIV_TOP_PLL_FREQ_DET 0x064c
+#define DIV_STAT_TOP0 0x0700
+#define DIV_STAT_TOP1 0x0704
+#define DIV_STAT_TOP2 0x0708
+#define DIV_STAT_TOP3 0x070c
+#define DIV_STAT_TOP4 0x0710
+#define DIV_STAT_TOP_MSCL 0x0718
+#define DIV_STAT_TOP_CAM10 0x071c
+#define DIV_STAT_TOP_CAM11 0x0720
+#define DIV_STAT_TOP_FSYS0 0x072c
+#define DIV_STAT_TOP_FSYS1 0x0730
+#define DIV_STAT_TOP_FSYS2 0x0734
+#define DIV_STAT_TOP_PERIC0 0x0738
+#define DIV_STAT_TOP_PERIC1 0x073c
+#define DIV_STAT_TOP_PERIC2 0x0740
+#define DIV_STAT_TOP_PERIC3 0x0744
+#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
+#define ENABLE_ACLK_TOP 0x0800
+#define ENABLE_SCLK_TOP 0x0a00
+#define ENABLE_SCLK_TOP_MSCL 0x0a04
+#define ENABLE_SCLK_TOP_CAM1 0x0a08
+#define ENABLE_SCLK_TOP_DISP 0x0a0c
+#define ENABLE_SCLK_TOP_FSYS 0x0a10
+#define ENABLE_SCLK_TOP_PERIC 0x0a14
+#define ENABLE_IP_TOP 0x0b00
+#define ENABLE_CMU_TOP 0x0c00
+#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
+
+static const unsigned long top_clk_regs[] __initconst = {
+ ISP_PLL_LOCK,
+ AUD_PLL_LOCK,
+ ISP_PLL_CON0,
+ ISP_PLL_CON1,
+ ISP_PLL_FREQ_DET,
+ AUD_PLL_CON0,
+ AUD_PLL_CON1,
+ AUD_PLL_CON2,
+ AUD_PLL_FREQ_DET,
+ MUX_SEL_TOP0,
+ MUX_SEL_TOP1,
+ MUX_SEL_TOP2,
+ MUX_SEL_TOP3,
+ MUX_SEL_TOP4,
+ MUX_SEL_TOP_MSCL,
+ MUX_SEL_TOP_CAM1,
+ MUX_SEL_TOP_DISP,
+ MUX_SEL_TOP_FSYS0,
+ MUX_SEL_TOP_FSYS1,
+ MUX_SEL_TOP_PERIC0,
+ MUX_SEL_TOP_PERIC1,
+ MUX_ENABLE_TOP0,
+ MUX_ENABLE_TOP1,
+ MUX_ENABLE_TOP2,
+ MUX_ENABLE_TOP3,
+ MUX_ENABLE_TOP4,
+ MUX_ENABLE_TOP_MSCL,
+ MUX_ENABLE_TOP_CAM1,
+ MUX_ENABLE_TOP_DISP,
+ MUX_ENABLE_TOP_FSYS0,
+ MUX_ENABLE_TOP_FSYS1,
+ MUX_ENABLE_TOP_PERIC0,
+ MUX_ENABLE_TOP_PERIC1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_TOP2,
+ DIV_TOP3,
+ DIV_TOP4,
+ DIV_TOP_MSCL,
+ DIV_TOP_CAM10,
+ DIV_TOP_CAM11,
+ DIV_TOP_FSYS0,
+ DIV_TOP_FSYS1,
+ DIV_TOP_FSYS2,
+ DIV_TOP_PERIC0,
+ DIV_TOP_PERIC1,
+ DIV_TOP_PERIC2,
+ DIV_TOP_PERIC3,
+ DIV_TOP_PERIC4,
+ DIV_TOP_PLL_FREQ_DET,
+ ENABLE_ACLK_TOP,
+ ENABLE_SCLK_TOP,
+ ENABLE_SCLK_TOP_MSCL,
+ ENABLE_SCLK_TOP_CAM1,
+ ENABLE_SCLK_TOP_DISP,
+ ENABLE_SCLK_TOP_FSYS,
+ ENABLE_SCLK_TOP_PERIC,
+ ENABLE_IP_TOP,
+ ENABLE_CMU_TOP,
+ ENABLE_CMU_TOP_DIV_STAT,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
+PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
+PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
+PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
+PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
+PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
+PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
+PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
+
+PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
+PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
+PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
+ "mout_mfc_pll_user", };
+PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
+
+PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
+ "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
+
+PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
+ "mout_mphy_pll_user", };
+
+PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
+PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
+
+PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
+PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
+PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
+PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
+PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
+
+PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
+ "oscclk", "ioclk_spdif_extclk", };
+PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
+ "mout_aud_pll_user_t",};
+PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
+ "mout_aud_pll_user_t",};
+
+PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
+
+static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
+};
+
+static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
+ FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
+ /* XspiCLK[4:0] input clock for SPI */
+ FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
+ FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
+ FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
+ FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
+ FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
+ /* Xi2s1SCLK input clock for I2S1_BCLK */
+ FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
+};
+
+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
+ /* MUX_SEL_TOP0 */
+ MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
+ 4, 1),
+ MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
+ 0, 1),
+
+ /* MUX_SEL_TOP1 */
+ MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
+ mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
+ MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
+ MUX_SEL_TOP1, 8, 1),
+ MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
+ MUX_SEL_TOP1, 4, 1),
+ MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
+ MUX_SEL_TOP1, 0, 1),
+
+ /* MUX_SEL_TOP2 */
+ MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
+ mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
+ mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
+ mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
+ MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
+ MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
+
+ /* MUX_SEL_TOP3 */
+ MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
+ mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
+ MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
+ mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
+ MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
+ mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
+ MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
+ mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
+ MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
+ mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
+ /* MUX_SEL_TOP_MSCL */
+ MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
+ MUX_SEL_TOP_MSCL, 8, 1),
+ MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
+ MUX_SEL_TOP_MSCL, 4, 1),
+ MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_MSCL, 0, 1),
+
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
+
+ /* MUX_SEL_TOP_FSYS0 */
+ MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
+ MUX_SEL_TOP_FSYS0, 28, 1),
+ MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS0, 24, 1),
+ MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
+ MUX_SEL_TOP_FSYS0, 20, 1),
+ MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS0, 16, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
+ MUX_SEL_TOP_FSYS0, 12, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
+ MUX_SEL_TOP_FSYS0, 8, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
+ MUX_SEL_TOP_FSYS0, 4, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS0, 0, 1),
+
+ /* MUX_SEL_TOP_FSYS1 */
+ MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_FSYS1, 12, 1),
+ MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
+ mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
+ MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
+ MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
+
+ /* MUX_SEL_TOP_PERIC0 */
+ MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 28, 1),
+ MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 24, 1),
+ MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 20, 1),
+ MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 16, 1),
+ MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 12, 1),
+ MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 8, 1),
+ MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 4, 1),
+ MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
+ MUX_SEL_TOP_PERIC0, 0, 1),
+
+ /* MUX_SEL_TOP_PERIC1 */
+ MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
+ MUX_SEL_TOP_PERIC1, 16, 1),
+ MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
+ MUX_SEL_TOP_PERIC1, 12, 2),
+ MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
+ MUX_SEL_TOP_PERIC1, 4, 2),
+ MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
+ MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
+};
+
+static const struct samsung_div_clock top_div_clks[] __initconst = {
+ /* DIV_TOP0 */
+ DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
+ DIV_TOP0, 28, 3),
+ DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
+ DIV_TOP0, 24, 3),
+ DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
+ DIV_TOP0, 20, 3),
+ DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
+ DIV_TOP0, 16, 3),
+ DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
+ DIV_TOP0, 12, 3),
+ DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
+ DIV_TOP0, 8, 3),
+ DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
+ "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
+ DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
+ "mout_aclk_isp_400", DIV_TOP0, 0, 4),
+
+ /* DIV_TOP1 */
+ DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
+ DIV_TOP1, 28, 3),
+ DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
+ DIV_TOP1, 24, 3),
+ DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
+ DIV_TOP1, 20, 3),
+ DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
+ DIV_TOP1, 12, 3),
+ DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
+ DIV_TOP1, 8, 3),
+ DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
+ DIV_TOP1, 0, 3),
+
+ /* DIV_TOP2 */
+ DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
+ DIV_TOP2, 4, 3),
+ DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
+ DIV_TOP2, 0, 3),
+
+ /* DIV_TOP3 */
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
+ "mout_bus_pll_user", DIV_TOP3, 24, 3),
+ DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
+ "mout_bus_pll_user", DIV_TOP3, 20, 3),
+ DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
+ "mout_bus_pll_user", DIV_TOP3, 16, 3),
+ DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
+ "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
+ DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
+ "mout_bus_pll_user", DIV_TOP3, 8, 3),
+ DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
+ "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
+ DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
+ "mout_bus_pll_user", DIV_TOP3, 0, 3),
+
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
+ DIV_TOP4, 0, 3),
+
+ /* DIV_TOP_MSCL */
+ DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
+ DIV_TOP_MSCL, 0, 4),
+
+ /* DIV_TOP_CAM10 */
+ DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
+ DIV_TOP_CAM10, 24, 5),
+ DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
+ "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
+ DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
+ "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
+ DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
+ "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
+ DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
+ "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
+
+ /* DIV_TOP_CAM11 */
+ DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
+ "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
+ DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
+ "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
+ DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
+ "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
+ DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
+ "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
+ DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
+ "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
+ DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
+ "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
+
+ /* DIV_TOP_FSYS0 */
+ DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
+ DIV_TOP_FSYS0, 16, 8),
+ DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
+ DIV_TOP_FSYS0, 12, 4),
+ DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
+ DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
+ DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
+
+ /* DIV_TOP_FSYS1 */
+ DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
+ DIV_TOP_FSYS1, 4, 8),
+ DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
+ DIV_TOP_FSYS1, 0, 4),
+
+ /* DIV_TOP_FSYS2 */
+ DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
+ DIV_TOP_FSYS2, 12, 3),
+ DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
+ "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
+ DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
+ "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
+ DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
+ DIV_TOP_FSYS2, 0, 4),
+
+ /* DIV_TOP_PERIC0 */
+ DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
+ DIV_TOP_PERIC0, 16, 8),
+ DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
+ DIV_TOP_PERIC0, 12, 4),
+ DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
+ DIV_TOP_PERIC0, 4, 8),
+ DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
+ DIV_TOP_PERIC0, 0, 4),
+
+ /* DIV_TOP_PERIC1 */
+ DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
+ DIV_TOP_PERIC1, 4, 8),
+ DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
+ DIV_TOP_PERIC1, 0, 4),
+
+ /* DIV_TOP_PERIC2 */
+ DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
+ DIV_TOP_PERIC2, 8, 4),
+ DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
+ DIV_TOP_PERIC2, 4, 4),
+ DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
+ DIV_TOP_PERIC2, 0, 4),
+
+ /* DIV_TOP_PERIC3 */
+ DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
+ DIV_TOP_PERIC3, 16, 6),
+ DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
+ DIV_TOP_PERIC3, 8, 8),
+ DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
+ DIV_TOP_PERIC3, 4, 4),
+ DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
+ DIV_TOP_PERIC3, 0, 4),
+
+ /* DIV_TOP_PERIC4 */
+ DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
+ DIV_TOP_PERIC4, 16, 8),
+ DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
+ DIV_TOP_PERIC4, 12, 4),
+ DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
+ DIV_TOP_PERIC4, 4, 8),
+ DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
+ DIV_TOP_PERIC4, 0, 4),
+};
+
+static const struct samsung_gate_clock top_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
+ ENABLE_ACLK_TOP, 30, 0, 0),
+ GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
+ "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
+ 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
+ ENABLE_ACLK_TOP, 26,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
+ ENABLE_ACLK_TOP, 25,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
+ ENABLE_ACLK_TOP, 24,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
+ ENABLE_ACLK_TOP, 23,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
+ ENABLE_ACLK_TOP, 22,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
+ ENABLE_ACLK_TOP, 21,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
+ ENABLE_ACLK_TOP, 19,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
+ ENABLE_ACLK_TOP, 18,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
+ ENABLE_ACLK_TOP, 15,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
+ ENABLE_ACLK_TOP, 14,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
+ ENABLE_ACLK_TOP, 13,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
+ ENABLE_ACLK_TOP, 12,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
+ ENABLE_ACLK_TOP, 11,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
+ ENABLE_ACLK_TOP, 10,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
+ ENABLE_ACLK_TOP, 9,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
+ ENABLE_ACLK_TOP, 8,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
+ ENABLE_ACLK_TOP, 7,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
+ ENABLE_ACLK_TOP, 6,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
+ ENABLE_ACLK_TOP, 5,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
+ ENABLE_ACLK_TOP, 3,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
+ ENABLE_ACLK_TOP, 2,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
+ ENABLE_ACLK_TOP, 0,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_TOP_MSCL */
+ GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
+ ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
+
+ /* ENABLE_SCLK_TOP_CAM1 */
+ GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
+ ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
+ GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
+ ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
+ GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
+ ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
+ GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
+ ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
+ GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
+ ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
+ GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
+ ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
+ GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
+ ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
+
+ /* ENABLE_SCLK_TOP_DISP */
+ GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
+ "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
+ ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
+ ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
+ ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
+ ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
+ "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
+ 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
+ "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
+ 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
+ "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
+ 0, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_SCLK_TOP_PERIC */
+ GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
+ ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
+ ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
+ ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
+ ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
+ ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
+ ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
+ ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
+ ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
+ ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
+ ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
+ ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* MUX_ENABLE_TOP_PERIC1 */
+ GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
+ MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
+ GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
+ MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
+ GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
+ MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
+};
+
+/*
+ * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
+ * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
+ */
+static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = {
+ PLL_35XX_RATE(2500000000U, 625, 6, 0),
+ PLL_35XX_RATE(2400000000U, 500, 5, 0),
+ PLL_35XX_RATE(2300000000U, 575, 6, 0),
+ PLL_35XX_RATE(2200000000U, 550, 6, 0),
+ PLL_35XX_RATE(2100000000U, 350, 4, 0),
+ PLL_35XX_RATE(2000000000U, 500, 6, 0),
+ PLL_35XX_RATE(1900000000U, 475, 6, 0),
+ PLL_35XX_RATE(1800000000U, 375, 5, 0),
+ PLL_35XX_RATE(1700000000U, 425, 6, 0),
+ PLL_35XX_RATE(1600000000U, 400, 6, 0),
+ PLL_35XX_RATE(1500000000U, 250, 4, 0),
+ PLL_35XX_RATE(1400000000U, 350, 6, 0),
+ PLL_35XX_RATE(1332000000U, 222, 4, 0),
+ PLL_35XX_RATE(1300000000U, 325, 6, 0),
+ PLL_35XX_RATE(1200000000U, 500, 5, 1),
+ PLL_35XX_RATE(1100000000U, 550, 6, 1),
+ PLL_35XX_RATE(1086000000U, 362, 4, 1),
+ PLL_35XX_RATE(1066000000U, 533, 6, 1),
+ PLL_35XX_RATE(1000000000U, 500, 6, 1),
+ PLL_35XX_RATE(933000000U, 311, 4, 1),
+ PLL_35XX_RATE(921000000U, 307, 4, 1),
+ PLL_35XX_RATE(900000000U, 375, 5, 1),
+ PLL_35XX_RATE(825000000U, 275, 4, 1),
+ PLL_35XX_RATE(800000000U, 400, 6, 1),
+ PLL_35XX_RATE(733000000U, 733, 12, 1),
+ PLL_35XX_RATE(700000000U, 175, 3, 1),
+ PLL_35XX_RATE(667000000U, 222, 4, 1),
+ PLL_35XX_RATE(633000000U, 211, 4, 1),
+ PLL_35XX_RATE(600000000U, 500, 5, 2),
+ PLL_35XX_RATE(552000000U, 460, 5, 2),
+ PLL_35XX_RATE(550000000U, 550, 6, 2),
+ PLL_35XX_RATE(543000000U, 362, 4, 2),
+ PLL_35XX_RATE(533000000U, 533, 6, 2),
+ PLL_35XX_RATE(500000000U, 500, 6, 2),
+ PLL_35XX_RATE(444000000U, 370, 5, 2),
+ PLL_35XX_RATE(420000000U, 350, 5, 2),
+ PLL_35XX_RATE(400000000U, 400, 6, 2),
+ PLL_35XX_RATE(350000000U, 350, 6, 2),
+ PLL_35XX_RATE(333000000U, 222, 4, 2),
+ PLL_35XX_RATE(300000000U, 500, 5, 3),
+ PLL_35XX_RATE(266000000U, 532, 6, 3),
+ PLL_35XX_RATE(200000000U, 400, 6, 3),
+ PLL_35XX_RATE(166000000U, 332, 6, 3),
+ PLL_35XX_RATE(160000000U, 320, 6, 3),
+ PLL_35XX_RATE(133000000U, 532, 6, 4),
+ PLL_35XX_RATE(100000000U, 400, 6, 4),
+ { /* sentinel */ }
+};
+
+/* AUD_PLL */
+static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = {
+ PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
+ PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
+ PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
+ PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
+ PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
+ PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
+ PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
+ PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
+ PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
+ { /* sentinel */ }
+};
+
+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
+ ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
+ AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+ .pll_clks = top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
+ .mux_clks = top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
+ .div_clks = top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .gate_clks = top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
+ .fixed_clks = top_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+ .fixed_factor_clks = top_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
+ .nr_clk_ids = TOP_NR_CLK,
+ .clk_regs = top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos5433_cmu_top_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &top_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
+ exynos5433_cmu_top_init);
+
+/*
+ * Register offset definitions for CMU_CPIF
+ */
+#define MPHY_PLL_LOCK 0x0000
+#define MPHY_PLL_CON0 0x0100
+#define MPHY_PLL_CON1 0x0104
+#define MPHY_PLL_FREQ_DET 0x010c
+#define MUX_SEL_CPIF0 0x0200
+#define DIV_CPIF 0x0600
+#define ENABLE_SCLK_CPIF 0x0a00
+
+static const unsigned long cpif_clk_regs[] __initconst = {
+ MPHY_PLL_LOCK,
+ MPHY_PLL_CON0,
+ MPHY_PLL_CON1,
+ MPHY_PLL_FREQ_DET,
+ MUX_SEL_CPIF0,
+ DIV_CPIF,
+ ENABLE_SCLK_CPIF,
+};
+
+/* list of all parent clock list */
+PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
+
+static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
+ MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
+};
+
+static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
+ /* MUX_SEL_CPIF0 */
+ MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
+ 0, 1),
+};
+
+static const struct samsung_div_clock cpif_div_clks[] __initconst = {
+ /* DIV_CPIF */
+ DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
+ 0, 6),
+};
+
+static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
+ /* ENABLE_SCLK_CPIF */
+ GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
+ ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
+ ENABLE_SCLK_CPIF, 4, 0, 0),
+};
+
+static const struct samsung_cmu_info cpif_cmu_info __initconst = {
+ .pll_clks = cpif_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
+ .mux_clks = cpif_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
+ .div_clks = cpif_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
+ .gate_clks = cpif_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
+ .nr_clk_ids = CPIF_NR_CLK,
+ .clk_regs = cpif_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
+};
+
+static void __init exynos5433_cmu_cpif_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cpif_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
+ exynos5433_cmu_cpif_init);
+
+/*
+ * Register offset definitions for CMU_MIF
+ */
+#define MEM0_PLL_LOCK 0x0000
+#define MEM1_PLL_LOCK 0x0004
+#define BUS_PLL_LOCK 0x0008
+#define MFC_PLL_LOCK 0x000c
+#define MEM0_PLL_CON0 0x0100
+#define MEM0_PLL_CON1 0x0104
+#define MEM0_PLL_FREQ_DET 0x010c
+#define MEM1_PLL_CON0 0x0110
+#define MEM1_PLL_CON1 0x0114
+#define MEM1_PLL_FREQ_DET 0x011c
+#define BUS_PLL_CON0 0x0120
+#define BUS_PLL_CON1 0x0124
+#define BUS_PLL_FREQ_DET 0x012c
+#define MFC_PLL_CON0 0x0130
+#define MFC_PLL_CON1 0x0134
+#define MFC_PLL_FREQ_DET 0x013c
+#define MUX_SEL_MIF0 0x0200
+#define MUX_SEL_MIF1 0x0204
+#define MUX_SEL_MIF2 0x0208
+#define MUX_SEL_MIF3 0x020c
+#define MUX_SEL_MIF4 0x0210
+#define MUX_SEL_MIF5 0x0214
+#define MUX_SEL_MIF6 0x0218
+#define MUX_SEL_MIF7 0x021c
+#define MUX_ENABLE_MIF0 0x0300
+#define MUX_ENABLE_MIF1 0x0304
+#define MUX_ENABLE_MIF2 0x0308
+#define MUX_ENABLE_MIF3 0x030c
+#define MUX_ENABLE_MIF4 0x0310
+#define MUX_ENABLE_MIF5 0x0314
+#define MUX_ENABLE_MIF6 0x0318
+#define MUX_ENABLE_MIF7 0x031c
+#define MUX_STAT_MIF0 0x0400
+#define MUX_STAT_MIF1 0x0404
+#define MUX_STAT_MIF2 0x0408
+#define MUX_STAT_MIF3 0x040c
+#define MUX_STAT_MIF4 0x0410
+#define MUX_STAT_MIF5 0x0414
+#define MUX_STAT_MIF6 0x0418
+#define MUX_STAT_MIF7 0x041c
+#define DIV_MIF1 0x0604
+#define DIV_MIF2 0x0608
+#define DIV_MIF3 0x060c
+#define DIV_MIF4 0x0610
+#define DIV_MIF5 0x0614
+#define DIV_MIF_PLL_FREQ_DET 0x0618
+#define DIV_STAT_MIF1 0x0704
+#define DIV_STAT_MIF2 0x0708
+#define DIV_STAT_MIF3 0x070c
+#define DIV_STAT_MIF4 0x0710
+#define DIV_STAT_MIF5 0x0714
+#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
+#define ENABLE_ACLK_MIF0 0x0800
+#define ENABLE_ACLK_MIF1 0x0804
+#define ENABLE_ACLK_MIF2 0x0808
+#define ENABLE_ACLK_MIF3 0x080c
+#define ENABLE_PCLK_MIF 0x0900
+#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
+#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
+#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
+#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
+#define ENABLE_SCLK_MIF 0x0a00
+#define ENABLE_IP_MIF0 0x0b00
+#define ENABLE_IP_MIF1 0x0b04
+#define ENABLE_IP_MIF2 0x0b08
+#define ENABLE_IP_MIF3 0x0b0c
+#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
+#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
+#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
+#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
+#define CLKOUT_CMU_MIF 0x0c00
+#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
+#define DREX_FREQ_CTRL0 0x1000
+#define DREX_FREQ_CTRL1 0x1004
+#define PAUSE 0x1008
+#define DDRPHY_LOCK_CTRL 0x100c
+
+static const unsigned long mif_clk_regs[] __initconst = {
+ MEM0_PLL_LOCK,
+ MEM1_PLL_LOCK,
+ BUS_PLL_LOCK,
+ MFC_PLL_LOCK,
+ MEM0_PLL_CON0,
+ MEM0_PLL_CON1,
+ MEM0_PLL_FREQ_DET,
+ MEM1_PLL_CON0,
+ MEM1_PLL_CON1,
+ MEM1_PLL_FREQ_DET,
+ BUS_PLL_CON0,
+ BUS_PLL_CON1,
+ BUS_PLL_FREQ_DET,
+ MFC_PLL_CON0,
+ MFC_PLL_CON1,
+ MFC_PLL_FREQ_DET,
+ MUX_SEL_MIF0,
+ MUX_SEL_MIF1,
+ MUX_SEL_MIF2,
+ MUX_SEL_MIF3,
+ MUX_SEL_MIF4,
+ MUX_SEL_MIF5,
+ MUX_SEL_MIF6,
+ MUX_SEL_MIF7,
+ MUX_ENABLE_MIF0,
+ MUX_ENABLE_MIF1,
+ MUX_ENABLE_MIF2,
+ MUX_ENABLE_MIF3,
+ MUX_ENABLE_MIF4,
+ MUX_ENABLE_MIF5,
+ MUX_ENABLE_MIF6,
+ MUX_ENABLE_MIF7,
+ DIV_MIF1,
+ DIV_MIF2,
+ DIV_MIF3,
+ DIV_MIF4,
+ DIV_MIF5,
+ DIV_MIF_PLL_FREQ_DET,
+ ENABLE_ACLK_MIF0,
+ ENABLE_ACLK_MIF1,
+ ENABLE_ACLK_MIF2,
+ ENABLE_ACLK_MIF3,
+ ENABLE_PCLK_MIF,
+ ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
+ ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
+ ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
+ ENABLE_PCLK_MIF_SECURE_RTC,
+ ENABLE_SCLK_MIF,
+ ENABLE_IP_MIF0,
+ ENABLE_IP_MIF1,
+ ENABLE_IP_MIF2,
+ ENABLE_IP_MIF3,
+ ENABLE_IP_MIF_SECURE_DREX0_TZ,
+ ENABLE_IP_MIF_SECURE_DREX1_TZ,
+ ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
+ ENABLE_IP_MIF_SECURE_RTC,
+ CLKOUT_CMU_MIF,
+ CLKOUT_CMU_MIF_DIV_STAT,
+ DREX_FREQ_CTRL0,
+ DREX_FREQ_CTRL1,
+ PAUSE,
+ DDRPHY_LOCK_CTRL,
+};
+
+static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
+ MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
+ MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
+ BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
+ PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
+ MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
+};
+
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
+PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
+PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
+PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
+PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
+PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
+PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
+PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
+
+PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
+PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
+PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
+PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
+
+PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
+PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
+
+PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
+ "mout_bus_pll_div2", };
+PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
+
+PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
+PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
+ "mout_mfc_pll_div2", };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
+PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
+
+PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
+ "sclk_mphy_pll", };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
+ "mout_mfc_pll_div2", };
+PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
+PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
+
+static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
+ /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+ FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
+ FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
+ FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
+ FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
+};
+
+static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
+ /* MUX_SEL_MIF0 */
+ MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
+ MUX_SEL_MIF0, 28, 1),
+ MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
+ MUX_SEL_MIF0, 24, 1),
+ MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
+ MUX_SEL_MIF0, 20, 1),
+ MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
+ MUX_SEL_MIF0, 16, 1),
+ MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
+ 12, 1),
+ MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
+ 8, 1),
+ MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
+ 4, 1),
+ MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
+ 0, 1),
+
+ /* MUX_SEL_MIF1 */
+ MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
+ MUX_SEL_MIF1, 24, 1),
+ MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
+ MUX_SEL_MIF1, 20, 1),
+ MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
+ MUX_SEL_MIF1, 16, 1),
+ MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
+ MUX_SEL_MIF1, 12, 1),
+ MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
+ MUX_SEL_MIF1, 8, 1),
+ MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
+ MUX_SEL_MIF1, 4, 1),
+
+ /* MUX_SEL_MIF2 */
+ MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
+ mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
+ MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
+ mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
+
+ /* MUX_SEL_MIF3 */
+ MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
+ mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
+ MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
+ mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
+
+ /* MUX_SEL_MIF4 */
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
+ mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
+ mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
+ mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
+ mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
+ mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
+ mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
+
+ /* MUX_SEL_MIF5 */
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
+ mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
+ mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
+ mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
+ MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
+ MUX_SEL_MIF5, 8, 1),
+ MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
+ MUX_SEL_MIF5, 4, 1),
+ MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
+ MUX_SEL_MIF5, 0, 1),
+
+ /* MUX_SEL_MIF6 */
+ MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
+ MUX_SEL_MIF6, 8, 1),
+ MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
+ MUX_SEL_MIF6, 4, 1),
+ MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
+ MUX_SEL_MIF6, 0, 1),
+
+ /* MUX_SEL_MIF7 */
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
+ mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
+ mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
+ mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
+ MUX_SEL_MIF7, 8, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
+ MUX_SEL_MIF7, 4, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
+ MUX_SEL_MIF7, 0, 1),
+};
+
+static const struct samsung_div_clock mif_div_clks[] __initconst = {
+ /* DIV_MIF1 */
+ DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
+ DIV_MIF1, 16, 2),
+ DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
+ 12, 2),
+ DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
+ 8, 2),
+ DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
+ 4, 4),
+
+ /* DIV_MIF2 */
+ DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
+ DIV_MIF2, 20, 3),
+ DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
+ DIV_MIF2, 16, 4),
+ DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
+ DIV_MIF2, 12, 4),
+ DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
+ "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
+ DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
+ DIV_MIF2, 4, 2),
+ DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
+ DIV_MIF2, 0, 3),
+
+ /* DIV_MIF3 */
+ DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
+ DIV_MIF3, 16, 4),
+ DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
+ DIV_MIF3, 4, 3),
+ DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
+ DIV_MIF3, 0, 3),
+
+ /* DIV_MIF4 */
+ DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
+ DIV_MIF4, 24, 4),
+ DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
+ "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
+ DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
+ DIV_MIF4, 16, 4),
+ DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
+ DIV_MIF4, 12, 4),
+ DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
+ "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
+ DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
+ "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
+ DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
+ "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
+
+ /* DIV_MIF5 */
+ DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
+ 0, 3),
+};
+
+static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_MIF0 */
+ GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
+ ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
+ ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_MIF1 */
+ GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF1,
+ 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
+ "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
+ 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
+ "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
+ 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
+ "div_aclk_drex1", ENABLE_ACLK_MIF1,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
+ "div_aclk_mif_133", ENABLE_ACLK_MIF1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
+ "div_aclk_drex0", ENABLE_ACLK_MIF1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
+ ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
+ ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
+ ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
+ ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
+ ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
+ ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_MIF2 */
+ GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
+ ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
+ ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
+ ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
+ ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
+ ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
+ ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
+ ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
+ "div_aclk_mif_400", ENABLE_ACLK_MIF2,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
+ ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
+ "div_aclk_mif_200", ENABLE_ACLK_MIF2,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
+ "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
+
+ /* ENABLE_ACLK_MIF3 */
+ GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
+ ENABLE_ACLK_MIF3, 4,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
+ ENABLE_ACLK_MIF3, 1,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
+ ENABLE_ACLK_MIF3, 0,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_PCLK_MIF */
+ GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
+ ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
+ ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
+ ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
+ ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
+ ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
+ ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 19, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 18, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
+ "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
+ GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 11, 0, 0),
+ GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 7, 0, 0),
+ GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 5, 0, 0),
+ GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 2, 0, 0),
+ GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
+ GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
+ GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
+ GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
+
+ /* ENABLE_PCLK_MIF_SECURE_RTC */
+ GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
+ ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
+
+ /* ENABLE_SCLK_MIF */
+ GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
+ "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
+ "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
+ "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
+ "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
+ ENABLE_SCLK_MIF, 4,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
+ ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
+ ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
+ ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
+ ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info mif_cmu_info __initconst = {
+ .pll_clks = mif_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
+ .mux_clks = mif_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
+ .div_clks = mif_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mif_div_clks),
+ .gate_clks = mif_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
+ .fixed_factor_clks = mif_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
+ .nr_clk_ids = MIF_NR_CLK,
+ .clk_regs = mif_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
+};
+
+static void __init exynos5433_cmu_mif_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mif_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
+ exynos5433_cmu_mif_init);
+
+/*
+ * Register offset definitions for CMU_PERIC
+ */
+#define DIV_PERIC 0x0600
+#define DIV_STAT_PERIC 0x0700
+#define ENABLE_ACLK_PERIC 0x0800
+#define ENABLE_PCLK_PERIC0 0x0900
+#define ENABLE_PCLK_PERIC1 0x0904
+#define ENABLE_SCLK_PERIC 0x0A00
+#define ENABLE_IP_PERIC0 0x0B00
+#define ENABLE_IP_PERIC1 0x0B04
+#define ENABLE_IP_PERIC2 0x0B08
+
+static const unsigned long peric_clk_regs[] __initconst = {
+ DIV_PERIC,
+ ENABLE_ACLK_PERIC,
+ ENABLE_PCLK_PERIC0,
+ ENABLE_PCLK_PERIC1,
+ ENABLE_SCLK_PERIC,
+ ENABLE_IP_PERIC0,
+ ENABLE_IP_PERIC1,
+ ENABLE_IP_PERIC2,
+};
+
+static const struct samsung_div_clock peric_div_clks[] __initconst = {
+ /* DIV_PERIC */
+ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
+ DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
+};
+
+static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_PERIC */
+ GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
+ ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIC0 */
+ GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 31, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 28, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 26, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 25, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 24, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 23, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 22, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 15,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 14, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 13, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
+ ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
+ 0, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_PCLK_PERIC1 */
+ GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
+ 9, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
+ 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
+ ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_SCLK_PERIC */
+ GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
+ ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
+ ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
+ 19, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
+ 18, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
+ 17, 0, 0),
+ GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
+ 16, 0, 0),
+ GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
+ GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
+ ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
+ ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
+ ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
+ "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
+ ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
+ ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
+ ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
+ 5, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
+ 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
+ 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
+ ENABLE_SCLK_PERIC, 2,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
+ ENABLE_SCLK_PERIC, 1,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
+ ENABLE_SCLK_PERIC, 0,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info peric_cmu_info __initconst = {
+ .div_clks = peric_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peric_div_clks),
+ .gate_clks = peric_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
+ .nr_clk_ids = PERIC_NR_CLK,
+ .clk_regs = peric_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
+};
+
+static void __init exynos5433_cmu_peric_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peric_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
+ exynos5433_cmu_peric_init);
+
+/*
+ * Register offset definitions for CMU_PERIS
+ */
+#define ENABLE_ACLK_PERIS 0x0800
+#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
+#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
+#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
+#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
+#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
+#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
+#define ENABLE_SCLK_PERIS 0x0a00
+#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
+#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
+#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
+#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
+#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
+#define ENABLE_IP_PERIS0 0x0b00
+#define ENABLE_IP_PERIS1 0x0b04
+#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
+#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
+#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
+#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
+#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
+#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
+#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
+
+static const unsigned long peris_clk_regs[] __initconst = {
+ ENABLE_ACLK_PERIS,
+ ENABLE_PCLK_PERIS,
+ ENABLE_PCLK_PERIS_SECURE_TZPC,
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
+ ENABLE_SCLK_PERIS,
+ ENABLE_SCLK_PERIS_SECURE_SECKEY,
+ ENABLE_SCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC,
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON,
+ ENABLE_IP_PERIS0,
+ ENABLE_IP_PERIS1,
+ ENABLE_IP_PERIS_SECURE_TZPC,
+ ENABLE_IP_PERIS_SECURE_SECKEY,
+ ENABLE_IP_PERIS_SECURE_CHIPID,
+ ENABLE_IP_PERIS_SECURE_TOPRTC,
+ ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
+ ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
+ ENABLE_IP_PERIS_SECURE_OTP_CON,
+};
+
+static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_PERIS */
+ GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
+ ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIS */
+ GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
+ ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_TZPC */
+ GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
+ GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
+ GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
+ GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
+ GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
+ "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
+ GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
+ "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
+
+ /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
+ GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
+ "aclk_peris_66",
+ ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS */
+ GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS, 10, 0, 0),
+ GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS, 4, 0, 0),
+ GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS, 3, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
+ GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
+ GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
+ GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
+ GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
+ GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
+
+ /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
+ GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
+ ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info peris_cmu_info __initconst = {
+ .gate_clks = peris_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
+ .nr_clk_ids = PERIS_NR_CLK,
+ .clk_regs = peris_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos5433_cmu_peris_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
+ exynos5433_cmu_peris_init);
+
+/*
+ * Register offset definitions for CMU_FSYS
+ */
+#define MUX_SEL_FSYS0 0x0200
+#define MUX_SEL_FSYS1 0x0204
+#define MUX_SEL_FSYS2 0x0208
+#define MUX_SEL_FSYS3 0x020c
+#define MUX_SEL_FSYS4 0x0210
+#define MUX_ENABLE_FSYS0 0x0300
+#define MUX_ENABLE_FSYS1 0x0304
+#define MUX_ENABLE_FSYS2 0x0308
+#define MUX_ENABLE_FSYS3 0x030c
+#define MUX_ENABLE_FSYS4 0x0310
+#define MUX_STAT_FSYS0 0x0400
+#define MUX_STAT_FSYS1 0x0404
+#define MUX_STAT_FSYS2 0x0408
+#define MUX_STAT_FSYS3 0x040c
+#define MUX_STAT_FSYS4 0x0410
+#define MUX_IGNORE_FSYS2 0x0508
+#define MUX_IGNORE_FSYS3 0x050c
+#define ENABLE_ACLK_FSYS0 0x0800
+#define ENABLE_ACLK_FSYS1 0x0804
+#define ENABLE_PCLK_FSYS 0x0900
+#define ENABLE_SCLK_FSYS 0x0a00
+#define ENABLE_IP_FSYS0 0x0b00
+#define ENABLE_IP_FSYS1 0x0b04
+
+/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
+PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
+PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
+PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
+PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
+PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
+PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
+PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
+PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+ = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+ = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+ = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+ = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+ = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+ = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+ = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+ = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
+PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
+ = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
+ = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
+ = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
+PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
+ = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
+PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
+ = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
+PNAME(mout_sclk_mphy_p)
+ = { "mout_sclk_ufs_mphy_user",
+ "mout_phyclk_lli_mphy_to_ufs_user", };
+
+static const unsigned long fsys_clk_regs[] __initconst = {
+ MUX_SEL_FSYS0,
+ MUX_SEL_FSYS1,
+ MUX_SEL_FSYS2,
+ MUX_SEL_FSYS3,
+ MUX_SEL_FSYS4,
+ MUX_ENABLE_FSYS0,
+ MUX_ENABLE_FSYS1,
+ MUX_ENABLE_FSYS2,
+ MUX_ENABLE_FSYS3,
+ MUX_ENABLE_FSYS4,
+ MUX_IGNORE_FSYS2,
+ MUX_IGNORE_FSYS3,
+ ENABLE_ACLK_FSYS0,
+ ENABLE_ACLK_FSYS1,
+ ENABLE_PCLK_FSYS,
+ ENABLE_SCLK_FSYS,
+ ENABLE_IP_FSYS0,
+ ENABLE_IP_FSYS1,
+};
+
+static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
+ /* PHY clocks from USBDRD30_PHY */
+ FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
+ "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
+ 0, 60000000),
+ FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
+ "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
+ 0, 125000000),
+ /* PHY clocks from USBHOST30_PHY */
+ FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
+ "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
+ 0, 60000000),
+ FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
+ "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
+ 0, 125000000),
+ /* PHY clocks from USBHOST20_PHY */
+ FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
+ "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
+ FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
+ "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
+ FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
+ "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
+ 0, 48000000),
+ FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
+ "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
+ 60000000),
+ /* PHY clocks from UFS_PHY */
+ FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
+ NULL, 0, 300000000),
+ FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
+ NULL, 0, 300000000),
+ FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
+ NULL, 0, 300000000),
+ FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
+ NULL, 0, 300000000),
+ /* PHY clocks from LLI_PHY */
+ FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
+ NULL, 0, 26000000),
+};
+
+static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
+ /* MUX_SEL_FSYS0 */
+ MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
+ mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
+ MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
+ mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
+
+ /* MUX_SEL_FSYS1 */
+ MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
+ mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
+ MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
+ mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
+ MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
+ mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
+ MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
+ mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
+ MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
+ mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
+ MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
+ mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
+ MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
+ mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
+
+ /* MUX_SEL_FSYS2 */
+ MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
+ "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
+ mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
+ MUX_SEL_FSYS2, 28, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
+ "mout_phyclk_usbhost30_uhost30_phyclock_user",
+ mout_phyclk_usbhost30_uhost30_phyclock_user_p,
+ MUX_SEL_FSYS2, 24, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
+ "mout_phyclk_usbhost20_phy_hsic1",
+ mout_phyclk_usbhost20_phy_hsic1_p,
+ MUX_SEL_FSYS2, 20, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
+ "mout_phyclk_usbhost20_phy_clk48mohci_user",
+ mout_phyclk_usbhost20_phy_clk48mohci_user_p,
+ MUX_SEL_FSYS2, 16, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
+ "mout_phyclk_usbhost20_phy_phyclock_user",
+ mout_phyclk_usbhost20_phy_phyclock_user_p,
+ MUX_SEL_FSYS2, 12, 1),
+ MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
+ "mout_phyclk_usbhost20_phy_freeclk_user",
+ mout_phyclk_usbhost20_phy_freeclk_user_p,
+ MUX_SEL_FSYS2, 8, 1),
+ MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
+ "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
+ mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
+ MUX_SEL_FSYS2, 4, 1),
+ MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
+ "mout_phyclk_usbdrd30_udrd30_phyclock_user",
+ mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
+ MUX_SEL_FSYS2, 0, 1),
+
+ /* MUX_SEL_FSYS3 */
+ MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
+ "mout_phyclk_ufs_rx1_symbol_user",
+ mout_phyclk_ufs_rx1_symbol_user_p,
+ MUX_SEL_FSYS3, 16, 1),
+ MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
+ "mout_phyclk_ufs_rx0_symbol_user",
+ mout_phyclk_ufs_rx0_symbol_user_p,
+ MUX_SEL_FSYS3, 12, 1),
+ MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
+ "mout_phyclk_ufs_tx1_symbol_user",
+ mout_phyclk_ufs_tx1_symbol_user_p,
+ MUX_SEL_FSYS3, 8, 1),
+ MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
+ "mout_phyclk_ufs_tx0_symbol_user",
+ mout_phyclk_ufs_tx0_symbol_user_p,
+ MUX_SEL_FSYS3, 4, 1),
+ MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
+ "mout_phyclk_lli_mphy_to_ufs_user",
+ mout_phyclk_lli_mphy_to_ufs_user_p,
+ MUX_SEL_FSYS3, 0, 1),
+
+ /* MUX_SEL_FSYS4 */
+ MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
+ MUX_SEL_FSYS4, 0, 1),
+};
+
+static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_FSYS0 */
+ GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_FSYS1 */
+ GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 13, 0, 0),
+ GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 12, 0, 0),
+ GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
+ "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
+ ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_FSYS */
+ GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 5, 0, 0),
+ GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
+ "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
+ GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
+ "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
+ GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
+ ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
+ "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_FSYS */
+ GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
+ ENABLE_SCLK_FSYS, 21, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
+ "phyclk_usbhost30_uhost30_pipe_pclk",
+ "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
+ ENABLE_SCLK_FSYS, 18, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
+ "phyclk_usbhost30_uhost30_phyclock",
+ "mout_phyclk_usbhost30_uhost30_phyclock_user",
+ ENABLE_SCLK_FSYS, 17, 0, 0),
+ GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
+ "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
+ 16, 0, 0),
+ GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
+ "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
+ 15, 0, 0),
+ GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
+ "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
+ 14, 0, 0),
+ GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
+ "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
+ 13, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
+ "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
+ 12, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
+ "phyclk_usbhost20_phy_clk48mohci",
+ "mout_phyclk_usbhost20_phy_clk48mohci_user",
+ ENABLE_SCLK_FSYS, 11, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
+ "phyclk_usbhost20_phy_phyclock",
+ "mout_phyclk_usbhost20_phy_phyclock_user",
+ ENABLE_SCLK_FSYS, 10, 0, 0),
+ GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
+ "phyclk_usbhost20_phy_freeclk",
+ "mout_phyclk_usbhost20_phy_freeclk_user",
+ ENABLE_SCLK_FSYS, 9, 0, 0),
+ GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
+ "phyclk_usbdrd30_udrd30_pipe_pclk",
+ "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
+ ENABLE_SCLK_FSYS, 8, 0, 0),
+ GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
+ "phyclk_usbdrd30_udrd30_phyclock",
+ "mout_phyclk_usbdrd30_udrd30_phyclock_user",
+ ENABLE_SCLK_FSYS, 7, 0, 0),
+ GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
+ ENABLE_SCLK_FSYS, 6, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
+ ENABLE_SCLK_FSYS, 5, 0, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
+ ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
+ ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
+ ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
+ ENABLE_SCLK_FSYS, 1, 0, 0),
+ GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
+ ENABLE_SCLK_FSYS, 0, 0, 0),
+
+ /* ENABLE_IP_FSYS0 */
+ GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys_cmu_info __initconst = {
+ .mux_clks = fsys_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
+ .gate_clks = fsys_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
+ .fixed_clks = fsys_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
+ .nr_clk_ids = FSYS_NR_CLK,
+ .clk_regs = fsys_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
+};
+
+static void __init exynos5433_cmu_fsys_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &fsys_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
+ exynos5433_cmu_fsys_init);
+
+/*
+ * Register offset definitions for CMU_G2D
+ */
+#define MUX_SEL_G2D0 0x0200
+#define MUX_SEL_ENABLE_G2D0 0x0300
+#define MUX_SEL_STAT_G2D0 0x0400
+#define DIV_G2D 0x0600
+#define DIV_STAT_G2D 0x0700
+#define DIV_ENABLE_ACLK_G2D 0x0800
+#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
+#define DIV_ENABLE_PCLK_G2D 0x0900
+#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
+#define DIV_ENABLE_IP_G2D0 0x0b00
+#define DIV_ENABLE_IP_G2D1 0x0b04
+#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
+
+static const unsigned long g2d_clk_regs[] __initconst = {
+ MUX_SEL_G2D0,
+ MUX_SEL_ENABLE_G2D0,
+ DIV_G2D,
+ DIV_ENABLE_ACLK_G2D,
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_PCLK_G2D,
+ DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
+ DIV_ENABLE_IP_G2D0,
+ DIV_ENABLE_IP_G2D1,
+ DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
+PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
+
+static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
+ /* MUX_SEL_G2D0 */
+ MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
+ mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
+ MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
+ mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
+};
+
+static const struct samsung_div_clock g2d_div_clks[] __initconst = {
+ /* DIV_G2D */
+ DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
+ DIV_G2D, 0, 2),
+};
+
+static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
+ /* DIV_ENABLE_ACLK_G2D */
+ GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
+ DIV_ENABLE_ACLK_G2D, 12, 0, 0),
+ GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
+ DIV_ENABLE_ACLK_G2D, 11, 0, 0),
+ GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 10, 0, 0),
+ GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 9, 0, 0),
+ GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 8, 0, 0),
+ GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
+ "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
+ 7, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
+ DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
+ DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
+ DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
+ DIV_ENABLE_ACLK_G2D, 1, 0, 0),
+ GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D, 0, 0, 0),
+
+ /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
+ GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
+ DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
+
+ /* DIV_ENABLE_PCLK_G2D */
+ GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 7, 0, 0),
+ GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 6, 0, 0),
+ GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 5, 0, 0),
+ GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 4, 0, 0),
+ GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 3, 0, 0),
+ GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
+ 0, 0, 0),
+
+ /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
+ GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
+ DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info g2d_cmu_info __initconst = {
+ .mux_clks = g2d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
+ .div_clks = g2d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
+ .gate_clks = g2d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
+ .nr_clk_ids = G2D_NR_CLK,
+ .clk_regs = g2d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
+};
+
+static void __init exynos5433_cmu_g2d_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &g2d_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
+ exynos5433_cmu_g2d_init);
+
+/*
+ * Register offset definitions for CMU_DISP
+ */
+#define DISP_PLL_LOCK 0x0000
+#define DISP_PLL_CON0 0x0100
+#define DISP_PLL_CON1 0x0104
+#define DISP_PLL_FREQ_DET 0x0108
+#define MUX_SEL_DISP0 0x0200
+#define MUX_SEL_DISP1 0x0204
+#define MUX_SEL_DISP2 0x0208
+#define MUX_SEL_DISP3 0x020c
+#define MUX_SEL_DISP4 0x0210
+#define MUX_ENABLE_DISP0 0x0300
+#define MUX_ENABLE_DISP1 0x0304
+#define MUX_ENABLE_DISP2 0x0308
+#define MUX_ENABLE_DISP3 0x030c
+#define MUX_ENABLE_DISP4 0x0310
+#define MUX_STAT_DISP0 0x0400
+#define MUX_STAT_DISP1 0x0404
+#define MUX_STAT_DISP2 0x0408
+#define MUX_STAT_DISP3 0x040c
+#define MUX_STAT_DISP4 0x0410
+#define MUX_IGNORE_DISP2 0x0508
+#define DIV_DISP 0x0600
+#define DIV_DISP_PLL_FREQ_DET 0x0604
+#define DIV_STAT_DISP 0x0700
+#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_DISP0 0x0800
+#define ENABLE_ACLK_DISP1 0x0804
+#define ENABLE_PCLK_DISP 0x0900
+#define ENABLE_SCLK_DISP 0x0a00
+#define ENABLE_IP_DISP0 0x0b00
+#define ENABLE_IP_DISP1 0x0b04
+#define CLKOUT_CMU_DISP 0x0c00
+#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
+
+static const unsigned long disp_clk_regs[] __initconst = {
+ DISP_PLL_LOCK,
+ DISP_PLL_CON0,
+ DISP_PLL_CON1,
+ DISP_PLL_FREQ_DET,
+ MUX_SEL_DISP0,
+ MUX_SEL_DISP1,
+ MUX_SEL_DISP2,
+ MUX_SEL_DISP3,
+ MUX_SEL_DISP4,
+ MUX_ENABLE_DISP0,
+ MUX_ENABLE_DISP1,
+ MUX_ENABLE_DISP2,
+ MUX_ENABLE_DISP3,
+ MUX_ENABLE_DISP4,
+ MUX_IGNORE_DISP2,
+ DIV_DISP,
+ DIV_DISP_PLL_FREQ_DET,
+ ENABLE_ACLK_DISP0,
+ ENABLE_ACLK_DISP1,
+ ENABLE_PCLK_DISP,
+ ENABLE_SCLK_DISP,
+ ENABLE_IP_DISP0,
+ ENABLE_IP_DISP1,
+ CLKOUT_CMU_DISP,
+ CLKOUT_CMU_DISP_DIV_STAT,
+};
+
+/* list of all parent clock list */
+PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
+PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
+PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
+PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
+PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
+ "sclk_decon_tv_eclk_disp", };
+PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
+ "sclk_decon_vclk_disp", };
+PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
+ "sclk_decon_eclk_disp", };
+PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
+ "sclk_decon_tv_vclk_disp", };
+PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
+
+PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
+ "phyclk_mipidphy1_bitclkdiv8_phy", };
+PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
+ "phyclk_mipidphy1_rxclkesc0_phy", };
+PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
+ "phyclk_mipidphy0_bitclkdiv8_phy", };
+PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
+ "phyclk_mipidphy0_rxclkesc0_phy", };
+PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
+ "phyclk_hdmiphy_tmds_clko_phy", };
+PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
+ "phyclk_hdmiphy_pixel_clko_phy", };
+
+PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
+ "mout_sclk_dsim0_user", };
+PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
+ "mout_sclk_decon_tv_eclk_user", };
+PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
+ "mout_sclk_decon_vclk_user", };
+PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
+ "mout_sclk_decon_eclk_user", };
+
+PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
+ "mout_sclk_dsim1_user", };
+PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
+ "mout_phyclk_hdmiphy_pixel_clko_user",
+ "mout_sclk_decon_tv_vclk_b_disp", };
+PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
+ "mout_sclk_decon_tv_vclk_user", };
+
+static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
+ DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
+};
+
+static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
+ /*
+ * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
+ * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
+ * and sclk_decon_{vclk|tv_vclk}.
+ */
+ FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
+ 1, 2, 0),
+ FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
+ 1, 2, 0),
+};
+
+static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
+ /* PHY clocks from MIPI_DPHY1 */
+ FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
+ FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
+ /* PHY clocks from MIPI_DPHY0 */
+ FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
+ FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
+ /* PHY clocks from HDMI_PHY */
+ FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
+ NULL, 0, 300000000),
+ FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
+ NULL, 0, 166000000),
+};
+
+static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
+ /* MUX_SEL_DISP0 */
+ MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
+ 0, 1),
+
+ /* MUX_SEL_DISP1 */
+ MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
+ mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
+ MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
+ mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
+ MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
+ MUX_SEL_DISP1, 20, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
+ mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
+ mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
+ mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
+ mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
+ MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
+ mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
+
+ /* MUX_SEL_DISP2 */
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
+ "mout_phyclk_mipidphy1_bitclkdiv8_user",
+ mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
+ 20, 1),
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
+ "mout_phyclk_mipidphy1_rxclkesc0_user",
+ mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
+ 16, 1),
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
+ "mout_phyclk_mipidphy0_bitclkdiv8_user",
+ mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
+ 12, 1),
+ MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
+ "mout_phyclk_mipidphy0_rxclkesc0_user",
+ mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
+ 8, 1),
+ MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
+ "mout_phyclk_hdmiphy_tmds_clko_user",
+ mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
+ 4, 1),
+ MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
+ "mout_phyclk_hdmiphy_pixel_clko_user",
+ mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
+ 0, 1),
+
+ /* MUX_SEL_DISP3 */
+ MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
+ MUX_SEL_DISP3, 12, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
+ mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
+ mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
+ MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
+ mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
+
+ /* MUX_SEL_DISP4 */
+ MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
+ mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
+ MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
+ mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
+ "mout_sclk_decon_tv_vclk_c_disp",
+ mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
+ "mout_sclk_decon_tv_vclk_b_disp",
+ mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
+ MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
+ "mout_sclk_decon_tv_vclk_a_disp",
+ mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
+};
+
+static const struct samsung_div_clock disp_div_clks[] __initconst = {
+ /* DIV_DISP */
+ DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
+ "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
+ DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
+ "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
+ DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
+ DIV_DISP, 16, 3),
+ DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
+ "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
+ DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
+ "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
+ DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
+ "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
+ DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
+ DIV_DISP, 0, 2),
+};
+
+static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_DISP0 */
+ GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP0, 2, 0, 0),
+ GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP0, 0, 0, 0),
+
+ /* ENABLE_ACLK_DISP1 */
+ GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 25, 0, 0),
+ GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 24, 0, 0),
+ GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
+ GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
+ GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
+ "div_pclk_disp", ENABLE_ACLK_DISP1,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
+ "div_pclk_disp", ENABLE_ACLK_DISP1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
+ "div_pclk_disp", ENABLE_ACLK_DISP1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
+ ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 7, 0, 0),
+ GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 6, 0, 0),
+ GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
+ GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
+ GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
+ ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
+ ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
+ "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_DISP */
+ GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 23, 0, 0),
+ GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 22, 0, 0),
+ GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 21, 0, 0),
+ GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 20, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 19, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 18, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 17, 0, 0),
+ GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 16, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 15, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 14, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 13, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 12, 0, 0),
+ GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 11, 0, 0),
+ GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 10, 0, 0),
+ GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 7, 0, 0),
+ GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 6, 0, 0),
+ GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 5, 0, 0),
+ GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 3, 0, 0),
+ GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 2, 0, 0),
+ GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 1, 0, 0),
+ GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 0, 0, 0),
+
+ /* ENABLE_SCLK_DISP */
+ GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
+ "mout_phyclk_mipidphy1_bitclkdiv8_user",
+ ENABLE_SCLK_DISP, 26, 0, 0),
+ GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
+ "mout_phyclk_mipidphy1_rxclkesc0_user",
+ ENABLE_SCLK_DISP, 25, 0, 0),
+ GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
+ "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
+ GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
+ "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
+ GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
+ ENABLE_SCLK_DISP, 22, 0, 0),
+ GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
+ "div_sclk_decon_tv_vclk_disp",
+ ENABLE_SCLK_DISP, 21, 0, 0),
+ GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
+ "mout_phyclk_mipidphy0_bitclkdiv8_user",
+ ENABLE_SCLK_DISP, 15, 0, 0),
+ GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
+ "mout_phyclk_mipidphy0_rxclkesc0_user",
+ ENABLE_SCLK_DISP, 14, 0, 0),
+ GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
+ "mout_phyclk_hdmiphy_tmds_clko_user",
+ ENABLE_SCLK_DISP, 13, 0, 0),
+ GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
+ "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
+ GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
+ "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
+ GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
+ "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
+ GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
+ "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
+ GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
+ ENABLE_SCLK_DISP, 7, 0, 0),
+ GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
+ ENABLE_SCLK_DISP, 6, 0, 0),
+ GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
+ ENABLE_SCLK_DISP, 5, 0, 0),
+ GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
+ "div_sclk_decon_tv_eclk_disp",
+ ENABLE_SCLK_DISP, 4, 0, 0),
+ GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
+ "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
+ GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
+ "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
+};
+
+static const struct samsung_cmu_info disp_cmu_info __initconst = {
+ .pll_clks = disp_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
+ .mux_clks = disp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
+ .div_clks = disp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(disp_div_clks),
+ .gate_clks = disp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
+ .fixed_clks = disp_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
+ .fixed_factor_clks = disp_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
+ .nr_clk_ids = DISP_NR_CLK,
+ .clk_regs = disp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
+};
+
+static void __init exynos5433_cmu_disp_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &disp_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
+ exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0 0x0200
+#define MUX_SEL_AUD1 0x0204
+#define MUX_ENABLE_AUD0 0x0300
+#define MUX_ENABLE_AUD1 0x0304
+#define MUX_STAT_AUD0 0x0400
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define ENABLE_ACLK_AUD 0x0800
+#define ENABLE_PCLK_AUD 0x0900
+#define ENABLE_SCLK_AUD0 0x0a00
+#define ENABLE_SCLK_AUD1 0x0a04
+#define ENABLE_IP_AUD0 0x0b00
+#define ENABLE_IP_AUD1 0x0b04
+
+static const unsigned long aud_clk_regs[] __initconst = {
+ MUX_SEL_AUD0,
+ MUX_SEL_AUD1,
+ MUX_ENABLE_AUD0,
+ MUX_ENABLE_AUD1,
+ DIV_AUD0,
+ DIV_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD0,
+ ENABLE_SCLK_AUD1,
+ ENABLE_IP_AUD0,
+ ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
+PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
+
+static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
+ FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
+ FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
+ FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
+};
+
+static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
+ /* MUX_SEL_AUD0 */
+ MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
+ mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+ /* MUX_SEL_AUD1 */
+ MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 8, 1),
+ MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 0, 1),
+};
+
+static const struct samsung_div_clock aud_div_clks[] __initconst = {
+ /* DIV_AUD0 */
+ DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
+ 12, 4),
+ DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
+ 8, 4),
+ DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
+ 4, 4),
+ DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
+ 0, 4),
+
+ /* DIV_AUD1 */
+ DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
+ "mout_aud_pll_user", DIV_AUD1, 16, 5),
+ DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
+ DIV_AUD1, 12, 4),
+ DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
+ DIV_AUD1, 4, 8),
+ DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
+ DIV_AUD1, 0, 4),
+};
+
+static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_AUD */
+ GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 12, 0, 0),
+ GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 7, 0, 0),
+ GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 0, 4, 0),
+ GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 0, 3, 0),
+ GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
+ ENABLE_ACLK_AUD, 0, 2, 0),
+ GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
+ 0, 1, 0),
+ GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_AUD */
+ GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 13, 0, 0),
+ GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 12, 0, 0),
+ GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 11, 0, 0),
+ GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 10, 0, 0),
+ GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 6, 0, 0),
+ GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 5, 0, 0),
+ GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 4, 0, 0),
+ GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 3, 0, 0),
+ GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
+ 2, 0, 0),
+ GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
+ ENABLE_PCLK_AUD, 0, 0, 0),
+
+ /* ENABLE_SCLK_AUD0 */
+ GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
+ ENABLE_SCLK_AUD0, 1, 0, 0),
+ GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
+ 0, 0, 0),
+
+ /* ENABLE_SCLK_AUD1 */
+ GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
+ ENABLE_SCLK_AUD1, 6, 0, 0),
+ GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
+ ENABLE_SCLK_AUD1, 5, 0, 0),
+ GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
+ ENABLE_SCLK_AUD1, 4, 0, 0),
+ GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
+ ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
+ ENABLE_SCLK_AUD1, 2, 0, 0),
+ GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
+ ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
+ ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info aud_cmu_info __initconst = {
+ .mux_clks = aud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
+ .div_clks = aud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(aud_div_clks),
+ .gate_clks = aud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
+ .fixed_clks = aud_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
+ .nr_clk_ids = AUD_NR_CLK,
+ .clk_regs = aud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos5433_cmu_aud_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &aud_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
+ exynos5433_cmu_aud_init);
+
+
+/*
+ * Register offset definitions for CMU_BUS{0|1|2}
+ */
+#define DIV_BUS 0x0600
+#define DIV_STAT_BUS 0x0700
+#define ENABLE_ACLK_BUS 0x0800
+#define ENABLE_PCLK_BUS 0x0900
+#define ENABLE_IP_BUS0 0x0b00
+#define ENABLE_IP_BUS1 0x0b04
+
+#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
+#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
+#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
+
+/* list of all parent clock list */
+PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
+
+#define CMU_BUS_COMMON_CLK_REGS \
+ DIV_BUS, \
+ ENABLE_ACLK_BUS, \
+ ENABLE_PCLK_BUS, \
+ ENABLE_IP_BUS0, \
+ ENABLE_IP_BUS1
+
+static const unsigned long bus01_clk_regs[] __initconst = {
+ CMU_BUS_COMMON_CLK_REGS,
+};
+
+static const unsigned long bus2_clk_regs[] __initconst = {
+ MUX_SEL_BUS2,
+ MUX_ENABLE_BUS2,
+ CMU_BUS_COMMON_CLK_REGS,
+};
+
+static const struct samsung_div_clock bus0_div_clks[] __initconst = {
+ /* DIV_BUS0 */
+ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
+ DIV_BUS, 0, 3),
+};
+
+/* CMU_BUS0 clocks */
+static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_BUS0 */
+ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
+ ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
+ ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
+ ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS0 */
+ GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/* CMU_BUS1 clocks */
+static const struct samsung_div_clock bus1_div_clks[] __initconst = {
+ /* DIV_BUS1 */
+ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
+ DIV_BUS, 0, 3),
+};
+
+static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_BUS1 */
+ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
+ ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
+ ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
+ ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS1 */
+ GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+/* CMU_BUS2 clocks */
+static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
+ /* MUX_SEL_BUS2 */
+ MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
+ mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
+};
+
+static const struct samsung_div_clock bus2_div_clks[] __initconst = {
+ /* DIV_BUS2 */
+ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
+ "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
+};
+
+static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_BUS2 */
+ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
+ ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
+ ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
+ "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
+ "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS2 */
+ GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+#define CMU_BUS_INFO_CLKS(id) \
+ .div_clks = bus##id##_div_clks, \
+ .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
+ .gate_clks = bus##id##_gate_clks, \
+ .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
+ .nr_clk_ids = BUSx_NR_CLK
+
+static const struct samsung_cmu_info bus0_cmu_info __initconst = {
+ CMU_BUS_INFO_CLKS(0),
+ .clk_regs = bus01_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
+};
+
+static const struct samsung_cmu_info bus1_cmu_info __initconst = {
+ CMU_BUS_INFO_CLKS(1),
+ .clk_regs = bus01_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
+};
+
+static const struct samsung_cmu_info bus2_cmu_info __initconst = {
+ CMU_BUS_INFO_CLKS(2),
+ .mux_clks = bus2_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
+ .clk_regs = bus2_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
+};
+
+#define exynos5433_cmu_bus_init(id) \
+static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
+{ \
+ samsung_cmu_register_one(np, &bus##id##_cmu_info); \
+} \
+CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
+ "samsung,exynos5433-cmu-bus"#id, \
+ exynos5433_cmu_bus##id##_init)
+
+exynos5433_cmu_bus_init(0);
+exynos5433_cmu_bus_init(1);
+exynos5433_cmu_bus_init(2);
+
+/*
+ * Register offset definitions for CMU_G3D
+ */
+#define G3D_PLL_LOCK 0x0000
+#define G3D_PLL_CON0 0x0100
+#define G3D_PLL_CON1 0x0104
+#define G3D_PLL_FREQ_DET 0x010c
+#define MUX_SEL_G3D 0x0200
+#define MUX_ENABLE_G3D 0x0300
+#define MUX_STAT_G3D 0x0400
+#define DIV_G3D 0x0600
+#define DIV_G3D_PLL_FREQ_DET 0x0604
+#define DIV_STAT_G3D 0x0700
+#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
+#define ENABLE_ACLK_G3D 0x0800
+#define ENABLE_PCLK_G3D 0x0900
+#define ENABLE_SCLK_G3D 0x0a00
+#define ENABLE_IP_G3D0 0x0b00
+#define ENABLE_IP_G3D1 0x0b04
+#define CLKOUT_CMU_G3D 0x0c00
+#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
+#define CLK_STOPCTRL 0x1000
+
+static const unsigned long g3d_clk_regs[] __initconst = {
+ G3D_PLL_LOCK,
+ G3D_PLL_CON0,
+ G3D_PLL_CON1,
+ G3D_PLL_FREQ_DET,
+ MUX_SEL_G3D,
+ MUX_ENABLE_G3D,
+ DIV_G3D,
+ DIV_G3D_PLL_FREQ_DET,
+ ENABLE_ACLK_G3D,
+ ENABLE_PCLK_G3D,
+ ENABLE_SCLK_G3D,
+ ENABLE_IP_G3D0,
+ ENABLE_IP_G3D1,
+ CLKOUT_CMU_G3D,
+ CLKOUT_CMU_G3D_DIV_STAT,
+ CLK_STOPCTRL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
+PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
+
+static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
+ G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
+};
+
+static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
+ /* MUX_SEL_G3D */
+ MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
+ MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+ MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock g3d_div_clks[] __initconst = {
+ /* DIV_G3D */
+ DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
+ 8, 2),
+ DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
+ 4, 3),
+ DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
+ 0, 3, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_G3D */
+ GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 7, 0, 0),
+ GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 6, 0, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
+ ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
+ ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
+ ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
+ ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+ /* ENABLE_PCLK_G3D */
+ GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 3, 0, 0),
+ GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
+ ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_G3D */
+ GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
+ ENABLE_SCLK_G3D, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info g3d_cmu_info __initconst = {
+ .pll_clks = g3d_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
+ .mux_clks = g3d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
+ .div_clks = g3d_div_clks,
+ .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
+ .gate_clks = g3d_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
+ .nr_clk_ids = G3D_NR_CLK,
+ .clk_regs = g3d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
+};
+
+static void __init exynos5433_cmu_g3d_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &g3d_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
+ exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL 0x0300
+#define MUX_STAT_GSCL 0x0400
+#define ENABLE_ACLK_GSCL 0x0800
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#define ENABLE_PCLK_GSCL 0x0900
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#define ENABLE_IP_GSCL0 0x0b00
+#define ENABLE_IP_GSCL1 0x0b04
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
+#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
+
+static const unsigned long gscl_clk_regs[] __initconst = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
+PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
+
+static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
+ aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
+};
+
+static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_GSCL */
+ GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 11, 0, 0),
+ GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 10, 0, 0),
+ GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 9, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
+ "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 7, 0, 0),
+ GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
+ ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
+ "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
+ "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 3, 0, 0),
+ GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 2, 0, 0),
+ GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 1, 0, 0),
+ GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL, 0, 0, 0),
+
+ /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
+ GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+ /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
+ GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
+
+ /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
+ GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL */
+ GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 7, 0, 0),
+ GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 6, 0, 0),
+ GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 5, 0, 0),
+ GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
+ "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 2, 0, 0),
+ GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 1, 0, 0),
+ GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
+ GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
+ GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
+
+ /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
+ GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info gscl_cmu_info __initconst = {
+ .mux_clks = gscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
+ .gate_clks = gscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
+ .nr_clk_ids = GSCL_NR_CLK,
+ .clk_regs = gscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
+};
+
+static void __init exynos5433_cmu_gscl_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &gscl_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
+ exynos5433_cmu_gscl_init);
+
+/*
+ * Register offset definitions for CMU_APOLLO
+ */
+#define APOLLO_PLL_LOCK 0x0000
+#define APOLLO_PLL_CON0 0x0100
+#define APOLLO_PLL_CON1 0x0104
+#define APOLLO_PLL_FREQ_DET 0x010c
+#define MUX_SEL_APOLLO0 0x0200
+#define MUX_SEL_APOLLO1 0x0204
+#define MUX_SEL_APOLLO2 0x0208
+#define MUX_ENABLE_APOLLO0 0x0300
+#define MUX_ENABLE_APOLLO1 0x0304
+#define MUX_ENABLE_APOLLO2 0x0308
+#define MUX_STAT_APOLLO0 0x0400
+#define MUX_STAT_APOLLO1 0x0404
+#define MUX_STAT_APOLLO2 0x0408
+#define DIV_APOLLO0 0x0600
+#define DIV_APOLLO1 0x0604
+#define DIV_APOLLO_PLL_FREQ_DET 0x0608
+#define DIV_STAT_APOLLO0 0x0700
+#define DIV_STAT_APOLLO1 0x0704
+#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
+#define ENABLE_ACLK_APOLLO 0x0800
+#define ENABLE_PCLK_APOLLO 0x0900
+#define ENABLE_SCLK_APOLLO 0x0a00
+#define ENABLE_IP_APOLLO0 0x0b00
+#define ENABLE_IP_APOLLO1 0x0b04
+#define CLKOUT_CMU_APOLLO 0x0c00
+#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
+#define ARMCLK_STOPCTRL 0x1000
+#define APOLLO_PWR_CTRL 0x1020
+#define APOLLO_PWR_CTRL2 0x1024
+#define APOLLO_INTR_SPREAD_ENABLE 0x1080
+#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
+#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
+
+static const unsigned long apollo_clk_regs[] __initconst = {
+ APOLLO_PLL_LOCK,
+ APOLLO_PLL_CON0,
+ APOLLO_PLL_CON1,
+ APOLLO_PLL_FREQ_DET,
+ MUX_SEL_APOLLO0,
+ MUX_SEL_APOLLO1,
+ MUX_SEL_APOLLO2,
+ MUX_ENABLE_APOLLO0,
+ MUX_ENABLE_APOLLO1,
+ MUX_ENABLE_APOLLO2,
+ DIV_APOLLO0,
+ DIV_APOLLO1,
+ DIV_APOLLO_PLL_FREQ_DET,
+ ENABLE_ACLK_APOLLO,
+ ENABLE_PCLK_APOLLO,
+ ENABLE_SCLK_APOLLO,
+ ENABLE_IP_APOLLO0,
+ ENABLE_IP_APOLLO1,
+ CLKOUT_CMU_APOLLO,
+ CLKOUT_CMU_APOLLO_DIV_STAT,
+ ARMCLK_STOPCTRL,
+ APOLLO_PWR_CTRL,
+ APOLLO_PWR_CTRL2,
+ APOLLO_INTR_SPREAD_ENABLE,
+ APOLLO_INTR_SPREAD_USE_STANDBYWFI,
+ APOLLO_INTR_SPREAD_BLOCKING_DURATION,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
+PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
+PNAME(mout_apollo_p) = { "mout_apollo_pll",
+ "mout_bus_pll_apollo_user", };
+
+static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
+ APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
+};
+
+static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
+ /* MUX_SEL_APOLLO0 */
+ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
+ MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
+ CLK_RECALC_NEW_RATES, 0),
+
+ /* MUX_SEL_APOLLO1 */
+ MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
+ mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
+
+ /* MUX_SEL_APOLLO2 */
+ MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
+ 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock apollo_div_clks[] __initconst = {
+ /* DIV_APOLLO0 */
+ DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
+ DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
+ DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
+ DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
+ DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
+ DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
+ DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
+ DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
+ DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
+
+ /* DIV_APOLLO1 */
+ DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
+ DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
+ DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+};
+
+static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_APOLLO */
+ GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
+ "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
+ "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
+ "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+ 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
+ "div_atclk_apollo", ENABLE_ACLK_APOLLO,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
+ "div_aclk_apollo", ENABLE_ACLK_APOLLO,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
+ "div_pclk_apollo", ENABLE_ACLK_APOLLO,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
+ "div_pclk_apollo", ENABLE_ACLK_APOLLO,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_APOLLO */
+ GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
+ "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
+ ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
+ "div_pclk_apollo", ENABLE_PCLK_APOLLO,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_APOLLO */
+ GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
+ ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
+ ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
+};
+
+#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
+ (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
+ ((pclk) << 12) | ((aclk) << 8))
+
+#define E5433_APOLLO_DIV1(hpm, copy) \
+ (((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
+ { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
+ { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
+ { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
+ { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
+ { 0 },
+};
+
+static void __init exynos5433_cmu_apollo_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ struct samsung_clk_provider *ctx;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ panic("%s: failed to map registers\n", __func__);
+ return;
+ }
+
+ ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
+ if (!ctx) {
+ panic("%s: unable to allocate ctx\n", __func__);
+ return;
+ }
+
+ samsung_clk_register_pll(ctx, apollo_pll_clks,
+ ARRAY_SIZE(apollo_pll_clks), reg_base);
+ samsung_clk_register_mux(ctx, apollo_mux_clks,
+ ARRAY_SIZE(apollo_mux_clks));
+ samsung_clk_register_div(ctx, apollo_div_clks,
+ ARRAY_SIZE(apollo_div_clks));
+ samsung_clk_register_gate(ctx, apollo_gate_clks,
+ ARRAY_SIZE(apollo_gate_clks));
+
+ exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
+ mout_apollo_p[0], mout_apollo_p[1], 0x200,
+ exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
+ CLK_CPU_HAS_E5433_REGS_LAYOUT);
+
+ samsung_clk_sleep_init(reg_base, apollo_clk_regs,
+ ARRAY_SIZE(apollo_clk_regs));
+
+ samsung_clk_of_add_provider(np, ctx);
+}
+CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
+ exynos5433_cmu_apollo_init);
+
+/*
+ * Register offset definitions for CMU_ATLAS
+ */
+#define ATLAS_PLL_LOCK 0x0000
+#define ATLAS_PLL_CON0 0x0100
+#define ATLAS_PLL_CON1 0x0104
+#define ATLAS_PLL_FREQ_DET 0x010c
+#define MUX_SEL_ATLAS0 0x0200
+#define MUX_SEL_ATLAS1 0x0204
+#define MUX_SEL_ATLAS2 0x0208
+#define MUX_ENABLE_ATLAS0 0x0300
+#define MUX_ENABLE_ATLAS1 0x0304
+#define MUX_ENABLE_ATLAS2 0x0308
+#define MUX_STAT_ATLAS0 0x0400
+#define MUX_STAT_ATLAS1 0x0404
+#define MUX_STAT_ATLAS2 0x0408
+#define DIV_ATLAS0 0x0600
+#define DIV_ATLAS1 0x0604
+#define DIV_ATLAS_PLL_FREQ_DET 0x0608
+#define DIV_STAT_ATLAS0 0x0700
+#define DIV_STAT_ATLAS1 0x0704
+#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
+#define ENABLE_ACLK_ATLAS 0x0800
+#define ENABLE_PCLK_ATLAS 0x0900
+#define ENABLE_SCLK_ATLAS 0x0a00
+#define ENABLE_IP_ATLAS0 0x0b00
+#define ENABLE_IP_ATLAS1 0x0b04
+#define CLKOUT_CMU_ATLAS 0x0c00
+#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
+#define ARMCLK_STOPCTRL 0x1000
+#define ATLAS_PWR_CTRL 0x1020
+#define ATLAS_PWR_CTRL2 0x1024
+#define ATLAS_INTR_SPREAD_ENABLE 0x1080
+#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
+#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
+
+static const unsigned long atlas_clk_regs[] __initconst = {
+ ATLAS_PLL_LOCK,
+ ATLAS_PLL_CON0,
+ ATLAS_PLL_CON1,
+ ATLAS_PLL_FREQ_DET,
+ MUX_SEL_ATLAS0,
+ MUX_SEL_ATLAS1,
+ MUX_SEL_ATLAS2,
+ MUX_ENABLE_ATLAS0,
+ MUX_ENABLE_ATLAS1,
+ MUX_ENABLE_ATLAS2,
+ DIV_ATLAS0,
+ DIV_ATLAS1,
+ DIV_ATLAS_PLL_FREQ_DET,
+ ENABLE_ACLK_ATLAS,
+ ENABLE_PCLK_ATLAS,
+ ENABLE_SCLK_ATLAS,
+ ENABLE_IP_ATLAS0,
+ ENABLE_IP_ATLAS1,
+ CLKOUT_CMU_ATLAS,
+ CLKOUT_CMU_ATLAS_DIV_STAT,
+ ARMCLK_STOPCTRL,
+ ATLAS_PWR_CTRL,
+ ATLAS_PWR_CTRL2,
+ ATLAS_INTR_SPREAD_ENABLE,
+ ATLAS_INTR_SPREAD_USE_STANDBYWFI,
+ ATLAS_INTR_SPREAD_BLOCKING_DURATION,
+};
+
+/* list of all parent clock list */
+PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
+PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
+PNAME(mout_atlas_p) = { "mout_atlas_pll",
+ "mout_bus_pll_atlas_user", };
+
+static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
+ PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
+ ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
+};
+
+static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
+ /* MUX_SEL_ATLAS0 */
+ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
+ MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
+ CLK_RECALC_NEW_RATES, 0),
+
+ /* MUX_SEL_ATLAS1 */
+ MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
+ mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
+
+ /* MUX_SEL_ATLAS2 */
+ MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
+ 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock atlas_div_clks[] __initconst = {
+ /* DIV_ATLAS0 */
+ DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
+ DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
+ DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
+ DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
+ DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
+ DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
+ DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
+ DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
+ DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
+
+ /* DIV_ATLAS1 */
+ DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
+ DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
+ DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
+ CLK_DIVIDER_READ_ONLY),
+};
+
+static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_ATLAS */
+ GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
+ "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
+ "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
+ "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
+ "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
+ "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
+ "div_atclk_atlas", ENABLE_ACLK_ATLAS,
+ 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
+ "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
+ "div_aclk_atlas", ENABLE_ACLK_ATLAS,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
+ ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
+ ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_ATLAS */
+ GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
+ "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
+ "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
+ 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
+ "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
+ ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
+ ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
+ ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_ATLAS */
+ GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
+ ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
+ ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
+ ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
+ ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
+ ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
+ ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
+ ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
+ ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
+};
+
+#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
+ (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
+ ((pclk) << 12) | ((aclk) << 8))
+
+#define E5433_ATLAS_DIV1(hpm, copy) \
+ (((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
+ { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
+ { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
+ { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
+ { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
+ { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
+ { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
+ { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
+ { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
+ { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
+ { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
+ { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
+ { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
+ { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
+ { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
+ { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
+ { 0 },
+};
+
+static void __init exynos5433_cmu_atlas_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ struct samsung_clk_provider *ctx;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ panic("%s: failed to map registers\n", __func__);
+ return;
+ }
+
+ ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
+ if (!ctx) {
+ panic("%s: unable to allocate ctx\n", __func__);
+ return;
+ }
+
+ samsung_clk_register_pll(ctx, atlas_pll_clks,
+ ARRAY_SIZE(atlas_pll_clks), reg_base);
+ samsung_clk_register_mux(ctx, atlas_mux_clks,
+ ARRAY_SIZE(atlas_mux_clks));
+ samsung_clk_register_div(ctx, atlas_div_clks,
+ ARRAY_SIZE(atlas_div_clks));
+ samsung_clk_register_gate(ctx, atlas_gate_clks,
+ ARRAY_SIZE(atlas_gate_clks));
+
+ exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
+ mout_atlas_p[0], mout_atlas_p[1], 0x200,
+ exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
+ CLK_CPU_HAS_E5433_REGS_LAYOUT);
+
+ samsung_clk_sleep_init(reg_base, atlas_clk_regs,
+ ARRAY_SIZE(atlas_clk_regs));
+
+ samsung_clk_of_add_provider(np, ctx);
+}
+CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
+ exynos5433_cmu_atlas_init);
+
+/*
+ * Register offset definitions for CMU_MSCL
+ */
+#define MUX_SEL_MSCL0 0x0200
+#define MUX_SEL_MSCL1 0x0204
+#define MUX_ENABLE_MSCL0 0x0300
+#define MUX_ENABLE_MSCL1 0x0304
+#define MUX_STAT_MSCL0 0x0400
+#define MUX_STAT_MSCL1 0x0404
+#define DIV_MSCL 0x0600
+#define DIV_STAT_MSCL 0x0700
+#define ENABLE_ACLK_MSCL 0x0800
+#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
+#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
+#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
+#define ENABLE_PCLK_MSCL 0x0900
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
+#define ENABLE_SCLK_MSCL 0x0a00
+#define ENABLE_IP_MSCL0 0x0b00
+#define ENABLE_IP_MSCL1 0x0b04
+#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
+#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
+#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
+
+static const unsigned long mscl_clk_regs[] __initconst = {
+ MUX_SEL_MSCL0,
+ MUX_SEL_MSCL1,
+ MUX_ENABLE_MSCL0,
+ MUX_ENABLE_MSCL1,
+ DIV_MSCL,
+ ENABLE_ACLK_MSCL,
+ ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
+ ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
+ ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
+ ENABLE_PCLK_MSCL,
+ ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
+ ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
+ ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
+ ENABLE_SCLK_MSCL,
+ ENABLE_IP_MSCL0,
+ ENABLE_IP_MSCL1,
+ ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
+ ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
+ ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
+};
+
+/* list of all parent clock list */
+PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
+PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
+PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
+ "mout_aclk_mscl_400_user", };
+
+static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
+ /* MUX_SEL_MSCL0 */
+ MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
+ mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
+ MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
+ mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
+
+ /* MUX_SEL_MSCL1 */
+ MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
+ MUX_SEL_MSCL1, 0, 1),
+};
+
+static const struct samsung_div_clock mscl_div_clks[] __initconst = {
+ /* DIV_MSCL */
+ DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
+ DIV_MSCL, 0, 3),
+};
+
+static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_MSCL */
+ GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL, 9, 0, 0),
+ GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
+ "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
+ GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
+ "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
+ ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
+ ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL, 2, 0, 0),
+ GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL, 1, 0, 0),
+ GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL, 0, 0, 0),
+
+ /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
+ GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
+ "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
+ GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
+ "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
+ GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
+ ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MSCL */
+ GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 7, 0, 0),
+ GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 6, 0, 0),
+ GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 5, 0, 0),
+ GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 2, 0, 0),
+ GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 1, 0, 0),
+ GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL, 0, 0, 0),
+
+ /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
+ GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
+ GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
+ GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
+ ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_MSCL */
+ GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
+ CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info mscl_cmu_info __initconst = {
+ .mux_clks = mscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
+ .div_clks = mscl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
+ .gate_clks = mscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
+ .nr_clk_ids = MSCL_NR_CLK,
+ .clk_regs = mscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
+};
+
+static void __init exynos5433_cmu_mscl_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mscl_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
+ exynos5433_cmu_mscl_init);
+
+/*
+ * Register offset definitions for CMU_MFC
+ */
+#define MUX_SEL_MFC 0x0200
+#define MUX_ENABLE_MFC 0x0300
+#define MUX_STAT_MFC 0x0400
+#define DIV_MFC 0x0600
+#define DIV_STAT_MFC 0x0700
+#define ENABLE_ACLK_MFC 0x0800
+#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
+#define ENABLE_PCLK_MFC 0x0900
+#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
+#define ENABLE_IP_MFC0 0x0b00
+#define ENABLE_IP_MFC1 0x0b04
+#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
+
+static const unsigned long mfc_clk_regs[] __initconst = {
+ MUX_SEL_MFC,
+ MUX_ENABLE_MFC,
+ DIV_MFC,
+ ENABLE_ACLK_MFC,
+ ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
+ ENABLE_PCLK_MFC,
+ ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
+ ENABLE_IP_MFC0,
+ ENABLE_IP_MFC1,
+ ENABLE_IP_MFC_SECURE_SMMU_MFC,
+};
+
+PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
+
+static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
+ /* MUX_SEL_MFC */
+ MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
+ mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
+};
+
+static const struct samsung_div_clock mfc_div_clks[] __initconst = {
+ /* DIV_MFC */
+ DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
+ DIV_MFC, 0, 2),
+};
+
+static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_MFC */
+ GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC, 6, 0, 0),
+ GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC, 5, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
+ ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
+ ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC, 0, 0, 0),
+
+ /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
+ GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
+ ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MFC */
+ GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
+ ENABLE_PCLK_MFC, 4, 0, 0),
+ GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
+ ENABLE_PCLK_MFC, 3, 0, 0),
+ GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
+ ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
+ ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
+ ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
+ GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
+ ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
+ ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
+ 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info mfc_cmu_info __initconst = {
+ .mux_clks = mfc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
+ .div_clks = mfc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
+ .gate_clks = mfc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
+ .nr_clk_ids = MFC_NR_CLK,
+ .clk_regs = mfc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
+};
+
+static void __init exynos5433_cmu_mfc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mfc_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
+ exynos5433_cmu_mfc_init);
+
+/*
+ * Register offset definitions for CMU_HEVC
+ */
+#define MUX_SEL_HEVC 0x0200
+#define MUX_ENABLE_HEVC 0x0300
+#define MUX_STAT_HEVC 0x0400
+#define DIV_HEVC 0x0600
+#define DIV_STAT_HEVC 0x0700
+#define ENABLE_ACLK_HEVC 0x0800
+#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
+#define ENABLE_PCLK_HEVC 0x0900
+#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
+#define ENABLE_IP_HEVC0 0x0b00
+#define ENABLE_IP_HEVC1 0x0b04
+#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
+
+static const unsigned long hevc_clk_regs[] __initconst = {
+ MUX_SEL_HEVC,
+ MUX_ENABLE_HEVC,
+ DIV_HEVC,
+ ENABLE_ACLK_HEVC,
+ ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
+ ENABLE_PCLK_HEVC,
+ ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
+ ENABLE_IP_HEVC0,
+ ENABLE_IP_HEVC1,
+ ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
+};
+
+PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
+
+static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
+ /* MUX_SEL_HEVC */
+ MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
+ mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
+};
+
+static const struct samsung_div_clock hevc_div_clks[] __initconst = {
+ /* DIV_HEVC */
+ DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
+ DIV_HEVC, 0, 2),
+};
+
+static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_HEVC */
+ GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC, 6, 0, 0),
+ GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC, 5, 0, 0),
+ GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
+ ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
+ ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC, 0, 0, 0),
+
+ /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
+ GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
+ "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
+ "mout_aclk_hevc_400_user",
+ ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_HEVC */
+ GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC, 4, 0, 0),
+ GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC, 3, 0, 0),
+ GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
+ GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
+ ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
+ 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info hevc_cmu_info __initconst = {
+ .mux_clks = hevc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
+ .div_clks = hevc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
+ .gate_clks = hevc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
+ .nr_clk_ids = HEVC_NR_CLK,
+ .clk_regs = hevc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
+};
+
+static void __init exynos5433_cmu_hevc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &hevc_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
+ exynos5433_cmu_hevc_init);
+
+/*
+ * Register offset definitions for CMU_ISP
+ */
+#define MUX_SEL_ISP 0x0200
+#define MUX_ENABLE_ISP 0x0300
+#define MUX_STAT_ISP 0x0400
+#define DIV_ISP 0x0600
+#define DIV_STAT_ISP 0x0700
+#define ENABLE_ACLK_ISP0 0x0800
+#define ENABLE_ACLK_ISP1 0x0804
+#define ENABLE_ACLK_ISP2 0x0808
+#define ENABLE_PCLK_ISP 0x0900
+#define ENABLE_SCLK_ISP 0x0a00
+#define ENABLE_IP_ISP0 0x0b00
+#define ENABLE_IP_ISP1 0x0b04
+#define ENABLE_IP_ISP2 0x0b08
+#define ENABLE_IP_ISP3 0x0b0c
+
+static const unsigned long isp_clk_regs[] __initconst = {
+ MUX_SEL_ISP,
+ MUX_ENABLE_ISP,
+ DIV_ISP,
+ ENABLE_ACLK_ISP0,
+ ENABLE_ACLK_ISP1,
+ ENABLE_ACLK_ISP2,
+ ENABLE_PCLK_ISP,
+ ENABLE_SCLK_ISP,
+ ENABLE_IP_ISP0,
+ ENABLE_IP_ISP1,
+ ENABLE_IP_ISP2,
+ ENABLE_IP_ISP3,
+};
+
+PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
+PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
+
+static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
+ /* MUX_SEL_ISP */
+ MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
+ mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
+ MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
+ mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
+};
+
+static const struct samsung_div_clock isp_div_clks[] __initconst = {
+ /* DIV_ISP */
+ DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
+ "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
+ DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
+ DIV_ISP, 8, 3),
+ DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
+ "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
+ DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
+ "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
+};
+
+static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_ISP0 */
+ GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP0, 5, 0, 0),
+ GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP0, 4, 0, 0),
+ GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
+ ENABLE_ACLK_ISP0, 3, 0, 0),
+ GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP0, 2, 0, 0),
+ GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP0, 1, 0, 0),
+ GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP0, 0, 0, 0),
+
+ /* ENABLE_ACLK_ISP1 */
+ GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
+ "div_pclk_isp", ENABLE_ACLK_ISP1,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
+ "div_pclk_isp", ENABLE_ACLK_ISP1,
+ 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
+ "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
+ "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
+ "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
+ "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
+ ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
+ ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
+ "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
+ 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
+ "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_ISP2 */
+ GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+ 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
+ "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
+ ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_ISP */
+ GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
+ ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
+ ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
+ ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
+ ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
+ "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
+ ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
+ ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
+ ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
+ ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
+ ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_ISP */
+ GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
+ "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
+ 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
+ "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
+ 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
+ "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
+ "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
+ "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
+ "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+ 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info isp_cmu_info __initconst = {
+ .mux_clks = isp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
+ .div_clks = isp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(isp_div_clks),
+ .gate_clks = isp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
+ .nr_clk_ids = ISP_NR_CLK,
+ .clk_regs = isp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
+};
+
+static void __init exynos5433_cmu_isp_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &isp_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
+ exynos5433_cmu_isp_init);
+
+/*
+ * Register offset definitions for CMU_CAM0
+ */
+#define MUX_SEL_CAM00 0x0200
+#define MUX_SEL_CAM01 0x0204
+#define MUX_SEL_CAM02 0x0208
+#define MUX_SEL_CAM03 0x020c
+#define MUX_SEL_CAM04 0x0210
+#define MUX_ENABLE_CAM00 0x0300
+#define MUX_ENABLE_CAM01 0x0304
+#define MUX_ENABLE_CAM02 0x0308
+#define MUX_ENABLE_CAM03 0x030c
+#define MUX_ENABLE_CAM04 0x0310
+#define MUX_STAT_CAM00 0x0400
+#define MUX_STAT_CAM01 0x0404
+#define MUX_STAT_CAM02 0x0408
+#define MUX_STAT_CAM03 0x040c
+#define MUX_STAT_CAM04 0x0410
+#define MUX_IGNORE_CAM01 0x0504
+#define DIV_CAM00 0x0600
+#define DIV_CAM01 0x0604
+#define DIV_CAM02 0x0608
+#define DIV_CAM03 0x060c
+#define DIV_STAT_CAM00 0x0700
+#define DIV_STAT_CAM01 0x0704
+#define DIV_STAT_CAM02 0x0708
+#define DIV_STAT_CAM03 0x070c
+#define ENABLE_ACLK_CAM00 0X0800
+#define ENABLE_ACLK_CAM01 0X0804
+#define ENABLE_ACLK_CAM02 0X0808
+#define ENABLE_PCLK_CAM0 0X0900
+#define ENABLE_SCLK_CAM0 0X0a00
+#define ENABLE_IP_CAM00 0X0b00
+#define ENABLE_IP_CAM01 0X0b04
+#define ENABLE_IP_CAM02 0X0b08
+#define ENABLE_IP_CAM03 0X0b0C
+
+static const unsigned long cam0_clk_regs[] __initconst = {
+ MUX_SEL_CAM00,
+ MUX_SEL_CAM01,
+ MUX_SEL_CAM02,
+ MUX_SEL_CAM03,
+ MUX_SEL_CAM04,
+ MUX_ENABLE_CAM00,
+ MUX_ENABLE_CAM01,
+ MUX_ENABLE_CAM02,
+ MUX_ENABLE_CAM03,
+ MUX_ENABLE_CAM04,
+ MUX_IGNORE_CAM01,
+ DIV_CAM00,
+ DIV_CAM01,
+ DIV_CAM02,
+ DIV_CAM03,
+ ENABLE_ACLK_CAM00,
+ ENABLE_ACLK_CAM01,
+ ENABLE_ACLK_CAM02,
+ ENABLE_PCLK_CAM0,
+ ENABLE_SCLK_CAM0,
+ ENABLE_IP_CAM00,
+ ENABLE_IP_CAM01,
+ ENABLE_IP_CAM02,
+ ENABLE_IP_CAM03,
+};
+PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
+PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
+PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
+
+PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
+ "phyclk_rxbyteclkhs0_s4_phy", };
+PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
+ "phyclk_rxbyteclkhs0_s2a_phy", };
+
+PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
+ "mout_aclk_cam0_333_user", };
+
+PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
+ "mout_aclk_cam0_333_user" };
+PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk-cam0_400_user", };
+PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+
+PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
+ "div_pclk_lite_d", };
+PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
+ "div_pclk_pixelasync_lite_c", };
+PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
+ "div_pclk_lite_b", };
+PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
+ "mout_aclk_cam0_333_user", };
+PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
+ "mout_sclk_pixelasync_lite_c_init_a",
+ "mout_aclk_cam0_400_user", };
+PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
+ "mout_aclk_cam0_552_user",
+ "mout_aclk_cam0_400_user", };
+
+static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
+ FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
+ NULL, 0, 100000000),
+ FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
+ NULL, 0, 100000000),
+};
+
+static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
+ /* MUX_SEL_CAM00 */
+ MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
+ mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
+ MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
+ mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
+ MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
+ mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
+
+ /* MUX_SEL_CAM01 */
+ MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
+ "mout_phyclk_rxbyteclkhs0_s4_user",
+ mout_phyclk_rxbyteclkhs0_s4_user_p,
+ MUX_SEL_CAM01, 4, 1),
+ MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
+ "mout_phyclk_rxbyteclkhs0_s2a_user",
+ mout_phyclk_rxbyteclkhs0_s2a_user_p,
+ MUX_SEL_CAM01, 0, 1),
+
+ /* MUX_SEL_CAM02 */
+ MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
+ MUX_SEL_CAM02, 24, 1),
+ MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
+ MUX_SEL_CAM02, 20, 1),
+ MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
+ MUX_SEL_CAM02, 16, 1),
+ MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
+ MUX_SEL_CAM02, 12, 1),
+ MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
+ MUX_SEL_CAM02, 8, 1),
+ MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
+ MUX_SEL_CAM02, 4, 1),
+ MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
+ MUX_SEL_CAM02, 0, 1),
+
+ /* MUX_SEL_CAM03 */
+ MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
+ MUX_SEL_CAM03, 28, 1),
+ MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
+ MUX_SEL_CAM03, 24, 1),
+ MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
+ MUX_SEL_CAM03, 20, 1),
+ MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
+ MUX_SEL_CAM03, 16, 1),
+ MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
+ MUX_SEL_CAM03, 12, 1),
+ MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
+ MUX_SEL_CAM03, 8, 1),
+ MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
+ MUX_SEL_CAM03, 4, 1),
+ MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
+ MUX_SEL_CAM03, 0, 1),
+
+ /* MUX_SEL_CAM04 */
+ MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
+ mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
+ MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
+ mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
+ MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
+ mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
+ MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
+ mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
+ MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
+ mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
+ MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
+ "mout_sclk_pixelasync_lite_c_init_b",
+ mout_sclk_pixelasync_lite_c_init_b_p,
+ MUX_SEL_CAM04, 4, 1),
+ MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
+ "mout_sclk_pixelasync_lite_c_init_a",
+ mout_sclk_pixelasync_lite_c_init_a_p,
+ MUX_SEL_CAM04, 0, 1),
+};
+
+static const struct samsung_div_clock cam0_div_clks[] __initconst = {
+ /* DIV_CAM00 */
+ DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
+ DIV_CAM00, 8, 2),
+ DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
+ DIV_CAM00, 4, 3),
+ DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
+ "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
+
+ /* DIV_CAM01 */
+ DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
+ DIV_CAM01, 20, 2),
+ DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
+ DIV_CAM01, 16, 3),
+ DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
+ DIV_CAM01, 12, 2),
+ DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
+ DIV_CAM01, 8, 3),
+ DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
+ DIV_CAM01, 4, 2),
+ DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
+ DIV_CAM01, 0, 3),
+
+ /* DIV_CAM02 */
+ DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
+ DIV_CAM02, 20, 3),
+ DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
+ DIV_CAM02, 16, 3),
+ DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
+ DIV_CAM02, 12, 2),
+ DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
+ DIV_CAM02, 8, 3),
+ DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
+ DIV_CAM02, 4, 2),
+ DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
+ DIV_CAM02, 0, 3),
+
+ /* DIV_CAM03 */
+ DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
+ "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
+ DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
+ "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
+ DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
+ "div_sclk_pixelasync_lite_c_init",
+ "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
+};
+
+static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_CAM00 */
+ GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
+ 6, 0, 0),
+ GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
+ 5, 0, 0),
+ GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
+ 4, 0, 0),
+ GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
+ 3, 0, 0),
+ GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
+ ENABLE_ACLK_CAM00, 2, 0, 0),
+ GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
+ ENABLE_ACLK_CAM00, 1, 0, 0),
+ GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
+ ENABLE_ACLK_CAM00, 0, 0, 0),
+
+ /* ENABLE_ACLK_CAM01 */
+ GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
+ ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
+ ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
+ ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
+ ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
+ ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
+ "div_pclk_lite_d", ENABLE_ACLK_CAM01,
+ 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
+ "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
+ "div_pclk_lite_b", ENABLE_ACLK_CAM01,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
+ "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+ 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
+ "div_pclk_lite_a", ENABLE_ACLK_CAM01,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
+ "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
+ "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
+ "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
+ "div_aclk_3aa1", ENABLE_ACLK_CAM01,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
+ "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
+ "div_aclk_3aa0", ENABLE_ACLK_CAM01,
+ 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
+ "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
+ "div_aclk_lite_d", ENABLE_ACLK_CAM01,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
+ "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
+ "div_aclk_lite_b", ENABLE_ACLK_CAM01,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
+ "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
+ "div_aclk_lite_a", ENABLE_ACLK_CAM01,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
+ "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
+ 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
+ ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
+ ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
+ ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
+ ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_CAM02 */
+ GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
+ ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_CAM0 */
+ GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
+ "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
+ "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
+ 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
+ "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
+ ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
+ "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
+ 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
+ ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
+ ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
+ ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
+ ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
+ ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
+ ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_CAM0 */
+ GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
+ "mout_phyclk_rxbyteclkhs0_s4_user",
+ ENABLE_SCLK_CAM0, 8, 0, 0),
+ GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
+ "mout_phyclk_rxbyteclkhs0_s2a_user",
+ ENABLE_SCLK_CAM0, 7, 0, 0),
+ GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
+ "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
+ "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
+ "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
+ "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
+ "div_sclk_pixelasync_lite_c",
+ ENABLE_SCLK_CAM0, 2, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
+ "div_sclk_pixelasync_lite_c_init",
+ ENABLE_SCLK_CAM0, 1, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
+ "div_sclk_pixelasync_lite_c",
+ ENABLE_SCLK_CAM0, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info cam0_cmu_info __initconst = {
+ .mux_clks = cam0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
+ .div_clks = cam0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
+ .gate_clks = cam0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
+ .fixed_clks = cam0_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
+ .nr_clk_ids = CAM0_NR_CLK,
+ .clk_regs = cam0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
+};
+
+static void __init exynos5433_cmu_cam0_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cam0_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
+ exynos5433_cmu_cam0_init);
+
+/*
+ * Register offset definitions for CMU_CAM1
+ */
+#define MUX_SEL_CAM10 0x0200
+#define MUX_SEL_CAM11 0x0204
+#define MUX_SEL_CAM12 0x0208
+#define MUX_ENABLE_CAM10 0x0300
+#define MUX_ENABLE_CAM11 0x0304
+#define MUX_ENABLE_CAM12 0x0308
+#define MUX_STAT_CAM10 0x0400
+#define MUX_STAT_CAM11 0x0404
+#define MUX_STAT_CAM12 0x0408
+#define MUX_IGNORE_CAM11 0x0504
+#define DIV_CAM10 0x0600
+#define DIV_CAM11 0x0604
+#define DIV_STAT_CAM10 0x0700
+#define DIV_STAT_CAM11 0x0704
+#define ENABLE_ACLK_CAM10 0X0800
+#define ENABLE_ACLK_CAM11 0X0804
+#define ENABLE_ACLK_CAM12 0X0808
+#define ENABLE_PCLK_CAM1 0X0900
+#define ENABLE_SCLK_CAM1 0X0a00
+#define ENABLE_IP_CAM10 0X0b00
+#define ENABLE_IP_CAM11 0X0b04
+#define ENABLE_IP_CAM12 0X0b08
+
+static const unsigned long cam1_clk_regs[] __initconst = {
+ MUX_SEL_CAM10,
+ MUX_SEL_CAM11,
+ MUX_SEL_CAM12,
+ MUX_ENABLE_CAM10,
+ MUX_ENABLE_CAM11,
+ MUX_ENABLE_CAM12,
+ MUX_IGNORE_CAM11,
+ DIV_CAM10,
+ DIV_CAM11,
+ ENABLE_ACLK_CAM10,
+ ENABLE_ACLK_CAM11,
+ ENABLE_ACLK_CAM12,
+ ENABLE_PCLK_CAM1,
+ ENABLE_SCLK_CAM1,
+ ENABLE_IP_CAM10,
+ ENABLE_IP_CAM11,
+ ENABLE_IP_CAM12,
+};
+
+PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
+PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
+PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
+
+PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
+PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
+PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
+
+PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
+ "phyclk_rxbyteclkhs0_s2b_phy", };
+
+PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
+ "mout_aclk_cam1_333_user", };
+PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
+ "mout_aclk_cam1_400_user", };
+
+PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
+ "mout_aclk_cam1_333_user", };
+PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
+ "mout_aclk_cam1_400_user", };
+
+PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
+ "mout_aclk_cam1_333_user", };
+PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
+ "mout_aclk_cam1_400_user", };
+
+static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
+ FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
+ 0, 100000000),
+};
+
+static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
+ /* MUX_SEL_CAM10 */
+ MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
+ mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
+ mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
+ mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
+ mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
+ mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
+ MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
+ mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
+
+ /* MUX_SEL_CAM11 */
+ MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
+ "mout_phyclk_rxbyteclkhs0_s2b_user",
+ mout_phyclk_rxbyteclkhs0_s2b_user_p,
+ MUX_SEL_CAM11, 0, 1),
+
+ /* MUX_SEL_CAM12 */
+ MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
+ MUX_SEL_CAM12, 20, 1),
+ MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
+ MUX_SEL_CAM12, 16, 1),
+ MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
+ MUX_SEL_CAM12, 12, 1),
+ MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
+ MUX_SEL_CAM12, 8, 1),
+ MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
+ MUX_SEL_CAM12, 4, 1),
+ MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
+ MUX_SEL_CAM12, 0, 1),
+};
+
+static const struct samsung_div_clock cam1_div_clks[] __initconst = {
+ /* DIV_CAM10 */
+ DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
+ "div_pclk_cam1_83", DIV_CAM10, 16, 2),
+ DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
+ "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
+ DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
+ "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
+ DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
+ "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
+ DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
+ DIV_CAM10, 0, 3),
+
+ /* DIV_CAM11 */
+ DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
+ DIV_CAM11, 16, 3),
+ DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
+ DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
+ DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
+ DIV_CAM11, 4, 2),
+ DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
+ DIV_CAM11, 0, 3),
+};
+
+static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_CAM10 */
+ GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
+ ENABLE_ACLK_CAM10, 4, 0, 0),
+ GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
+ ENABLE_ACLK_CAM10, 3, 0, 0),
+ GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
+ ENABLE_ACLK_CAM10, 1, 0, 0),
+ GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
+ ENABLE_ACLK_CAM10, 0, 0, 0),
+
+ /* ENABLE_ACLK_CAM11 */
+ GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
+ ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
+ ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
+ "div_pclk_lite_c", ENABLE_ACLK_CAM11,
+ 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
+ "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
+ 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
+ "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
+ 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
+ "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
+ 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+ 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
+ "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
+ 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+ 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+ 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+ 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+ 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
+ ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
+ 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
+ "div_aclk_lite_c", ENABLE_ACLK_CAM11,
+ 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
+ ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
+ ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
+ 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
+ ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
+ ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
+ ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
+ ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
+ ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
+ ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
+ ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_ACLK_CAM12 */
+ GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+ 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+ 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
+ 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
+ "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
+ 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
+ ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
+ "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_CAM1 */
+ GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
+ ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
+ ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
+ ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
+ ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
+ "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
+ 20, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
+ "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
+ 19, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
+ "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
+ 17, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
+ "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
+ 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
+ ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
+ ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
+ ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
+ ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_SCLK_CAM1 */
+ GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
+ 15, 0, 0),
+ GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
+ 14, 0, 0),
+ GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
+ 13, 0, 0),
+ GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
+ 12, 0, 0),
+ GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
+ "mout_phyclk_rxbyteclkhs0_s2b_user",
+ ENABLE_SCLK_CAM1, 11, 0, 0),
+ GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
+ ENABLE_SCLK_CAM1, 10, 0, 0),
+ GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
+ ENABLE_SCLK_CAM1, 9, 0, 0),
+ GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
+ ENABLE_SCLK_CAM1, 7, 0, 0),
+ GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
+ ENABLE_SCLK_CAM1, 6, 0, 0),
+ GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
+ ENABLE_SCLK_CAM1, 5, 0, 0),
+ GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
+ ENABLE_SCLK_CAM1, 4, 0, 0),
+ GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
+ ENABLE_SCLK_CAM1, 3, 0, 0),
+ GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
+ ENABLE_SCLK_CAM1, 2, 0, 0),
+ GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
+ ENABLE_SCLK_CAM1, 1, 0, 0),
+ GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
+ ENABLE_SCLK_CAM1, 0, 0, 0),
+};
+
+static const struct samsung_cmu_info cam1_cmu_info __initconst = {
+ .mux_clks = cam1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
+ .div_clks = cam1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
+ .gate_clks = cam1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
+ .fixed_clks = cam1_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
+ .nr_clk_ids = CAM1_NR_CLK,
+ .clk_regs = cam1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
+};
+
+static void __init exynos5433_cmu_cam1_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cam1_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
+ exynos5433_cmu_cam1_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5440 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5440.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define CLKEN_OV_VAL 0xf8
+#define CPU_CLK_STATUS 0xfc
+#define MISC_DOUT1 0x558
+
+static void __iomem *reg_base;
+
+/* parent clock name list */
+PNAME(mout_armclk_p) = { "cplla", "cpllb" };
+PNAME(mout_spi_p) = { "div125", "div200" };
+
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+ FRATE(0, "xtal", NULL, 0, 0),
+};
+
+/* fixed rate clocks */
+static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = {
+ FRATE(0, "ppll", NULL, 0, 1000000000),
+ FRATE(0, "usb_phy0", NULL, 0, 60000000),
+ FRATE(0, "usb_phy1", NULL, 0, 60000000),
+ FRATE(0, "usb_ohci12", NULL, 0, 12000000),
+ FRATE(0, "usb_ohci48", NULL, 0, 48000000),
+};
+
+/* fixed factor clocks */
+static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "div250", "ppll", 1, 4, 0),
+ FFACTOR(0, "div200", "ppll", 1, 5, 0),
+ FFACTOR(0, "div125", "div250", 1, 2, 0),
+};
+
+/* mux clocks */
+static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
+ MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
+ MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
+ CPU_CLK_STATUS, 0, 1, "armclk"),
+};
+
+/* divider clocks */
+static const struct samsung_div_clock exynos5440_div_clks[] __initconst = {
+ DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
+};
+
+/* gate clocks */
+static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = {
+ GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
+ GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
+ GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
+ GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
+ GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
+ GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
+ GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
+ GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
+ GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
+ GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
+ GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
+ GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
+ GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
+ GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
+ GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
+ GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
+ GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
+ GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
+ GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
+ GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
+};
+
+static const struct of_device_id ext_clk_match[] __initconst = {
+ { .compatible = "samsung,clock-xtal", .data = (void *)0, },
+ {},
+};
+
+static int exynos5440_clk_restart_notify(struct notifier_block *this,
+ unsigned long code, void *unused)
+{
+ u32 val, status;
+
+ status = readl_relaxed(reg_base + 0xbc);
+ val = readl_relaxed(reg_base + 0xcc);
+ val = (val & 0xffff0000) | (status & 0xffff);
+ writel_relaxed(val, reg_base + 0xcc);
+
+ return NOTIFY_DONE;
+}
+
+/*
+ * Exynos5440 Clock restart notifier, handles restart functionality
+ */
+static struct notifier_block exynos5440_clk_restart_handler = {
+ .notifier_call = exynos5440_clk_restart_notify,
+ .priority = 128,
+};
+
+static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
+ PLL(pll_2550x, CLK_CPLLA, "cplla", "xtal", 0, 0x4c, NULL),
+ PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
+};
+
+/* register exynos5440 clocks */
+static void __init exynos5440_clk_init(struct device_node *np)
+{
+ struct samsung_clk_provider *ctx;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: failed to map clock controller registers,"
+ " aborting clock initialization\n", __func__);
+ return;
+ }
+
+ ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
+
+ samsung_clk_register_pll(ctx, exynos5440_plls,
+ ARRAY_SIZE(exynos5440_plls), ctx->reg_base);
+
+ samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
+ ARRAY_SIZE(exynos5440_fixed_rate_clks));
+ samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
+ ARRAY_SIZE(exynos5440_fixed_factor_clks));
+ samsung_clk_register_mux(ctx, exynos5440_mux_clks,
+ ARRAY_SIZE(exynos5440_mux_clks));
+ samsung_clk_register_div(ctx, exynos5440_div_clks,
+ ARRAY_SIZE(exynos5440_div_clks));
+ samsung_clk_register_gate(ctx, exynos5440_gate_clks,
+ ARRAY_SIZE(exynos5440_gate_clks));
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ if (register_restart_handler(&exynos5440_clk_restart_handler))
+ pr_warn("exynos5440 clock can't register restart handler\n");
+
+ pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
+ pr_info("exynos5440 clock initialization complete\n");
+}
+CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include "clk.h"
+#include <dt-bindings/clock/exynos7-clk.h>
+
+/* Register Offset definitions for CMU_TOPC (0x10570000) */
+#define CC_PLL_LOCK 0x0000
+#define BUS0_PLL_LOCK 0x0004
+#define BUS1_DPLL_LOCK 0x0008
+#define MFC_PLL_LOCK 0x000C
+#define AUD_PLL_LOCK 0x0010
+#define CC_PLL_CON0 0x0100
+#define BUS0_PLL_CON0 0x0110
+#define BUS1_DPLL_CON0 0x0120
+#define MFC_PLL_CON0 0x0130
+#define AUD_PLL_CON0 0x0140
+#define MUX_SEL_TOPC0 0x0200
+#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC2 0x0208
+#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC0 0x0600
+#define DIV_TOPC1 0x0604
+#define DIV_TOPC3 0x060C
+#define ENABLE_ACLK_TOPC0 0x0800
+#define ENABLE_ACLK_TOPC1 0x0804
+#define ENABLE_SCLK_TOPC1 0x0A04
+
+static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
+ FFACTOR(0, "ffac_topc_bus0_pll_div4",
+ "ffac_topc_bus0_pll_div2", 1, 2, 0),
+ FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
+ FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
+ FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
+PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
+PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
+PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
+PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
+
+PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
+ "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
+ "mout_topc_mfc_pll_half" };
+
+PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
+ "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
+PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
+ "ffac_topc_bus1_pll_div2"};
+PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
+ "ffac_topc_cc_pll_div2"};
+PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
+ "ffac_topc_mfc_pll_div2"};
+
+
+PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
+ "ffac_topc_bus0_pll_div2"};
+
+static const unsigned long topc_clk_regs[] __initconst = {
+ CC_PLL_LOCK,
+ BUS0_PLL_LOCK,
+ BUS1_DPLL_LOCK,
+ MFC_PLL_LOCK,
+ AUD_PLL_LOCK,
+ CC_PLL_CON0,
+ BUS0_PLL_CON0,
+ BUS1_DPLL_CON0,
+ MFC_PLL_CON0,
+ AUD_PLL_CON0,
+ MUX_SEL_TOPC0,
+ MUX_SEL_TOPC1,
+ MUX_SEL_TOPC2,
+ MUX_SEL_TOPC3,
+ DIV_TOPC0,
+ DIV_TOPC1,
+ DIV_TOPC3,
+};
+
+static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
+ MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
+ MUX_SEL_TOPC0, 0, 1),
+ MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
+ MUX_SEL_TOPC0, 4, 1),
+ MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
+ MUX_SEL_TOPC0, 8, 1),
+ MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
+ MUX_SEL_TOPC0, 12, 1),
+ MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
+ MUX_SEL_TOPC0, 16, 2),
+ MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
+ MUX_SEL_TOPC0, 20, 1),
+ MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
+ MUX_SEL_TOPC0, 24, 1),
+ MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
+ MUX_SEL_TOPC0, 28, 1),
+
+ MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
+ MUX_SEL_TOPC1, 0, 1),
+ MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
+ MUX_SEL_TOPC1, 16, 1),
+
+ MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
+ MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
+ MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
+};
+
+static const struct samsung_div_clock topc_div_clks[] __initconst = {
+ DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+ DIV_TOPC0, 4, 4),
+
+ DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
+ DIV_TOPC1, 20, 4),
+ DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
+ DIV_TOPC1, 24, 4),
+
+ DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
+ DIV_TOPC3, 0, 4),
+ DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
+ DIV_TOPC3, 8, 4),
+ DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
+ DIV_TOPC3, 12, 4),
+ DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
+ DIV_TOPC3, 16, 4),
+ DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
+ DIV_TOPC3, 28, 4),
+};
+
+static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
+ PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
+ {},
+};
+
+static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
+ GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
+ ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
+
+ GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
+ ENABLE_ACLK_TOPC1, 20, 0, 0),
+
+ GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
+ ENABLE_ACLK_TOPC1, 24, 0, 0),
+
+ GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
+ ENABLE_SCLK_TOPC1, 20, 0, 0),
+ GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
+ ENABLE_SCLK_TOPC1, 17, 0, 0),
+ GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
+ ENABLE_SCLK_TOPC1, 16, 0, 0),
+ GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
+ ENABLE_SCLK_TOPC1, 13, 0, 0),
+ GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
+ ENABLE_SCLK_TOPC1, 12, 0, 0),
+ GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
+ ENABLE_SCLK_TOPC1, 5, 0, 0),
+ GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
+ ENABLE_SCLK_TOPC1, 4, 0, 0),
+ GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
+ ENABLE_SCLK_TOPC1, 1, 0, 0),
+ GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
+ ENABLE_SCLK_TOPC1, 0, 0, 0),
+};
+
+static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
+ PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
+ BUS0_PLL_CON0, NULL),
+ PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
+ CC_PLL_CON0, NULL),
+ PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
+ BUS1_DPLL_CON0, NULL),
+ PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
+ MFC_PLL_CON0, NULL),
+ PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
+ AUD_PLL_CON0, pll1460x_24mhz_tbl),
+};
+
+static const struct samsung_cmu_info topc_cmu_info __initconst = {
+ .pll_clks = topc_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
+ .mux_clks = topc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
+ .div_clks = topc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(topc_div_clks),
+ .gate_clks = topc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
+ .fixed_factor_clks = topc_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
+ .nr_clk_ids = TOPC_NR_CLK,
+ .clk_regs = topc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
+};
+
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &topc_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
+ exynos7_clk_topc_init);
+
+/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
+#define MUX_SEL_TOP00 0x0200
+#define MUX_SEL_TOP01 0x0204
+#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC0 0x0230
+#define MUX_SEL_TOP0_PERIC1 0x0234
+#define MUX_SEL_TOP0_PERIC2 0x0238
+#define MUX_SEL_TOP0_PERIC3 0x023C
+#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC0 0x0630
+#define DIV_TOP0_PERIC1 0x0634
+#define DIV_TOP0_PERIC2 0x0638
+#define DIV_TOP0_PERIC3 0x063C
+#define ENABLE_ACLK_TOP03 0x080C
+#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
+#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
+#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
+#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
+
+/* List of parent clocks for Muxes in CMU_TOP0 */
+PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
+PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
+PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
+PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
+PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
+
+PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
+ "ffac_top0_bus0_pll_div2"};
+PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
+ "ffac_top0_bus1_pll_div2"};
+PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
+ "ffac_top0_cc_pll_div2"};
+PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
+ "ffac_top0_mfc_pll_div2"};
+
+PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
+ "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
+ "mout_top0_mfc_pll_half"};
+PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
+ "ioclk_audiocdclk1", "ioclk_spdif_extclk",
+ "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
+ "mout_top0_bus1_pll_half"};
+PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
+ "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
+
+static const unsigned long top0_clk_regs[] __initconst = {
+ MUX_SEL_TOP00,
+ MUX_SEL_TOP01,
+ MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC0,
+ MUX_SEL_TOP0_PERIC1,
+ MUX_SEL_TOP0_PERIC2,
+ MUX_SEL_TOP0_PERIC3,
+ DIV_TOP03,
+ DIV_TOP0_PERIC0,
+ DIV_TOP0_PERIC1,
+ DIV_TOP0_PERIC2,
+ DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC0,
+ ENABLE_SCLK_TOP0_PERIC1,
+ ENABLE_SCLK_TOP0_PERIC2,
+ ENABLE_SCLK_TOP0_PERIC3,
+};
+
+static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
+ MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
+ MUX_SEL_TOP00, 0, 1),
+ MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
+ MUX_SEL_TOP00, 4, 1),
+ MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
+ MUX_SEL_TOP00, 8, 1),
+ MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
+ MUX_SEL_TOP00, 12, 1),
+ MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
+ MUX_SEL_TOP00, 16, 1),
+
+ MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
+ MUX_SEL_TOP01, 4, 1),
+ MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
+ MUX_SEL_TOP01, 8, 1),
+ MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
+ MUX_SEL_TOP01, 12, 1),
+ MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
+ MUX_SEL_TOP01, 16, 1),
+
+ MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
+ MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+
+ MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
+ MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
+ MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
+
+ MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+ MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+ MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+ MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
+ MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
+ MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
+ MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
+ MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+ MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
+};
+
+static const struct samsung_div_clock top0_div_clks[] __initconst = {
+ DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
+ DIV_TOP03, 12, 6),
+ DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
+ DIV_TOP03, 20, 6),
+
+ DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
+ DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
+ DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
+
+ DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
+ DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
+
+ DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
+ DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
+
+ DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
+ DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
+ DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
+ DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+ DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
+};
+
+static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
+ GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
+ ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
+ ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
+ ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
+ ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
+ ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
+ ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
+ ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
+ ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
+ ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
+ ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
+ ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
+ ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
+ ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+ GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
+ ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
+ 1, 2, 0),
+ FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
+ 1, 2, 0),
+ FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
+ FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
+};
+
+static const struct samsung_cmu_info top0_cmu_info __initconst = {
+ .mux_clks = top0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
+ .div_clks = top0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top0_div_clks),
+ .gate_clks = top0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
+ .fixed_factor_clks = top0_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
+ .nr_clk_ids = TOP0_NR_CLK,
+ .clk_regs = top0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
+};
+
+static void __init exynos7_clk_top0_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &top0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
+ exynos7_clk_top0_init);
+
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define MUX_SEL_TOP1_FSYS11 0x022C
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define DIV_TOP1_FSYS11 0x062C
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+#define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
+PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
+
+PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
+ "ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
+ "ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
+ "ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
+ "ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
+ "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
+ "mout_top1_mfc_pll_half"};
+
+static const unsigned long top1_clk_regs[] __initconst = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ MUX_SEL_TOP1_FSYS11,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ DIV_TOP1_FSYS11,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+ ENABLE_SCLK_TOP1_FSYS11,
+};
+
+static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
+ MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
+ MUX_SEL_TOP10, 4, 1),
+ MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
+ MUX_SEL_TOP10, 8, 1),
+ MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+ MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+ MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
+ MUX_SEL_TOP1_FSYS0, 0, 2),
+ MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
+ MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
+ MUX_SEL_TOP1_FSYS0, 28, 2),
+
+ MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
+ MUX_SEL_TOP1_FSYS1, 0, 2),
+ MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
+ MUX_SEL_TOP1_FSYS1, 16, 2),
+
+ MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
+ MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
+ MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
+ MUX_SEL_TOP1_FSYS11, 24, 2),
+};
+
+static const struct samsung_div_clock top1_div_clks[] __initconst = {
+ DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
+ DIV_TOP13, 24, 4),
+ DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
+ DIV_TOP13, 28, 4),
+
+ DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
+ "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
+
+ DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
+ "mout_sclk_ufsunipro20",
+ DIV_TOP1_FSYS1, 16, 6),
+
+ DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
+ DIV_TOP1_FSYS0, 16, 10),
+ DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
+ DIV_TOP1_FSYS0, 28, 4),
+
+ DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
+ DIV_TOP1_FSYS11, 0, 10),
+ DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
+ DIV_TOP1_FSYS11, 12, 10),
+
+ DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
+ "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
+};
+
+static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+ ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
+ ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
+
+ GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
+ ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
+ ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+ ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+ ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
+ ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
+ CLK_IS_CRITICAL, 0),
+ GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
+ ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
+ "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
+ 24, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
+ FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
+ 1, 2, 0),
+ FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
+ 1, 2, 0),
+ FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
+ FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
+};
+
+static const struct samsung_cmu_info top1_cmu_info __initconst = {
+ .mux_clks = top1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
+ .div_clks = top1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top1_div_clks),
+ .gate_clks = top1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
+ .fixed_factor_clks = top1_fixed_factor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
+ .nr_clk_ids = TOP1_NR_CLK,
+ .clk_regs = top1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &top1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+ exynos7_clk_top1_init);
+
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define MUX_SEL_CCORE 0x0200
+#define DIV_CCORE 0x0600
+#define ENABLE_ACLK_CCORE0 0x0800
+#define ENABLE_ACLK_CCORE1 0x0804
+#define ENABLE_PCLK_CCORE 0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
+
+static const unsigned long ccore_clk_regs[] __initconst = {
+ MUX_SEL_CCORE,
+ ENABLE_PCLK_CCORE,
+};
+
+static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
+ MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
+ MUX_SEL_CCORE, 1, 1),
+};
+
+static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
+ GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+ ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static const struct samsung_cmu_info ccore_cmu_info __initconst = {
+ .mux_clks = ccore_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
+ .gate_clks = ccore_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
+ .nr_clk_ids = CCORE_NR_CLK,
+ .clk_regs = ccore_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+ exynos7_clk_ccore_init);
+
+/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
+#define MUX_SEL_PERIC0 0x0200
+#define ENABLE_PCLK_PERIC0 0x0900
+#define ENABLE_SCLK_PERIC0 0x0A00
+
+/* List of parent clocks for Muxes in CMU_PERIC0 */
+PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
+PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
+
+static const unsigned long peric0_clk_regs[] __initconst = {
+ MUX_SEL_PERIC0,
+ ENABLE_PCLK_PERIC0,
+ ENABLE_SCLK_PERIC0,
+};
+
+static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
+ MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
+ MUX_SEL_PERIC0, 0, 1),
+ MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
+ MUX_SEL_PERIC0, 16, 1),
+};
+
+static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
+ GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
+ GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 20, 0, 0),
+ GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
+
+ GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
+ ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info peric0_cmu_info __initconst = {
+ .mux_clks = peric0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
+ .gate_clks = peric0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
+ .nr_clk_ids = PERIC0_NR_CLK,
+ .clk_regs = peric0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
+};
+
+static void __init exynos7_clk_peric0_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peric0_cmu_info);
+}
+
+/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
+#define MUX_SEL_PERIC10 0x0200
+#define MUX_SEL_PERIC11 0x0204
+#define MUX_SEL_PERIC12 0x0208
+#define ENABLE_PCLK_PERIC1 0x0900
+#define ENABLE_SCLK_PERIC10 0x0A00
+
+CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
+ exynos7_clk_peric0_init);
+
+/* List of parent clocks for Muxes in CMU_PERIC1 */
+PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
+PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
+
+static const unsigned long peric1_clk_regs[] __initconst = {
+ MUX_SEL_PERIC10,
+ MUX_SEL_PERIC11,
+ MUX_SEL_PERIC12,
+ ENABLE_PCLK_PERIC1,
+ ENABLE_SCLK_PERIC10,
+};
+
+static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
+ MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
+ MUX_SEL_PERIC10, 0, 1),
+
+ MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
+ MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
+ MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
+ MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
+ MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
+ MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
+ MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
+ MUX_SEL_PERIC11, 20, 1),
+ MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
+ MUX_SEL_PERIC11, 24, 1),
+ MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
+ MUX_SEL_PERIC11, 28, 1),
+};
+
+static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
+ GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
+ GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 9, 0, 0),
+ GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 10, 0, 0),
+ GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 11, 0, 0),
+ GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 12, 0, 0),
+ GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 13, 0, 0),
+ GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 14, 0, 0),
+ GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 15, 0, 0),
+ GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 16, 0, 0),
+ GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
+ GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 18, 0, 0),
+ GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 19, 0, 0),
+
+ GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
+ ENABLE_SCLK_PERIC10, 9, 0, 0),
+ GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
+ ENABLE_SCLK_PERIC10, 10, 0, 0),
+ GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
+ ENABLE_SCLK_PERIC10, 11, 0, 0),
+ GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
+ ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
+ ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
+ ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
+ ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
+ ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
+ ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
+ ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
+ ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info peric1_cmu_info __initconst = {
+ .mux_clks = peric1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
+ .gate_clks = peric1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
+ .nr_clk_ids = PERIC1_NR_CLK,
+ .clk_regs = peric1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
+};
+
+static void __init exynos7_clk_peric1_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peric1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
+ exynos7_clk_peric1_init);
+
+/* Register Offset definitions for CMU_PERIS (0x10040000) */
+#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
+
+static const unsigned long peris_clk_regs[] __initconst = {
+ MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
+ ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
+ ENABLE_SCLK_PERIS_SECURE_CHIPID,
+};
+
+static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
+ MUX(0, "mout_aclk_peris_66_user",
+ mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
+};
+
+static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
+ GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
+ GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
+ ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+ GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
+ ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
+};
+
+static const struct samsung_cmu_info peris_cmu_info __initconst = {
+ .mux_clks = peris_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
+ .gate_clks = peris_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
+ .nr_clk_ids = PERIS_NR_CLK,
+ .clk_regs = peris_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos7_clk_peris_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
+ exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define MUX_SEL_FSYS00 0x0200
+#define MUX_SEL_FSYS01 0x0204
+#define MUX_SEL_FSYS02 0x0208
+#define ENABLE_ACLK_FSYS00 0x0800
+#define ENABLE_ACLK_FSYS01 0x0804
+#define ENABLE_SCLK_FSYS01 0x0A04
+#define ENABLE_SCLK_FSYS02 0x0A08
+#define ENABLE_SCLK_FSYS04 0x0A10
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
+
+PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
+PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
+ "phyclk_usbdrd300_udrd30_phyclock" };
+PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
+ "phyclk_usbdrd300_udrd30_pipe_pclk" };
+
+/* fixed rate clocks used in the FSYS0 block */
+static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
+ FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
+ FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
+};
+
+static const unsigned long fsys0_clk_regs[] __initconst = {
+ MUX_SEL_FSYS00,
+ MUX_SEL_FSYS01,
+ MUX_SEL_FSYS02,
+ ENABLE_ACLK_FSYS00,
+ ENABLE_ACLK_FSYS01,
+ ENABLE_SCLK_FSYS01,
+ ENABLE_SCLK_FSYS02,
+ ENABLE_SCLK_FSYS04,
+};
+
+static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
+ MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
+ MUX_SEL_FSYS00, 24, 1),
+
+ MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
+ MUX_SEL_FSYS01, 24, 1),
+ MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
+ MUX_SEL_FSYS01, 28, 1),
+
+ MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+ mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
+ MUX_SEL_FSYS02, 24, 1),
+ MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+ mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
+ MUX_SEL_FSYS02, 28, 1),
+};
+
+static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
+ GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS00, 3, 0, 0),
+ GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS00, 4, 0, 0),
+ GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
+ "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS00, 19, 0, 0),
+
+ GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS01, 29, 0, 0),
+ GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS01, 31, 0, 0),
+
+ GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
+ "mout_sclk_usbdrd300_user",
+ ENABLE_SCLK_FSYS01, 4, 0, 0),
+ GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
+ ENABLE_SCLK_FSYS01, 8, 0, 0),
+
+ GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
+ "phyclk_usbdrd300_udrd30_pipe_pclk_user",
+ "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+ ENABLE_SCLK_FSYS02, 24, 0, 0),
+ GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
+ "phyclk_usbdrd300_udrd30_phyclk_user",
+ "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+ ENABLE_SCLK_FSYS02, 28, 0, 0),
+
+ GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
+ "fin_pll",
+ ENABLE_SCLK_FSYS04, 28, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
+ .fixed_clks = fixed_rate_clks_fsys0,
+ .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
+ .mux_clks = fsys0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
+ .gate_clks = fsys0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
+ .nr_clk_ids = FSYS0_NR_CLK,
+ .clk_regs = fsys0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &fsys0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+ exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define MUX_SEL_FSYS10 0x0200
+#define MUX_SEL_FSYS11 0x0204
+#define MUX_SEL_FSYS12 0x0208
+#define DIV_FSYS1 0x0600
+#define ENABLE_ACLK_FSYS1 0x0800
+#define ENABLE_PCLK_FSYS1 0x0900
+#define ENABLE_SCLK_FSYS11 0x0A04
+#define ENABLE_SCLK_FSYS12 0x0A08
+#define ENABLE_SCLK_FSYS13 0x0A0C
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
+PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
+ "sclk_phy_fsys1_26m" };
+PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
+PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
+PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
+PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
+PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
+
+/* fixed rate clocks used in the FSYS1 block */
+static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
+ FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
+ 0, 300000000),
+ FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
+ 0, 300000000),
+ FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
+ 0, 300000000),
+};
+
+static const unsigned long fsys1_clk_regs[] __initconst = {
+ MUX_SEL_FSYS10,
+ MUX_SEL_FSYS11,
+ MUX_SEL_FSYS12,
+ DIV_FSYS1,
+ ENABLE_ACLK_FSYS1,
+ ENABLE_PCLK_FSYS1,
+ ENABLE_SCLK_FSYS11,
+ ENABLE_SCLK_FSYS12,
+ ENABLE_SCLK_FSYS13,
+};
+
+static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
+ MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
+ mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
+ MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
+ MUX_SEL_FSYS10, 20, 2),
+ MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
+ MUX_SEL_FSYS10, 28, 1),
+
+ MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
+ MUX_SEL_FSYS11, 24, 1),
+ MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
+ MUX_SEL_FSYS11, 28, 1),
+ MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
+ MUX_SEL_FSYS11, 20, 1),
+
+ MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
+ mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
+ MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
+ mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
+ MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
+ mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
+};
+
+static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
+ DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
+ DIV_FSYS1, 0, 2),
+};
+
+static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
+ GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
+ "mout_sclk_ufsunipro20_user",
+ ENABLE_SCLK_FSYS11, 20, 0, 0),
+
+ GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
+ ENABLE_ACLK_FSYS1, 29, 0, 0),
+ GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
+ ENABLE_ACLK_FSYS1, 30, 0, 0),
+
+ GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
+ ENABLE_ACLK_FSYS1, 31, 0, 0),
+ GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
+ ENABLE_PCLK_FSYS1, 30, 0, 0),
+
+ GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
+ "mout_phyclk_ufs20_rx1_symbol_user",
+ ENABLE_SCLK_FSYS12, 16, 0, 0),
+ GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
+ "mout_phyclk_ufs20_rx0_symbol_user",
+ ENABLE_SCLK_FSYS12, 24, 0, 0),
+ GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
+ "mout_phyclk_ufs20_tx0_symbol_user",
+ ENABLE_SCLK_FSYS12, 28, 0, 0),
+
+ GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
+ "oscclk_phy_clkout_embedded_combo_phy",
+ "fin_pll",
+ ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
+
+ GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
+ "mout_fsys1_phyclk_sel1",
+ ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
+ .fixed_clks = fixed_rate_clks_fsys1,
+ .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
+ .mux_clks = fsys1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
+ .div_clks = fsys1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
+ .gate_clks = fsys1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
+ .nr_clk_ids = FSYS1_NR_CLK,
+ .clk_regs = fsys1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &fsys1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+ exynos7_clk_fsys1_init);
+
+#define MUX_SEL_MSCL 0x0200
+#define DIV_MSCL 0x0600
+#define ENABLE_ACLK_MSCL 0x0800
+#define ENABLE_PCLK_MSCL 0x0900
+
+/* List of parent clocks for Muxes in CMU_MSCL */
+PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
+
+static const unsigned long mscl_clk_regs[] __initconst = {
+ MUX_SEL_MSCL,
+ DIV_MSCL,
+ ENABLE_ACLK_MSCL,
+ ENABLE_PCLK_MSCL,
+};
+
+static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
+ MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
+ mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
+};
+static const struct samsung_div_clock mscl_div_clks[] __initconst = {
+ DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
+ DIV_MSCL, 0, 3),
+};
+static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
+
+ GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 31, 0, 0),
+ GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 30, 0, 0),
+ GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 29, 0, 0),
+ GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 28, 0, 0),
+ GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
+ "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 27, 0, 0),
+ GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
+ "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 26, 0, 0),
+ GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 25, 0, 0),
+ GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 24, 0, 0),
+ GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
+ "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 23, 0, 0),
+ GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 22, 0, 0),
+ GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 21, 0, 0),
+ GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 20, 0, 0),
+ GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 19, 0, 0),
+ GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 18, 0, 0),
+ GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 17, 0, 0),
+ GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 16, 0, 0),
+ GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
+ "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 15, 0, 0),
+ GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
+ "usermux_aclk_mscl_532",
+ ENABLE_ACLK_MSCL, 14, 0, 0),
+
+ GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 31, 0, 0),
+ GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 30, 0, 0),
+ GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 29, 0, 0),
+ GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 28, 0, 0),
+ GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 27, 0, 0),
+ GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 26, 0, 0),
+ GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 25, 0, 0),
+ GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 24, 0, 0),
+ GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 23, 0, 0),
+ GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 22, 0, 0),
+ GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 21, 0, 0),
+ GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
+ ENABLE_PCLK_MSCL, 20, 0, 0),
+};
+
+static const struct samsung_cmu_info mscl_cmu_info __initconst = {
+ .mux_clks = mscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
+ .div_clks = mscl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
+ .gate_clks = mscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
+ .nr_clk_ids = MSCL_NR_CLK,
+ .clk_regs = mscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
+};
+
+static void __init exynos7_clk_mscl_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &mscl_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
+ exynos7_clk_mscl_init);
+
+/* Register Offset definitions for CMU_AUD (0x114C0000) */
+#define MUX_SEL_AUD 0x0200
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define ENABLE_ACLK_AUD 0x0800
+#define ENABLE_PCLK_AUD 0x0900
+#define ENABLE_SCLK_AUD 0x0A00
+
+/*
+ * List of parent clocks for Muxes in CMU_AUD
+ */
+PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
+PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
+
+static const unsigned long aud_clk_regs[] __initconst = {
+ MUX_SEL_AUD,
+ DIV_AUD0,
+ DIV_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD,
+};
+
+static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
+ MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
+ MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
+ MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
+};
+
+static const struct samsung_div_clock aud_div_clks[] __initconst = {
+ DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
+ DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
+ DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
+
+ DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
+ DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
+ DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
+ DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
+ DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
+};
+
+static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
+ GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
+ ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
+ ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
+ GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
+ ENABLE_SCLK_AUD, 30, 0, 0),
+
+ GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
+ GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
+ GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
+ GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
+ GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
+ GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
+ GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
+ ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
+ GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
+ ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
+ GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
+
+ GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
+ GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
+ ENABLE_ACLK_AUD, 28, 0, 0),
+ GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
+};
+
+static const struct samsung_cmu_info aud_cmu_info __initconst = {
+ .mux_clks = aud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
+ .div_clks = aud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(aud_div_clks),
+ .gate_clks = aud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
+ .nr_clk_ids = AUD_NR_CLK,
+ .clk_regs = aud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos7_clk_aud_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &aud_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
+ exynos7_clk_aud_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Thomas Abraham <thomas.ab@samsung.com>
+ * Chander Kashyap <k.chander@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos8895 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <soc/samsung/cal-if.h>
+#include <dt-bindings/clock/exynos8895.h>
+
+#include "../../soc/samsung/cal-if/exynos8895/cmucal-vclk.h"
+#include "../../soc/samsung/cal-if/exynos8895/cmucal-node.h"
+#include "../../soc/samsung/cal-if/exynos8895/cmucal-qch.h"
+#include "../../soc/samsung/cal-if/exynos8895/clkout_exynos8895.h"
+#include "composite.h"
+
+static struct samsung_clk_provider *exynos8895_clk_provider;
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate exynos8895_fixed_rate_ext_clks[] __initdata = {
+ FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
+};
+
+/* HWACG VCLK */
+struct init_vclk exynos8895_abox_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_ABOX_CMU_ABOX, ABOX_CMU_ABOX_QCH, "GATE_ABOX_CMU_ABOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_TOP, ABOX_TOP_QCH, "GATE_ABOX_TOP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_ABOX, BTM_ABOX_QCH, "GATE_BTM_ABOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GPIO_ABOX, GPIO_ABOX_QCH, "GATE_GPIO_ABOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_ABOX, PMU_ABOX_QCH, "GATE_PMU_ABOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_ABOX, BCM_ABOX_QCH, "GATE_BCM_ABOX", NULL, 0, VCLK_GATE, "GATE_BCM_ABOX"),
+ HWACG_VCLK(GATE_SMMU_ABOX, SMMU_ABOX_QCH, "GATE_SMMU_ABOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_ABOX, SYSREG_ABOX_QCH, "GATE_SYSREG_ABOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_ABOXCPU, WDT_ABOXCPU_QCH, "GATE_WDT_ABOXCPU", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UAIF0, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0 , "GATE_UAIF0", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_UAIF1, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1 , "GATE_UAIF1", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_UAIF2, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2 , "GATE_UAIF2", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_UAIF3, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3 , "GATE_UAIF3", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_UAIF4, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4 , "GATE_UAIF4", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_DSIF, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF, "GATE_DSIF", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+};
+
+struct init_vclk exynos8895_apm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS_USER, "UMUX_CLKCMU_APM_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_APM_SYS, APM_QCH_SYS, "GATE_APM_SYS", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_APM_CPU, APM_QCH_CPU, "GATE_APM_CPU", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_APM_OSCCLK, APM_QCH_OSCCLK, "GATE_APM_OSCCLK", "fin_pll", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_APM_CMU_APM, APM_CMU_APM_QCH, "GATE_APM_CMU_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2AP, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CP, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2GNSS, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SCAN2AXI, SCAN2AXI_QCH, "GATE_SCAN2AXI", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_APM, SYSREG_APM_QCH, "GATE_SYSREG_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_APM, WDT_APM_QCH, "GATE_WDT_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_bus1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_BUS1_BUS, MUX_CLKCMU_BUS1_BUS_USER, "UMUX_CLKCMU_BUS1_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BUS1_CMU_BUS1, BUS1_CMU_BUS1_QCH, "GATE_BUS1_CMU_BUS1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_BUS1, PMU_BUS1_QCH, "GATE_PMU_BUS1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_BUS1, SYSREG_BUS1_QCH, "GATE_SYSREG_BUS1", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_busc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_BUSC_BUS, MUX_CLKCMU_BUSC_BUS_USER, "UMUX_CLKCMU_BUSC_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_BUSC_BUSPHSI2C, MUX_CLKCMU_BUSC_BUSPHSI2C_USER, "UMUX_CLKCMU_BUSC_BUSPHSI2C", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_ADCIF_BUSC_S0, ADCIF_BUSC_QCH_S0, "GATE_ADCIF_BUSC_S0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADCIF_BUSC_S1, ADCIF_BUSC_QCH_S1, "GATE_ADCIF_BUSC_S1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BUSC_CMU_BUSC, BUSC_CMU_BUSC_QCH, "GATE_BUSC_CMU_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BUSIF_CMUTOPC, BUSIF_CMUTOPC_QCH, "GATE_BUSIF_CMUTOPC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GNSSMBOX, GNSSMBOX_QCH, "GATE_GNSSMBOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GPIO_BUSC, GPIO_BUSC_QCH, "GATE_GPIO_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HSI2CDF, HSI2CDF_QCH, "GATE_HSI2CDF", "UMUX_CLKCMU_BUSC_BUSPHSI2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MBOX, MBOX_QCH, "GATE_MBOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA0, PDMA0_QCH, "GATE_PDMA0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_BUSC, PMU_BUSC_QCH, "GATE_PMU_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SECMBOX, SECMBOX_QCH, "GATE_SECMBOX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPDMA, SPDMA_QCH, "GATE_SPDMA", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY, SPEEDY_QCH, "GATE_SPEEDY", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_BATCHER_WRAP_BATCHER_SPEEDY, SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY, "GATE_SPEEDY_BATCHER_WRAP_BATCHER_SPEEDY", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_BATCHER_WRAP_BATCHER_CP, SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP, "GATE_SPEEDY_BATCHER_WRAP_BATCHER_CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP, SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP, "GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_BUSC, SYSREG_BUSC_QCH, "GATE_SYSREG_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK_QACTIVE(GATE_TREX_BUSC, "GATE_TREX_BUSC", NULL, 0, VCLK_QACTIVE, NULL, 0x151a1004, 0x1000001, 0x1000001),
+ HWACG_VCLK_QACTIVE(GATE_TREX_CORE, "GATE_TREX_CORE", NULL, 0, VCLK_QACTIVE, NULL, 0x14A91004, 0x1000001, 0x1000001),
+};
+
+struct init_vclk exynos8895_cam_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS_USER, "UMUX_CLKCMU_CAM_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_CAM_TPU0, MUX_CLKCMU_CAM_TPU0_USER, "UMUX_CLKCMU_CAM_TPU0", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_CAM_VRA, MUX_CLKCMU_CAM_VRA_USER, "UMUX_CLKCMU_CAM_VRA", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_CAM_TPU1, MUX_CLKCMU_CAM_TPU1_USER, "UMUX_CLKCMU_CAM_TPU1", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_CAMD0, BTM_CAMD0_QCH, "GATE_BTM_CAMD0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_CAMD1, BTM_CAMD1_QCH, "GATE_BTM_CAMD1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAM_CMU_CAM, CAM_CMU_CAM_QCH, "GATE_CAM_CMU_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ISP_EWGEN_CAM, ISP_EWGEN_CAM_QCH, "GATE_ISP_EWGEN_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_CSIS0, IS_CAM_QCH_CSIS0, "GATE_IS_CAM_CSIS0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_CSIS1, IS_CAM_QCH_CSIS1, "GATE_IS_CAM_CSIS1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_CSIS2, IS_CAM_QCH_CSIS2, "GATE_IS_CAM_CSIS2", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_CSIS3, IS_CAM_QCH_CSIS3, "GATE_IS_CAM_CSIS3", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_MC_SCALER, IS_CAM_QCH_MC_SCALER, "GATE_IS_CAM_MC_SCALER", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_CSISX4_DMA, IS_CAM_QCH_CSISX4_DMA, "GATE_IS_CAM_CSISX4_DMA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_SYSMMU_CAM0, IS_CAM_QCH_SYSMMU_CAM0, "GATE_IS_CAM_SYSMMU_CAM0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_SYSMMU_CAM1, IS_CAM_QCH_SYSMMU_CAM1, "GATE_IS_CAM_SYSMMU_CAM1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_BCM_CAM0, IS_CAM_QCH_BCM_CAM0, "GATE_IS_CAM_BCM_CAM0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, "GATE_BCM_CAM0"),
+ HWACG_VCLK(GATE_IS_CAM_BCM_CAM1, IS_CAM_QCH_BCM_CAM1, "GATE_IS_CAM_BCM_CAM1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, "GATE_BCM_CAM1"),
+ HWACG_VCLK(GATE_IS_CAM_QE_TPU0, IS_CAM_QCH_QE_TPU0, "GATE_IS_CAM_QE_TPU0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_QE_VRA, IS_CAM_QCH_QE_VRA, "GATE_IS_CAM_QE_VRA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_BNS, IS_CAM_QCH_BNS, "GATE_IS_CAM_BNS", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_QE_CSISX4, IS_CAM_QCH_QE_CSISX4, "GATE_IS_CAM_QE_CSISX4", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_QE_TPU1, IS_CAM_QCH_QE_TPU1, "GATE_IS_CAM_QE_TPU1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_CAM, PMU_CAM_QCH, "GATE_PMU_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_CAM, SYSREG_CAM_QCH, "GATE_SYSREG_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_TPU0, IS_CAM_QCH_TPU0, "GATE_IS_CAM_TPU0", "UMUX_CLKCMU_CAM_TPU0", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_VRA, IS_CAM_QCH_VRA, "GATE_IS_CAM_VRA", "UMUX_CLKCMU_CAM_VRA", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_CAM_TPU1, IS_CAM_QCH_TPU1, "GATE_IS_CAM_TPU1", "UMUX_CLKCMU_CAM_TPU1", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_cmu_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_CMU_CMU_CMUREF, CMU_CMU_CMUREF_QCH, "GATE_CMU_CMU_CMUREF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK0, "GATE_DFTMUX_TOP_CIS_CLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK1, "GATE_DFTMUX_TOP_CIS_CLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK2, "GATE_DFTMUX_TOP_CIS_CLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK3, DFTMUX_TOP_QCH_CIS_CLK3, "GATE_DFTMUX_TOP_CIS_CLK3", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_dcam_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCAM_BUS, MUX_CLKCMU_DCAM_BUS_USER, "UMUX_CLKCMU_DCAM_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DCAM_IMGD, MUX_CLKCMU_DCAM_IMGD_USER, "UMUX_CLKCMU_DCAM_IMGD", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_DCAM, BTM_DCAM_QCH, "GATE_BTM_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DCAM_CMU_DCAM, DCAM_CMU_DCAM_QCH, "GATE_DCAM_CMU_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DCP, DCP_QCH, "GATE_DCP", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_DCAM, PMU_DCAM_QCH, "GATE_PMU_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_DCAM, BCM_DCAM_QCH, "GATE_BCM_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, "GATE_BCM_DCAM"),
+ HWACG_VCLK(GATE_SYSREG_DCAM, SYSREG_DCAM_QCH, "GATE_SYSREG_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_dpu0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS_USER, "UMUX_CLKCMU_DPU_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_DPUD0, BTM_DPUD0_QCH, "GATE_BTM_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_DPUD1, BTM_DPUD1_QCH, "GATE_BTM_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_DPUD2, BTM_DPUD2_QCH, "GATE_BTM_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DECON0, DECON0_QCH, "GATE_DECON0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPP_DPP_G0, DPP_QCH_DPP_G0, "GATE_DPP_DPP_G0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPP_DPP_G1, DPP_QCH_DPP_G1, "GATE_DPP_DPP_G1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPP_DPP_VGR, DPP_QCH_DPP_VGR, "GATE_DPP_DPP_VGR", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU0_CMU_DPU0, DPU0_CMU_DPU0_QCH, "GATE_DPU0_CMU_DPU0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_DMA, DPU_DMA_QCH, "GATE_DPU_DMA", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_WB_MUX, DPU_WB_MUX_QCH, "GATE_DPU_WB_MUX", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_DPU0, PMU_DPU0_QCH, "GATE_PMU_DPU0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_DPUD0, BCM_DPUD0_QCH, "GATE_BCM_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, "GATE_BCM_DPU0"),
+ HWACG_VCLK(GATE_BCM_DPUD1, BCM_DPUD1_QCH, "GATE_BCM_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, "GATE_BCM_DPU1"),
+ HWACG_VCLK(GATE_BCM_DPUD2, BCM_DPUD2_QCH, "GATE_BCM_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, "GATE_BCM_DPU2"),
+ HWACG_VCLK(GATE_SYSMMU_DPUD0, SYSMMU_DPUD0_QCH, "GATE_SYSMMU_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD1, SYSMMU_DPUD1_QCH, "GATE_SYSMMU_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD2, SYSMMU_DPUD2_QCH, "GATE_SYSMMU_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_DPU0, SYSREG_DPU0_QCH, "GATE_SYSREG_DPU0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_dpu1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DPU1_BUSD, MUX_CLKCMU_DPU1_BUSD_USER, "UMUX_CLKCMU_DPU1_BUSD", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DPU1_BUSP, MUX_CLKCMU_DPU1_BUSP_USER, "UMUX_CLKCMU_DPU1_BUSP", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_DECON1, DECON1_QCH, "GATE_DECON1", "UMUX_CLKCMU_DPU1_BUSD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DECON2_ACLK, DECON2_QCH_ACLK, "GATE_DECON2_ACLK", "UMUX_CLKCMU_DPU1_BUSD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DECON2_VCLK, DECON2_QCH_VCLK, "GATE_DECON2_VCLK", "UMUX_CLKCMU_DPU1_BUSD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU1_CMU_DPU1, DPU1_CMU_DPU1_QCH, "GATE_DPU1_CMU_DPU1", "UMUX_CLKCMU_DPU1_BUSP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_DPU1, PMU_DPU1_QCH, "GATE_PMU_DPU1", "UMUX_CLKCMU_DPU1_BUSP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_DPU1, SYSREG_DPU1_QCH, "GATE_SYSREG_DPU1", "UMUX_CLKCMU_DPU1_BUSP", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_dsp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DSP_BUS, MUX_CLKCMU_DSP_BUS_USER, "UMUX_CLKCMU_DSP_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_SCORE, BTM_SCORE_QCH, "GATE_BTM_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DSP_CMU_DSP, DSP_CMU_DSP_QCH, "GATE_DSP_CMU_DSP", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_DSP, PMU_DSP_QCH, "GATE_PMU_DSP", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_SCORE, BCM_SCORE_QCH, "GATE_BCM_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, "GATE_BCM_SCORE"),
+ HWACG_VCLK(GATE_SCORE, SCORE_QCH, "GATE_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_SCORE, SMMU_SCORE_QCH, "GATE_SMMU_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_DSP, SYSREG_DSP_QCH, "GATE_SYSREG_DSP", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_fsys0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS_USER, "UMUX_CLKCMU_FSYS0_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC_USER, "UMUX_CLKCMU_FSYS0_DPGTC", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_UFS_EMBD, MUX_CLKCMU_FSYS0_UFS_EMBD_USER, "UMUX_CLKCMU_FSYS0_UFS_EMBD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_MMC_EMBD, MUX_CLKCMU_FSYS0_MMC_EMBD_USER, "UMUX_CLKCMU_FSYS0_MMC_EMBD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_USBDRD30, MUX_CLKCMU_FSYS0_USBDRD30_USER, "UMUX_CLKCMU_FSYS0_USBDRD30", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_FSYS0, BTM_FSYS0_QCH, "GATE_BTM_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ETR_MIU_PCLK, ETR_MIU_QCH_PCLK, "GATE_ETR_MIU_PCLK", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ETR_MIU_ACLK, ETR_MIU_QCH_ACLK, "GATE_ETR_MIU_ACLK", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_FSYS0_CMU_FSYS0, FSYS0_CMU_FSYS0_QCH, "GATE_FSYS0_CMU_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GPIO_FSYS0, GPIO_FSYS0_QCH, "GATE_GPIO_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_FSYS0, PMU_FSYS0_QCH, "GATE_PMU_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_FSYS0, BCM_FSYS0_QCH, "GATE_BCM_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, "GATE_BCM_FSYS0"),
+ HWACG_VCLK(GATE_SYSREG_FSYS0, SYSREG_FSYS0_QCH, "GATE_SYSREG_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_FMP", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USBTV_USBTV_HOST, USBTV_QCH_USBTV_HOST, "GATE_USBTV_USBTV_HOST", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DP_LINK, DP_LINK_QCH, "GATE_DP_LINK", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD, UFS_EMBD_QCH, "GATE_UFS_EMBD", "UMUX_CLKCMU_FSYS0_UFS_EMBD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MMC_EMBD, MMC_EMBD_QCH, "GATE_MMC_EMBD", "UMUX_CLKCMU_FSYS0_MMC_EMBD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USBTV_USB30DRD_LINK, USBTV_QCH_USB30DRD_LINK, "GATE_USBTV_USB30DRD_LINK", "UMUX_CLKCMU_FSYS0_USBDRD30", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_fsys1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS_USER, "UMUX_CLKCMU_FSYS1_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD_USER, "UMUX_CLKCMU_FSYS1_MMC_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD_USER, "UMUX_CLKCMU_FSYS1_UFS_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE_USER, "UMUX_CLKCMU_FSYS1_PCIE", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_ADM_AHB_SSS, ADM_AHB_SSS_QCH, "GATE_ADM_AHB_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_FSYS1, BTM_FSYS1_QCH, "GATE_BTM_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_FSYS1_CMU_FSYS1, FSYS1_CMU_FSYS1_QCH, "GATE_FSYS1_CMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GPIO_FSYS1, GPIO_FSYS1_QCH, "GATE_GPIO_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE0_MSTR, PCIE_QCH_PCIE0_MSTR, "GATE_PCIE_PCIE0_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE_PCS, PCIE_QCH_PCIE_PCS, "GATE_PCIE_PCIE_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE_PHY, PCIE_QCH_PCIE_PHY, "GATE_PCIE_PCIE_PHY", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE0_DBI, PCIE_QCH_PCIE0_DBI, "GATE_PCIE_PCIE0_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE0_APB, PCIE_QCH_PCIE0_APB, "GATE_PCIE_PCIE0_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ /* PCIE ref_clk don't have QCH */
+ HWACG_VCLK(GATE_PCIE_PCIE_SOCPLL, PCIE_QCH_PCIE_SOCPLL, "GATE_PCIE_PCIE_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE1_MSTR, PCIE_QCH_PCIE1_MSTR, "GATE_PCIE_PCIE1_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE1_DBI, PCIE_QCH_PCIE1_DBI, "GATE_PCIE_PCIE1_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_PCIE1_APB, PCIE_QCH_PCIE1_APB, "GATE_PCIE_PCIE1_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_FSYS1, PMU_FSYS1_QCH, "GATE_PMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_FSYS1, BCM_FSYS1_QCH, "GATE_BCM_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, "GATE_BCM_FSYS1"),
+ HWACG_VCLK(GATE_RTIC, RTIC_QCH, "GATE_RTIC", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SSS, SSS_QCH, "GATE_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_FSYS1, SYSREG_FSYS1_QCH, "GATE_SYSREG_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TOE_WIFI0, TOE_WIFI0_QCH, "GATE_TOE_WIFI0", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TOE_WIFI1, TOE_WIFI1_QCH, "GATE_TOE_WIFI1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_CARD_FMP, UFS_CARD_QCH_FMP, "GATE_UFS_CARD_FMP", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MMC_CARD, MMC_CARD_QCH, "GATE_MMC_CARD", "UMUX_CLKCMU_FSYS1_MMC_CARD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_CARD, UFS_CARD_QCH, "GATE_UFS_CARD", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_g2d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_G2D_JPEG, MUX_CLKCMU_G2D_JPEG_USER, "UMUX_CLKCMU_G2D_JPEG", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "UMUX_CLKCMU_G2D_G2D", "UMUX_CLKCMU_G2D_JPEG", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_G2DD0, BTM_G2DD0_QCH, "GATE_BTM_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_G2DD1, BTM_G2DD1_QCH, "GATE_BTM_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_G2D, G2D_QCH, "GATE_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_G2D_CMU_G2D, G2D_CMU_G2D_QCH, "GATE_G2D_CMU_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_G2D, PMU_G2D_QCH, "GATE_PMU_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_G2DD0, BCM_G2DD0_QCH, "GATE_BCM_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, "GATE_BCM_G2D0"),
+ HWACG_VCLK(GATE_BCM_G2DD1, BCM_G2DD1_QCH, "GATE_BCM_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, "GATE_BCM_G2D1"),
+ HWACG_VCLK(GATE_SMMU_G2DD0, SMMU_G2DD0_QCH, "GATE_SMMU_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD1, SMMU_G2DD1_QCH, "GATE_SMMU_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_G2D, SYSREG_G2D_QCH, "GATE_SYSREG_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+
+ HWACG_VCLK(GATE_JPEG, JPEG_QCH, "GATE_JPEG", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_M2MSCALER, M2MSCALER_QCH, "GATE_M2MSCALER", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_G2DD2, BTM_G2DD2_QCH, "GATE_BTM_G2DD2", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_QE_JPEG, QE_JPEG_QCH, "GATE_QE_JPEG", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_QE_M2MSCALER, QE_M2MSCALER_QCH, "GATE_QE_M2MSCALER", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_G2DD2, BCM_G2DD2_QCH, "GATE_BCM_G2DD2", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, "GATE_BCM_G2D2"),
+ HWACG_VCLK(GATE_SMMU_G2DD2, SMMU_G2DD2_QCH, "GATE_SMMU_G2DD2", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_g3d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_AGPU_G3D, AGPU_QCH_G3D, "GATE_AGPU_G3D", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BUSIF_HPMG3D, BUSIF_HPMG3D_QCH, "GATE_BUSIF_HPMG3D", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_G3D_CMU_G3D, G3D_CMU_G3D_QCH, "GATE_G3D_CMU_G3D", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_G3D, PMU_G3D_QCH, "GATE_PMU_G3D", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_G3D, SYSREG_G3D_QCH, "GATE_SYSREG_G3D", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_imem_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_IMEM_BUS, MUX_CLKCMU_IMEM_BUS_USER, "UMUX_CLKCMU_IMEM_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IMEM_CMU_IMEM, IMEM_CMU_IMEM_QCH, "GATE_IMEM_CMU_IMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_INTMEM, INTMEM_QCH, "GATE_INTMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_IMEM, PMU_IMEM_QCH, "GATE_PMU_IMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_IMEM, SYSREG_IMEM_QCH, "GATE_SYSREG_IMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_isphq_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS_USER, "UMUX_CLKCMU_ISPHQ_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_ISPHQ_CMU_ISPHQ, ISPHQ_CMU_ISPHQ_QCH, "GATE_ISPHQ_CMU_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ISP_EWGEN_ISPHQ, ISP_EWGEN_ISPHQ_QCH, "GATE_ISP_EWGEN_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_3AA, IS_ISPHQ_QCH_3AA, "GATE_IS_ISPHQ_3AA", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_ISPHQ, IS_ISPHQ_QCH_ISPHQ, "GATE_IS_ISPHQ_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_QE_3AA, IS_ISPHQ_QCH_QE_3AA, "GATE_IS_ISPHQ_QE_3AA", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_QE_ISPHQ, IS_ISPHQ_QCH_QE_ISPHQ, "GATE_IS_ISPHQ_QE_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_ISPHQ, PMU_ISPHQ_QCH, "GATE_PMU_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_ISPHQ, SYSREG_ISPHQ_QCH, "GATE_SYSREG_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_isplq_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS_USER, "UMUX_CLKCMU_ISPLP_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_ISPLP, BTM_ISPLP_QCH, "GATE_BTM_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ISPLP_CMU_ISPLP, ISPLP_CMU_ISPLP_QCH, "GATE_ISPLP_CMU_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ISP_EWGEN_ISPLP, ISP_EWGEN_ISPLP_QCH, "GATE_ISP_EWGEN_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_3AAW, IS_ISPLP_QCH_3AAW, "GATE_IS_ISPLP_3AAW", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_ISPLP, IS_ISPLP_QCH_ISPLP, "GATE_IS_ISPLP_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_QE_3AAW, IS_ISPLP_QCH_QE_3AAW, "GATE_IS_ISPLP_QE_3AAW", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_QE_ISPLP, IS_ISPLP_QCH_QE_ISPLP, "GATE_IS_ISPLP_QE_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_SMMU_ISPLP, IS_ISPLP_QCH_SMMU_ISPLP, "GATE_IS_ISPLP_SMMU_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_BCM_ISPLP, IS_ISPLP_QCH_BCM_ISPLP, "GATE_IS_ISPLP_BCM_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, "GATE_BCM_ISPLP"),
+ HWACG_VCLK(GATE_PMU_ISPLP, PMU_ISPLP_QCH, "GATE_PMU_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_ISPLP, SYSREG_ISPLP_QCH, "GATE_SYSREG_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_iva_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS_USER, "UMUX_CLKCMU_IVA_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_IVA, BTM_IVA_QCH, "GATE_BTM_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA, IVA_QCH, "GATE_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA_CMU_IVA, IVA_CMU_IVA_QCH, "GATE_IVA_CMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA_INTMEM, IVA_INTMEM_QCH, "GATE_IVA_INTMEM", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_IVA, PMU_IVA_QCH, "GATE_PMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_IVA, BCM_IVA_QCH, "GATE_BCM_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, "GATE_BCM_IVA"),
+ HWACG_VCLK(GATE_SMMU_IVA, SMMU_IVA_QCH, "GATE_SMMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_IVA, SYSREG_IVA_QCH, "GATE_SYSREG_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_mfc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_MFC_BUS, MUX_CLKCMU_MFC_BUS_USER, "UMUX_CLKCMU_MFC_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_MFCD0, BTM_MFCD0_QCH, "GATE_BTM_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BTM_MFCD1, BTM_MFCD1_QCH, "GATE_BTM_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MFC, MFC_QCH, "GATE_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MFC_CMU_MFC, MFC_CMU_MFC_QCH, "GATE_MFC_CMU_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_MFC, PMU_MFC_QCH, "GATE_PMU_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_MFCD0, BCM_MFCD0_QCH, "GATE_BCM_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, "GATE_BCM_MFC0"),
+ HWACG_VCLK(GATE_BCM_MFCD1, BCM_MFCD1_QCH, "GATE_BCM_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, "GATE_BCM_MFC1"),
+ HWACG_VCLK(GATE_SMMU_MFCD0, SMMU_MFCD0_QCH, "GATE_SMMU_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_MFCD1, SMMU_MFCD1_QCH, "GATE_SMMU_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_MFC, SYSREG_MFC_QCH, "GATE_SYSREG_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_peric0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS_USER, "UMUX_CLKCMU_PERIC0_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_UART_DBG, MUX_CLKCMU_PERIC0_UART_DBG_USER, "UMUX_CLKCMU_PERIC0_UART_DBG", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI00, MUX_CLKCMU_PERIC0_USI00_USER, "UMUX_CLKCMU_PERIC0_USI00", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI01, MUX_CLKCMU_PERIC0_USI01_USER, "UMUX_CLKCMU_PERIC0_USI01", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI02, MUX_CLKCMU_PERIC0_USI02_USER, "UMUX_CLKCMU_PERIC0_USI02", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI03, MUX_CLKCMU_PERIC0_USI03_USER, "UMUX_CLKCMU_PERIC0_USI03", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_GPIO_PERIC0, GPIO_PERIC0_QCH, "GATE_GPIO_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PERIC0_CMU_PERIC0, PERIC0_CMU_PERIC0_QCH, "GATE_PERIC0_CMU_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_PERIC0, PMU_PERIC0_QCH, "GATE_PMU_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM, PWM_QCH, "GATE_PWM", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY2_TSP, SPEEDY2_TSP_QCH, "GATE_SPEEDY2_TSP", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_PERIC0, SYSREG_PERIC0_QCH, "GATE_SYSREG_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_DBG, UART_DBG_QCH, "GATE_UART_DBG", "UMUX_CLKCMU_PERIC0_UART_DBG", 0, VCLK_GATE, "console-pclk0"),
+ HWACG_VCLK(GATE_USI00, USI00_QCH, "GATE_USI00", "UMUX_CLKCMU_PERIC0_USI00", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI01, USI01_QCH, "GATE_USI01", "UMUX_CLKCMU_PERIC0_USI01", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI02, USI02_QCH, "GATE_USI02", "UMUX_CLKCMU_PERIC0_USI02", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI03, USI03_QCH, "GATE_USI03", "UMUX_CLKCMU_PERIC0_USI03", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+};
+
+struct init_vclk exynos8895_peric1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS_USER, "UMUX_CLKCMU_PERIC1_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_UART_BT, MUX_CLKCMU_PERIC1_UART_BT_USER, "UMUX_CLKCMU_PERIC1_UART_BT", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI04, MUX_CLKCMU_PERIC1_USI04_USER, "UMUX_CLKCMU_PERIC1_USI04", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI05, MUX_CLKCMU_PERIC1_USI05_USER, "UMUX_CLKCMU_PERIC1_USI05", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI06, MUX_CLKCMU_PERIC1_USI06_USER, "UMUX_CLKCMU_PERIC1_USI06", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI07, MUX_CLKCMU_PERIC1_USI07_USER, "UMUX_CLKCMU_PERIC1_USI07", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI08, MUX_CLKCMU_PERIC1_USI08_USER, "UMUX_CLKCMU_PERIC1_USI08", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI09, MUX_CLKCMU_PERIC1_USI09_USER, "UMUX_CLKCMU_PERIC1_USI09", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI10, MUX_CLKCMU_PERIC1_USI10_USER, "UMUX_CLKCMU_PERIC1_USI10", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI11, MUX_CLKCMU_PERIC1_USI11_USER, "UMUX_CLKCMU_PERIC1_USI11", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI12, MUX_CLKCMU_PERIC1_USI12_USER, "UMUX_CLKCMU_PERIC1_USI12", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI13, MUX_CLKCMU_PERIC1_USI13_USER, "UMUX_CLKCMU_PERIC1_USI13", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_SPI_CAM0, MUX_CLKCMU_PERIC1_SPI_CAM0_USER, "UMUX_CLKCMU_PERIC1_SPI_CAM0", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_SPI_CAM1, MUX_CLKCMU_PERIC1_SPI_CAM1_USER, "UMUX_CLKCMU_PERIC1_SPI_CAM1", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_SPEEDY2, MUX_CLKCMU_PERIC1_SPEEDY2_USER, "UMUX_CLKCMU_PERIC1_SPEEDY2", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_GPIO_PERIC1, GPIO_PERIC1_QCH, "GATE_GPIO_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HSI2C_CAM0, HSI2C_CAM0_QCH, "GATE_HSI2C_CAM0", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HSI2C_CAM1, HSI2C_CAM1_QCH, "GATE_HSI2C_CAM1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HSI2C_CAM2, HSI2C_CAM2_QCH, "GATE_HSI2C_CAM2", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HSI2C_CAM3, HSI2C_CAM3_QCH, "GATE_HSI2C_CAM3", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PERIC1_CMU_PERIC1, PERIC1_CMU_PERIC1_QCH, "GATE_PERIC1_CMU_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_PERIC1, PMU_PERIC1_QCH, "GATE_PMU_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY2_TSP1, SPEEDY2_TSP1_QCH, "GATE_SPEEDY2_TSP1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY2_TSP2, SPEEDY2_TSP2_QCH, "GATE_SPEEDY2_TSP2", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_PERIC1, SYSREG_PERIC1_QCH, "GATE_SYSREG_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_BT, UART_BT_QCH, "GATE_UART_BT", "UMUX_CLKCMU_PERIC1_UART_BT", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI04, USI04_QCH, "GATE_USI04", "UMUX_CLKCMU_PERIC1_USI04", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI05, USI05_QCH, "GATE_USI05", "UMUX_CLKCMU_PERIC1_USI05", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI06, USI06_QCH, "GATE_USI06", "UMUX_CLKCMU_PERIC1_USI06", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI07, USI07_QCH, "GATE_USI07", "UMUX_CLKCMU_PERIC1_USI07", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI08, USI08_QCH, "GATE_USI08", "UMUX_CLKCMU_PERIC1_USI08", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI09, USI09_QCH, "GATE_USI09", "UMUX_CLKCMU_PERIC1_USI09", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI10, USI10_QCH, "GATE_USI10", "UMUX_CLKCMU_PERIC1_USI10", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI11, USI11_QCH, "GATE_USI11", "UMUX_CLKCMU_PERIC1_USI11", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI12, USI12_QCH, "GATE_USI12", "UMUX_CLKCMU_PERIC1_USI12", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_USI13, USI13_QCH, "GATE_USI13", "UMUX_CLKCMU_PERIC1_USI13", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
+ HWACG_VCLK(GATE_SPI_CAM0, SPI_CAM0_QCH, "GATE_SPI_CAM0", "UMUX_CLKCMU_PERIC1_SPI_CAM0", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_CAM1, SPI_CAM1_QCH, "GATE_SPI_CAM1", "UMUX_CLKCMU_PERIC1_SPI_CAM1", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY2_DDI, SPEEDY2_DDI_QCH, "GATE_SPEEDY2_DDI", "UMUX_CLKCMU_PERIC1_SPEEDY2", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY2_DDI1, SPEEDY2_DDI1_QCH, "GATE_SPEEDY2_DDI1", "UMUX_CLKCMU_PERIC1_SPEEDY2", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY2_DDI2, SPEEDY2_DDI2_QCH, "GATE_SPEEDY2_DDI2", "UMUX_CLKCMU_PERIC1_SPEEDY2", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_peris_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS_USER, "UMUX_CLKCMU_PERIS_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BUSIF_TMU, BUSIF_TMU_QCH, "GATE_BUSIF_TMU", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GIC, GIC_QCH, "GATE_GIC", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MCT, MCT_QCH, "GATE_MCT", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_BIRA, OTP_CON_BIRA_QCH, "GATE_OTP_CON_BIRA", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_TOP, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PERIS_CMU_PERIS, PERIS_CMU_PERIS_QCH, "GATE_PERIS_CMU_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_PERIS, PMU_PERIS_QCH, "GATE_PMU_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_PERIS, SYSREG_PERIS_QCH, "GATE_SYSREG_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC00, TZPC00_QCH, "GATE_TZPC00", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC01, TZPC01_QCH, "GATE_TZPC01", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC02, TZPC02_QCH, "GATE_TZPC02", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC03, TZPC03_QCH, "GATE_TZPC03", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC04, TZPC04_QCH, "GATE_TZPC04", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC05, TZPC05_QCH, "GATE_TZPC05", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC06, TZPC06_QCH, "GATE_TZPC06", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC07, TZPC07_QCH, "GATE_TZPC07", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC08, TZPC08_QCH, "GATE_TZPC08", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC09, TZPC09_QCH, "GATE_TZPC09", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC10, TZPC10_QCH, "GATE_TZPC10", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC11, TZPC11_QCH, "GATE_TZPC11", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC12, TZPC12_QCH, "GATE_TZPC12", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC13, TZPC13_QCH, "GATE_TZPC13", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC14, TZPC14_QCH, "GATE_TZPC14", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TZPC15, TZPC15_QCH, "GATE_TZPC15", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER0, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER1, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_srdz_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_SRDZ_BUS, MUX_CLKCMU_SRDZ_BUS_USER, "UMUX_CLKCMU_SRDZ_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_SRDZ_IMGD, MUX_CLKCMU_SRDZ_IMGD_USER, "UMUX_CLKCMU_SRDZ_IMGD", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_SRDZ, BTM_SRDZ_QCH, "GATE_BTM_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_SRDZ, PMU_SRDZ_QCH, "GATE_PMU_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_SRDZ, BCM_SRDZ_QCH, "GATE_BCM_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, "GATE_BCM_SRDZ"),
+ HWACG_VCLK(GATE_SMMU_SRDZ, SMMU_SRDZ_QCH, "GATE_SMMU_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SRDZ, SRDZ_QCH, "GATE_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SRDZ_CMU_SRDZ, SRDZ_CMU_SRDZ_QCH, "GATE_SRDZ_CMU_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_SRDZ, SYSREG_SRDZ_QCH, "GATE_SYSREG_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_vpu_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VPU_BUS, MUX_CLKCMU_VPU_BUS_USER, "UMUX_CLKCMU_VPU_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BTM_VPU, BTM_VPU_QCH, "GATE_BTM_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PMU_VPU, PMU_VPU_QCH, "GATE_PMU_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_BCM_VPU, BCM_VPU_QCH, "GATE_BCM_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, "GATE_BCM_VPU"),
+ HWACG_VCLK(GATE_SMMU_VPU, SMMU_VPU_QCH, "GATE_SMMU_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_VPU, SYSREG_VPU_QCH, "GATE_SYSREG_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VPU, VPU_QCH, "GATE_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VPU_CMU_VPU, VPU_CMU_VPU_QCH, "GATE_VPU_CMU_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos8895_vts_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_OSC_VTS, OSC_VTS, "GATE_OSC_VTS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_CMU_VTS_CMUREF, CMU_VTS_CMUREF_QCH, "GATE_CMU_VTS_CMUREF", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DMIC_AHB, DMIC_AHB_QCH_PCLK, "GATE_DMIC_AHB", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DMIC_AHB_HCLK, DMIC_AHB_QCH_HCLK, "GATE_DMIC_AHB_HCLK", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DMIC_IF, DMIC_IF_QCH_PCLK, "GATE_DMIC_IF", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DMIC_IF_DMIC_CLK, DMIC_IF_QCH_DMIC_CLK, "GATE_DMIC_IF_DMIC_CLK", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GPIO_VTS, GPIO_VTS_QCH, "GATE_GPIO_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_VTS2AP, MAILBOX_VTS2AP_QCH, "GATE_MAILBOX_VTS2AP", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_VTS, SYSREG_VTS_QCH, "GATE_SYSREG_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VTS_CPU, VTS_QCH_CPU, "GATE_VTS_CPU", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VTS_SYS, VTS_QCH_SYS, "GATE_VTS_SYS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VTS_SYS_DMIC, VTS_QCH_SYS_DMIC, "GATE_VTS_SYS_DMIC", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VTS_CMU_VTS, VTS_CMU_VTS_QCH, "GATE_VTS_CMU_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_VTS, WDT_VTS_QCH, "GATE_WDT_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
+};
+
+static struct init_vclk exynos8895_clkout_vclks[] __initdata = {
+ VCLK(OSCCLK_NFC, VCLK_CLKOUT1, "OSCCLK_NFC", 0, 0, NULL),
+ VCLK(OSCCLK_AUD, VCLK_CLKOUT0, "OSCCLK_AUD", 0, 0, NULL),
+};
+
+/* Special VCLK */
+struct init_vclk exynos8895_abox_vclks[] __initdata = {
+ VCLK(ABOX_CPU_PCLKDBG, VCLK_SPL_CLK_ABOX_CPU_PCLKDBG_BLK_ABOX, "ABOX_CPU_PCLKDBG", 0, 0, NULL),
+ VCLK(ABOX_UAIF0, VCLK_SPL_CLK_ABOX_UAIF0_BLK_ABOX, "ABOX_UAIF0", 0, 0, NULL),
+ VCLK(ABOX_UAIF1, VCLK_SPL_CLK_ABOX_UAIF1_BLK_ABOX, "ABOX_UAIF1", 0, 0, NULL),
+ VCLK(ABOX_UAIF2, VCLK_SPL_CLK_ABOX_UAIF2_BLK_ABOX, "ABOX_UAIF2", 0, 0, NULL),
+ VCLK(ABOX_UAIF3, VCLK_SPL_CLK_ABOX_UAIF3_BLK_ABOX, "ABOX_UAIF3", 0, 0, NULL),
+ VCLK(ABOX_UAIF4, VCLK_SPL_CLK_ABOX_UAIF4_BLK_ABOX, "ABOX_UAIF4", 0, 0, NULL),
+ VCLK(ABOX_CPU_ACLK, VCLK_SPL_CLK_ABOX_CPU_ACLK_BLK_ABOX, "ABOX_CPU_ACLK", 0, 0, NULL),
+ VCLK(ABOX_DMIC, VCLK_DIV_CLK_ABOX_DMIC_BLK_ABOX, "ABOX_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_AUDIF, DIV_CLK_ABOX_AUDIF, "DOUT_CLK_ABOX_AUDIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_DSIF, DIV_CLK_ABOX_DSIF, "DOUT_CLK_ABOX_DSIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_DMIC, DIV_CLK_ABOX_DMIC, "DOUT_CLK_ABOX_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF0, DIV_CLK_ABOX_UAIF0, "DOUT_CLK_ABOX_UAIF0", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF1, DIV_CLK_ABOX_UAIF1, "DOUT_CLK_ABOX_UAIF1", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF2, DIV_CLK_ABOX_UAIF2, "DOUT_CLK_ABOX_UAIF2", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF3, DIV_CLK_ABOX_UAIF3, "DOUT_CLK_ABOX_UAIF3", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF4, DIV_CLK_ABOX_UAIF4, "DOUT_CLK_ABOX_UAIF4", 0, 0, NULL),
+ VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_fsys0_vclks[] __initdata = {
+ VCLK(MMC_EMBD, VCLK_SPL_CLK_FSYS0_MMC_EMBD_BLK_CMU, "MMC_EMBD", 0, 0, NULL),
+ VCLK(DPGTC, VCLK_SPL_CLK_FSYS0_DPGTC_BLK_CMU, "DPGTC", 0, 0, NULL),
+ VCLK(UFS_EMBD, VCLK_SPL_CLK_FSYS0_UFS_EMBD_BLK_CMU, "UFS_EMBD", 0, 0, NULL),
+ VCLK(USBDRD30, VCLK_SPL_CLK_FSYS0_USBDRD30_BLK_CMU, "USBDRD30", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_fsys1_vclks[] __initdata = {
+ VCLK(MMC_CARD, VCLK_SPL_CLK_FSYS1_MMC_CARD_BLK_CMU, "MMC_CARD", 0, 0, NULL),
+ VCLK(UFS_CARD, VCLK_SPL_CLK_FSYS1_UFS_CARD_BLK_CMU, "UFS_CARD", 0, 0, NULL),
+ VCLK(PCIE, VCLK_OCC_CLK_FSYS1_PCIE_BLK_CMU, "PCIE", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_peric0_vclks[] __initdata = {
+ VCLK(UART_DBG, VCLK_SPL_CLK_PERIC0_UART_DBG_BLK_CMU, "UART_DBG", 0, 0, "console-sclk0"),
+ VCLK(USI00, VCLK_SPL_CLK_PERIC0_USI00_BLK_CMU, "USI00", 0, 0, NULL),
+ VCLK(USI01, VCLK_SPL_CLK_PERIC0_USI01_BLK_CMU, "USI01", 0, 0, NULL),
+ VCLK(USI02, VCLK_SPL_CLK_PERIC0_USI02_BLK_CMU, "USI02", 0, 0, NULL),
+ VCLK(USI03, VCLK_SPL_CLK_PERIC0_USI03_BLK_CMU, "USI03", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_peric1_vclks[] __initdata = {
+ VCLK(SPI_CAM0, VCLK_SPL_CLK_PERIC1_SPI_CAM0_BLK_CMU, "SPI_CAM0", 0, 0, NULL),
+ VCLK(SPI_CAM1, VCLK_SPL_CLK_PERIC1_SPI_CAM1_BLK_CMU, "SPI_CAM1", 0, 0, NULL),
+ VCLK(UART_BT, VCLK_SPL_CLK_PERIC1_UART_BT_BLK_CMU, "UART_BT", 0, 0, NULL),
+ VCLK(USI04, VCLK_SPL_CLK_PERIC1_USI04_BLK_CMU, "USI04", 0, 0, NULL),
+ VCLK(USI05, VCLK_SPL_CLK_PERIC1_USI05_BLK_CMU, "USI05", 0, 0, NULL),
+ VCLK(USI06, VCLK_SPL_CLK_PERIC1_USI06_BLK_CMU, "USI06", 0, 0, NULL),
+ VCLK(USI07, VCLK_SPL_CLK_PERIC1_USI07_BLK_CMU, "USI07", 0, 0, NULL),
+ VCLK(USI08, VCLK_SPL_CLK_PERIC1_USI08_BLK_CMU, "USI08", 0, 0, NULL),
+ VCLK(USI09, VCLK_SPL_CLK_PERIC1_USI09_BLK_CMU, "USI09", 0, 0, NULL),
+ VCLK(USI10, VCLK_SPL_CLK_PERIC1_USI10_BLK_CMU, "USI10", 0, 0, NULL),
+ VCLK(USI11, VCLK_SPL_CLK_PERIC1_USI11_BLK_CMU, "USI11", 0, 0, NULL),
+ VCLK(USI12, VCLK_SPL_CLK_PERIC1_USI12_BLK_CMU, "USI12", 0, 0, NULL),
+ VCLK(USI13, VCLK_SPL_CLK_PERIC1_USI13_BLK_CMU, "USI13", 0, 0, NULL),
+ VCLK(DOUT_CLKCMU_PERIC1_SPI_CAM0, CLKCMU_PERIC1_SPI_CAM0, "DOUT_CLKCMU_PERIC1_SPI_CAM0", 0, 0, NULL),
+ VCLK(DOUT_CLKCMU_PERIC1_SPI_CAM1, CLKCMU_PERIC1_SPI_CAM1, "DOUT_CLKCMU_PERIC1_SPI_CAM1", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_cmu_vclks[] __initdata = {
+ VCLK(CMU_CMUREF, VCLK_OCC_CMU_CMUREF_BLK_CMU, "CMU_CMUREF", 0, 0, NULL),
+ VCLK(HPM, VCLK_CLKCMU_HPM_BLK_CMU, "HPM", 0, 0, NULL),
+ VCLK(CIS_CLK0, VCLK_CLKCMU_CIS_CLK0_BLK_CMU, "CIS_CLK0", 0, 0, NULL),
+ VCLK(CIS_CLK1, VCLK_CLKCMU_CIS_CLK1_BLK_CMU, "CIS_CLK1", 0, 0, NULL),
+ VCLK(CIS_CLK2, VCLK_CLKCMU_CIS_CLK2_BLK_CMU, "CIS_CLK2", 0, 0, NULL),
+ VCLK(CIS_CLK3, VCLK_CLKCMU_CIS_CLK3_BLK_CMU, "CIS_CLK3", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_dpu1_vclks[] __initdata = {
+ VCLK(DECON2, VCLK_SPL_CLK_DPU1_DECON2_BLK_DPU1, "DECON2", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_vts_vclks[] __initdata = {
+ VCLK(DMIC, VCLK_DIV_CLK_VTS_DMIC_BLK_VTS, "DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMICIF, DIV_CLK_VTS_DMICIF, "DOUT_CLK_VTS_DMICIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC, "DOUT_CLK_VTS_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMIC_DIV2, "DOUT_CLK_VTS_DMIC_DIV2", 0, 0, NULL),
+};
+
+struct init_vclk exynos8895_dvfs_vclks[] __initdata = {
+ VCLK(DFS_ABOX, VCLK_DFS_ABOX, "dfs_abox", 0, VCLK_DFS, NULL),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ {.compatible = "samsung,exynos8895-oscclk", .data = (void *)0},
+ {},
+};
+
+void exynos8895_vclk_init(void)
+{
+ /* Common clock init */
+ cal_clk_setrate(VCLK_BLK_BUS1, 266500);
+ cal_clk_setrate(VCLK_BLK_BUSC, 266500);
+ cal_clk_setrate(VCLK_BLK_CORE, 355333);
+ cal_clk_setrate(VCLK_BLK_ABOX, 1179648);
+ cal_clk_setrate(VCLK_BLK_CAM, 266500);
+ cal_clk_setrate(VCLK_BLK_DBG, 200000);
+ cal_clk_setrate(VCLK_BLK_DCAM, 222444);
+ cal_clk_setrate(VCLK_BLK_DPU0, 157500);
+ cal_clk_setrate(VCLK_BLK_DSP, 266500);
+ cal_clk_setrate(VCLK_BLK_G2D, 266500);
+ cal_clk_setrate(VCLK_BLK_ISPHQ, 266500);
+ cal_clk_setrate(VCLK_BLK_ISPLP, 266500);
+ cal_clk_setrate(VCLK_BLK_IVA, 266500);
+ cal_clk_setrate(VCLK_BLK_MFC, 166833);
+ cal_clk_setrate(VCLK_BLK_SRDZ, 266500);
+ cal_clk_setrate(VCLK_BLK_VPU, 266500);
+ cal_clk_setrate(VCLK_BLK_VTS, 49152);
+
+ cal_clk_disable(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0);
+ cal_clk_disable(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1);
+ cal_clk_disable(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2);
+ cal_clk_disable(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3);
+ cal_clk_disable(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4);
+ cal_clk_disable(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF);
+}
+
+/* register exynos8895 clocks */
+void __init exynos8895_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ int ret;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ ret = cal_if_init(np);
+ if (ret)
+ panic("%s: unable to initialize cal-if\n", __func__);
+
+ exynos8895_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (!exynos8895_clk_provider)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_register_of_fixed_ext(exynos8895_clk_provider, exynos8895_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos8895_fixed_rate_ext_clks),
+ ext_clk_match);
+ /* register HWACG vclk */
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_abox_hwacg_vclks, ARRAY_SIZE(exynos8895_abox_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_apm_hwacg_vclks, ARRAY_SIZE(exynos8895_apm_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_bus1_hwacg_vclks, ARRAY_SIZE(exynos8895_bus1_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_busc_hwacg_vclks, ARRAY_SIZE(exynos8895_busc_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_cam_hwacg_vclks, ARRAY_SIZE(exynos8895_cam_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_cmu_hwacg_vclks, ARRAY_SIZE(exynos8895_cmu_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_dcam_hwacg_vclks, ARRAY_SIZE(exynos8895_dcam_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_dpu0_hwacg_vclks, ARRAY_SIZE(exynos8895_dpu0_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_dpu1_hwacg_vclks, ARRAY_SIZE(exynos8895_dpu1_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_dsp_hwacg_vclks, ARRAY_SIZE(exynos8895_dsp_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_fsys0_hwacg_vclks, ARRAY_SIZE(exynos8895_fsys0_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_fsys1_hwacg_vclks, ARRAY_SIZE(exynos8895_fsys1_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_g2d_hwacg_vclks, ARRAY_SIZE(exynos8895_g2d_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_g3d_hwacg_vclks, ARRAY_SIZE(exynos8895_g3d_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_imem_hwacg_vclks, ARRAY_SIZE(exynos8895_imem_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_isphq_hwacg_vclks, ARRAY_SIZE(exynos8895_isphq_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_isplq_hwacg_vclks, ARRAY_SIZE(exynos8895_isplq_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_iva_hwacg_vclks, ARRAY_SIZE(exynos8895_iva_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_mfc_hwacg_vclks, ARRAY_SIZE(exynos8895_mfc_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_peric0_hwacg_vclks, ARRAY_SIZE(exynos8895_peric0_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_peric1_hwacg_vclks, ARRAY_SIZE(exynos8895_peric1_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_peris_hwacg_vclks, ARRAY_SIZE(exynos8895_peris_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_srdz_hwacg_vclks, ARRAY_SIZE(exynos8895_srdz_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_vpu_hwacg_vclks, ARRAY_SIZE(exynos8895_vpu_hwacg_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_vts_hwacg_vclks, ARRAY_SIZE(exynos8895_vts_hwacg_vclks));
+
+ /* register special vclk */
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_cmu_vclks, ARRAY_SIZE(exynos8895_cmu_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_abox_vclks, ARRAY_SIZE(exynos8895_abox_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_fsys0_vclks, ARRAY_SIZE(exynos8895_fsys0_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_fsys1_vclks, ARRAY_SIZE(exynos8895_fsys1_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_peric0_vclks, ARRAY_SIZE(exynos8895_peric0_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_peric1_vclks, ARRAY_SIZE(exynos8895_peric1_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_dpu1_vclks, ARRAY_SIZE(exynos8895_dpu1_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_vts_vclks, ARRAY_SIZE(exynos8895_vts_vclks));
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_clkout_vclks, ARRAY_SIZE(exynos8895_clkout_vclks));
+
+ /* register DVFS vclk */
+ samsung_register_vclk(exynos8895_clk_provider, exynos8895_dvfs_vclks, ARRAY_SIZE(exynos8895_dvfs_vclks));
+
+ clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll",CLK_SET_RATE_PARENT, 1, 1);
+
+ samsung_clk_of_add_provider(np, exynos8895_clk_provider);
+
+ late_time_init = exynos8895_vclk_init;
+
+ pr_info("EXYNOS8895: Clock setup completed\n");
+}
+
+CLK_OF_DECLARE(exynos8895_clk, "samsung,exynos8895-clock", exynos8895_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos9610 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <soc/samsung/cal-if.h>
+#include <dt-bindings/clock/exynos9610.h>
+
+#include "../../soc/samsung/cal-if/exynos9610/cmucal-vclk.h"
+#include "../../soc/samsung/cal-if/exynos9610/cmucal-node.h"
+#include "../../soc/samsung/cal-if/exynos9610/cmucal-qch.h"
+#include "../../soc/samsung/cal-if/exynos9610/clkout_exynos9610.h"
+#include "composite.h"
+
+static struct samsung_clk_provider *exynos9610_clk_provider;
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate exynos9610_fixed_rate_ext_clks[] __initdata = {
+ FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
+};
+
+/* HWACG VCLK */
+struct init_vclk exynos9610_apm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS_USER, "UMUX_CLKCMU_APM_BUS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBEINTEGRATION_QCH_GREBE", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBEINTEGRATION_QCH_DBG", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_INTMEM_QCH, INTMEM_QCH, "GATE_INTMEM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP_QCH, MAILBOX_AP2CP_QCH, "GATE_MAILBOX_AP2CP_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP_S_QCH, MAILBOX_AP2CP_S_QCH, "GATE_MAILBOX_AP2CP_S_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2GNSS_QCH, MAILBOX_AP2GNSS_QCH, "GATE_MAILBOX_AP2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2SHUB_QCH, MAILBOX_AP2SHUB_QCH, "GATE_MAILBOX_AP2SHUB_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2WLBT_QCH, MAILBOX_AP2WLBT_QCH, "GATE_MAILBOX_AP2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2AP_QCH, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CP_QCH, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2GNSS_QCH, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2SHUB_QCH, MAILBOX_APM2SHUB_QCH, "GATE_MAILBOX_APM2SHUB_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2WLBT_QCH, MAILBOX_APM2WLBT_QCH, "GATE_MAILBOX_APM2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CP2GNSS_QCH, MAILBOX_CP2GNSS_QCH, "GATE_MAILBOX_CP2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CP2SHUB_QCH, MAILBOX_CP2SHUB_QCH, "GATE_MAILBOX_CP2SHUB_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CP2WLBT_QCH, MAILBOX_CP2WLBT_QCH, "GATE_MAILBOX_CP2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_SHUB2GNSS_QCH, MAILBOX_SHUB2GNSS_QCH, "GATE_MAILBOX_SHUB2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_SHUB2WLBT_QCH, MAILBOX_SHUB2WLBT_QCH, "GATE_MAILBOX_SHUB2WLBT_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_WLBT2ABOX_QCH, MAILBOX_WLBT2ABOX_QCH, "GATE_MAILBOX_WLBT2ABOX_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_WLBT2GNSS_QCH, MAILBOX_WLBT2GNSS_QCH, "GATE_MAILBOX_WLBT2GNSS_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PEM_QCH, PEM_QCH, "GATE_PEM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_APM_QCH, SPEEDY_APM_QCH, "GATE_SPEEDY_APM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSREG_APM_QCH, SYSREG_APM_QCH, "GATE_SYSREG_APM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_APM_QCH, WDT_APM_QCH, "GATE_WDT_APM_QCH", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_cam_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS_USER, "UMUX_CLKCMU_CAM_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0, IS6P10P0_CAM_QCH_S_CAM_CSIS0, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1, IS6P10P0_CAM_QCH_S_CAM_CSIS1, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2, IS6P10P0_CAM_QCH_S_CAM_CSIS2, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3, IS6P10P0_CAM_QCH_S_CAM_CSIS3, "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_3AA, IS6P10P0_CAM_QCH_S_CAM_3AA, "GATE_IS6P10P0_CAM_QCH_S_CAM_3AA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU, IS6P10P0_CAM_QCH_S_CAM_SMMU, "GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA, IS6P10P0_CAM_QCH_S_CAM_RDMA, "GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_cmgp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(MUX_CMGP_ADC, MUX_CLK_CMGP_ADC, "MUX_CMGP_ADC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_I2C, MUX_CLK_CMGP_I2C, "MUX_CMGP_I2C", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI00, MUX_CLK_CMGP_USI00, "MUX_CMGP_USI00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI01, MUX_CLK_CMGP_USI01, "MUX_CMGP_USI01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI02, MUX_CLK_CMGP_USI02, "MUX_CMGP_USI02", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI03, MUX_CLK_CMGP_USI03, "MUX_CMGP_USI03", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_CMGP_USI04, MUX_CLK_CMGP_USI04, "MUX_CMGP_USI04", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_QCH_S0, ADC_CMGP_QCH_S0, "GATE_ADC_CMGP_QCH_S0", "MUX_CMGP_ADC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_QCH_S1, ADC_CMGP_QCH_S1, "GATE_ADC_CMGP_QCH_S1", "MUX_CMGP_ADC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_QCH_ADC, ADC_CMGP_QCH_ADC, "GATE_ADC_CMGP_QCH_ADC", "MUX_CMGP_ADC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP00_QCH, I2C_CMGP00_QCH, "GATE_I2C_CMGP00_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP01_QCH, I2C_CMGP01_QCH, "GATE_I2C_CMGP01_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP02_QCH, I2C_CMGP02_QCH, "GATE_I2C_CMGP02_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP03_QCH, I2C_CMGP03_QCH, "GATE_I2C_CMGP03_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP04_QCH, I2C_CMGP04_QCH, "GATE_I2C_CMGP04_QCH", "MUX_CMGP_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP00_QCH, USI_CMGP00_QCH, "GATE_USI_CMGP00_QCH", "MUX_CMGP_USI00", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP01_QCH, USI_CMGP01_QCH, "GATE_USI_CMGP01_QCH", "MUX_CMGP_USI01", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP02_QCH, USI_CMGP02_QCH, "GATE_USI_CMGP02_QCH", "MUX_CMGP_USI02", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP03_QCH, USI_CMGP03_QCH, "GATE_USI_CMGP03_QCH", "MUX_CMGP_USI03", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP04_QCH, USI_CMGP04_QCH, "GATE_USI_CMGP04_QCH", "MUX_CMGP_USI04", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_top_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS0, DFTMUX_TOP_QCH_CLK_CSIS0, "GATE_DFTMUX_TOP_QCH_CLK_CSIS0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS1, DFTMUX_TOP_QCH_CLK_CSIS1, "GATE_DFTMUX_TOP_QCH_CLK_CSIS1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS2, DFTMUX_TOP_QCH_CLK_CSIS2, "GATE_DFTMUX_TOP_QCH_CLK_CSIS2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CLK_CSIS3, DFTMUX_TOP_QCH_CLK_CSIS3, "GATE_DFTMUX_TOP_QCH_CLK_CSIS3", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_QCH, OTP_QCH, "GATE_OTP_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_core_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(MUX_CORE_GIC, MUX_CLK_CORE_GIC, "MUX_CORE_GIC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GIC400_AIHWACG_QCH, GIC400_AIHWACG_QCH, "GATE_GIC400_AIHWACG_QCH", "MUX_CORE_GIC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA_CORE_QCH, PDMA_CORE_QCH, "GATE_PDMA_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW_CORE_MEM0_QCH, PPFW_CORE_MEM0_QCH, "GATE_PPFW_CORE_MEM0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW_CORE_MEM1_QCH, PPFW_CORE_MEM1_QCH, "GATE_PPFW_CORE_MEM1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW_CORE_PERI_QCH, PPFW_CORE_PERI_QCH, "GATE_PPFW_CORE_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SIREX_QCH, SIREX_QCH, "GATE_SIREX_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPDMA_CORE_QCH, SPDMA_CORE_QCH, "GATE_SPDMA_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_D_CORE_QCH, TREX_D_CORE_QCH, "GATE_TREX_D_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_D_NRT_QCH, TREX_D_NRT_QCH, "GATE_TREX_D_NRT_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P_CORE_QCH, TREX_P_CORE_QCH, "GATE_TREX_P_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_dispaud_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(MUX_AUD_FM, MUX_CLK_AUD_FM, "MUX_AUD_FM", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DISPAUD_BUS, MUX_CLKCMU_DISPAUD_DISP_USER, "MUX_CLKCMU_DISPAUD_DISP_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_CPU, ABOX_QCH_CPU, "GATE_ABOX_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_ACLK, ABOX_QCH_S_ACLK, "GATE_ABOX_QCH_S_ACLK", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK0, ABOX_QCH_S_BCLK0, "GATE_ABOX_QCH_S_BCLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK2, ABOX_QCH_S_BCLK2, "GATE_ABOX_QCH_S_BCLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK1, ABOX_QCH_S_BCLK1, "GATE_ABOX_QCH_S_BCLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_FM, ABOX_QCH_FM, "GATE_ABOX_QCH_FM", "MUX_AUD_FM", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_QCH_S_BCLK_DSIF, ABOX_QCH_S_BCLK_DSIF, "GATE_ABOX_QCH_S_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_QCH_S_DPP, DPU_QCH_S_DPP, "GATE_DPU_QCH_S_DPP", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_QCH_S_DMA, DPU_QCH_S_DMA, "GATE_DPU_QCH_S_DMA", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_QCH_S_DECON, DPU_QCH_S_DECON, "GATE_DPU_QCH_S_DECON", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_ABOX_QCH, SMMU_ABOX_QCH, "GATE_SMMU_ABOX_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DPU_QCH, SMMU_DPU_QCH, "GATE_SMMU_DPU_QCH", "MUX_CLKCMU_DISPAUD_DISP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_AUD_QCH, WDT_AUD_QCH, "GATE_WDT_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_fsys_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_BUS, MUX_CLKCMU_FSYS_BUS_USER, "MUX_CLKCMU_FSYS_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_EMBD, MUX_CLKCMU_FSYS_MMC_EMBD_USER, "MUX_CLKCMU_FSYS_MMC_EMBD_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_MMC_CARD, MUX_CLKCMU_FSYS_MMC_CARD_USER, "MUX_CLKCMU_FSYS_MMC_CARD_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS_UFS_EMBD, MUX_CLKCMU_FSYS_UFS_EMBD_USER, "MUX_CLKCMU_FSYS_UFS_EMBD_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_MMC_CARD_QCH, MMC_CARD_QCH, "GATE_MMC_CARD_QCH", "MUX_CLKCMU_FSYS_MMC_CARD_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MMC_EMBD_QCH, MMC_EMBD_QCH, "GATE_MMC_EMBD_QCH", "MUX_CLKCMU_FSYS_MMC_EMBD_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_RTIC_QCH, RTIC_QCH, "GATE_RTIC_QCH", "MUX_CLKCMU_FSYS_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SSS_QCH, SSS_QCH, "GATE_SSS_QCH", "MUX_CLKCMU_FSYS_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_QCH_UFS, UFS_EMBD_QCH_UFS, "GATE_UFS_EMBD_QCH_UFS", "MUX_CLKCMU_FSYS_UFS_EMBD_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_QCH_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_QCH_FMP", "MUX_CLKCMU_FSYS_UFS_EMBD_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_g2d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "MUX_CLKCMU_G2D_G2D_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, "MUX_CLKCMU_G2D_MSCL_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_G2D_QCH, G2D_QCH, "GATE_G2D_QCH", "MUX_CLKCMU_G2D_G2D_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_JPEG_QCH, JPEG_QCH, "GATE_JPEG_QCH", "MUX_CLKCMU_G2D_MSCL_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MSCL_QCH, MSCL_QCH, "GATE_MSCL_QCH", "MUX_CLKCMU_G2D_MSCL_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_G2D_QCH, SYSMMU_G2D_QCH, "GATE_SYSMMU_G2D_QCH", "MUX_CLKCMU_G2D_G2D_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_g3d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_G3D_QCH, G3D_QCH, "GATE_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_isp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISP_BUS, MUX_CLKCMU_ISP_BUS_USER, "MUX_CLKCMU_ISP_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISP_GDC, MUX_CLKCMU_ISP_GDC_USER, "MUX_CLKCMU_ISP_GDC_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISP_VRA, MUX_CLKCMU_ISP_VRA_USER, "MUX_CLKCMU_ISP_VRA_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_ISP, IS6P10P0_ISP_QCH_S_ISP_ISP, "GATE_IS6P10P0_ISP_QCH_S_ISP_ISP", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC, IS6P10P0_ISP_QCH_S_ISP_MCSC, "GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_VRA, IS6P10P0_ISP_QCH_S_ISP_VRA, "GATE_IS6P10P0_ISP_QCH_S_ISP_VRA", "MUX_CLKCMU_ISP_VRA_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_GDC, IS6P10P0_ISP_QCH_S_ISP_GDC, "GATE_IS6P10P0_ISP_QCH_S_ISP_GDC", "MUX_CLKCMU_ISP_GDC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1", "MUX_CLKCMU_ISP_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_mfc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC_USER, "MUX_CLKCMU_MFC_MFC_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, "MUX_CLKCMU_MFC_WFD_USER", "MUX_CLKCMU_MFC_MFC_USER", 0, 0, NULL),
+ HWACG_VCLK(GATE_MFC_QCH, MFC_QCH, "GATE_MFC_QCH", "MUX_CLKCMU_MFC_MFC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_MFCD0_QCH, SYSMMU_MFCD0_QCH, "GATE_SYSMMU_MFCD0_QCH", "MUX_CLKCMU_MFC_MFC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_MFCD1_QCH, SYSMMU_MFCD1_QCH, "GATE_SYSMMU_MFCD1_QCH", "MUX_CLKCMU_MFC_MFC_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WFD_QCH, WFD_QCH, "GATE_WFD_QCH", "MUX_CLKCMU_MFC_WFD_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_peri_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERI_UART, MUX_CLKCMU_PERI_UART_USER, "UMUX_CLKCMU_PERI_UART", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS_USER, "UMUX_CLKCMU_PERI_BUS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_0_QCH, CAMI2C_0_QCH, "GATE_CAMI2C_0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_1_QCH, CAMI2C_1_QCH, "GATE_CAMI2C_1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_2_QCH, CAMI2C_2_QCH, "GATE_CAMI2C_2_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CAMI2C_3_QCH, CAMI2C_3_QCH, "GATE_CAMI2C_3_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_0_QCH, I2C_0_QCH, "GATE_I2C_0_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_1_QCH, I2C_1_QCH, "GATE_I2C_1_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_2_QCH, I2C_2_QCH, "GATE_I2C_2_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_3_QCH, I2C_3_QCH, "GATE_I2C_3_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_4_QCH, I2C_4_QCH, "GATE_I2C_4_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_5_QCH, I2C_5_QCH, "GATE_I2C_5_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_6_QCH, I2C_6_QCH, "GATE_I2C_6_QCH", "UMUX_CLKCMU_PERI_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MCT_QCH, MCT_QCH, "GATE_MCT_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_TOP_QCH, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM_MOTOR_QCH, PWM_MOTOR_QCH, "GATE_PWM_MOTOR_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_0_QCH, SPI_0_QCH, "GATE_SPI_0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_1_QCH, SPI_1_QCH, "GATE_SPI_1_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_2_QCH, SPI_2_QCH, "GATE_SPI_2_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_QCH, UART_QCH, "GATE_UART_QCH", "UMUX_CLKCMU_PERI_UART", 0, 0, "console-pclk0"),
+ HWACG_VCLK(GATE_USI00_I2C_QCH, USI00_I2C_QCH, "GATE_USI00_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI00_USI_QCH, USI00_USI_QCH, "GATE_USI00_USI_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER0_QCH, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0_QCH", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER1_QCH, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1_QCH", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_shub_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_SHUB_BUS, MUX_CLKCMU_SHUB_BUS_USER, "MUX_CLKCMU_SHUB_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(MUX_SHUB_I2C, MUX_CLK_SHUB_I2C, "MUX_SHUB_I2C", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_SHUB_USI00, MUX_CLK_SHUB_USI00, "MUX_SHUB_USI00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(MUX_SHUB_USI01, MUX_CLK_SHUB_USI01, "MUX_SHUB_USI01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_CM4_SHUB_QCH, CM4_SHUB_QCH, "GATE_CM4_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_SHUB00_QCH, I2C_SHUB00_QCH, "GATE_I2C_SHUB00_QCH", "MUX_SHUB_I2C", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA_SHUB_QCH, PDMA_SHUB_QCH, "GATE_PDMA_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM_SHUB_QCH, PWM_SHUB_QCH, "GATE_PWM_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TIMER_SHUB_QCH, TIMER_SHUB_QCH, "GATE_TIMER_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_SHUB00_QCH, USI_SHUB00_QCH, "GATE_USI_SHUB00_QCH", "MUX_SHUB_USI00", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_SHUB_QCH, WDT_SHUB_QCH, "GATE_WDT_SHUB_QCH", "MUX_CLKCMU_SHUB_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_usb_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_USB_USBDRD30, MUX_CLKCMU_USB_USB30DRD, "MUX_CLKCMU_USB_USB30DRD", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_USB_DPGTC, MUX_CLKCMU_USB_DPGTC, "MUX_CLKCMU_USB_DPGTC", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_DP_LINK_QCH_DP, DP_LINK_QCH_DP, "GATE_DP_LINK_QCH_DP", "MUX_CLKCMU_USB_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DP_LINK_QCH_GTC, DP_LINK_QCH_GTC, "GATE_DP_LINK_QCH_GTC", "MUX_CLKCMU_USB_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USB30, USB30DRD_QCH_USB30, "GATE_USB30DRD_QCH_USB30", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USBPHY_30CTRL_0, USB30DRD_QCH_USBPHY_30CTRL_0, "GATE_USB30DRD_QCH_USBPHY_30CTRL_0", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USBPHY_30CTRL_1, USB30DRD_QCH_USBPHY_30CTRL_1, "GATE_USB30DRD_QCH_USBPHY_30CTRL_1", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_QCH_USBPHY_20CTRL, USB30DRD_QCH_USBPHY_20CTRL, "GATE_USB30DRD_QCH_USBPHY_20CTRL", "MUX_CLKCMU_USB_USB30DRD", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_vipx1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VIPX1_BUS, MUX_CLKCMU_VIPX1_BUS_USER, "MUX_CLKCMU_VIPX1_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_SMMU_D_VIPX1_QCH, SMMU_D_VIPX1_QCH, "GATE_SMMU_D_VIPX1_QCH", "MUX_CLKCMU_VIPX1_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VIPX1_QCH, VIPX1_QCH, "GATE_VIPX1_QCH", "MUX_CLKCMU_VIPX1_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9610_vipx2_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VIPX2_BUS, MUX_CLKCMU_VIPX2_BUS_USER, "MUX_CLKCMU_VIPX2_BUS_USER", NULL, 0, 0, NULL),
+ HWACG_VCLK(GATE_SMMU_D_VIPX2_QCH, SMMU_D_VIPX2_QCH, "GATE_SMMU_D_VIPX2_QCH", "MUX_CLKCMU_VIPX2_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VIPX2_QCH, VIPX2_QCH, "GATE_VIPX2_QCH", "MUX_CLKCMU_VIPX2_BUS_USER", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VIPX2_QCH_LOCAL, VIPX2_QCH_LOCAL, "GATE_VIPX2_QCH_LOCAL", "MUX_CLKCMU_VIPX2_BUS_USER", 0, VCLK_GATE, NULL),
+};
+
+/* Special VCLK */
+struct init_vclk exynos9610_dispaud_vclks[] __initdata = {
+ VCLK(DOUT_CLK_AUD_ACLK, DIV_CLK_AUD_BUS, "DOUT_CLK_AUD_ACLK", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_CLK_AUD_AUDIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_DSIF, DIV_CLK_AUD_DSIF, "DOUT_CLK_AUD_DSIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_CLK_AUD_UAIF0", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_CLK_AUD_UAIF1", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_AUD_UAIF2", 0, 0, NULL),
+ VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
+ VCLK(DOUT_CLK_AUD_FM, DIV_CLK_AUD_FM, "DOUT_CLK_AUD_FM", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_cmgp_vclks[] __initdata = {
+ VCLK(CMGP00_USI, DIV_CLK_CMGP_USI00, "CMGP00_USI", 0, 0, NULL),
+ VCLK(CMGP01_USI, DIV_CLK_CMGP_USI01, "CMGP01_USI", 0, 0, NULL),
+ VCLK(CMGP02_USI, DIV_CLK_CMGP_USI02, "CMGP02_USI", 0, 0, NULL),
+ VCLK(CMGP03_USI, DIV_CLK_CMGP_USI03, "CMGP03_USI", 0, 0, NULL),
+ VCLK(CMGP04_USI, DIV_CLK_CMGP_USI04, "CMGP04_USI", 0, 0, NULL),
+ VCLK(CMGP_I2C, DIV_CLK_CMGP_I2C, "CMGP_I2C", 0, 0, NULL),
+ VCLK(CMGP_ADC, DIV_CLK_CMGP_ADC, "CMGP_ADC", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_fsys_vclks[] __initdata = {
+ VCLK(MMC_EMBD, CLKCMU_FSYS_MMC_EMBD, "MMC_EMBD", 0, 0, NULL),
+ VCLK(MMC_CARD, CLKCMU_FSYS_MMC_CARD, "MMC_CARD", 0, 0, NULL),
+ VCLK(UFS_EMBD, CLKCMU_FSYS_BUS, "UFS_EMBD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_usb_vclks[] __initdata = {
+ VCLK(USB30DRD, VCLK_CLKCMU_USB_USB30DRD, "USB30DRD", 0, 0, NULL),
+ VCLK(DP_LINK, VCLK_CLKCMU_USB_DPGTC, "DP_LINK", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_peri_vclks[] __initdata = {
+ VCLK(UART, CLKCMU_PERI_UART, "UART", 0, 0, "console-sclk0"),
+ VCLK(I2C, DIV_CLK_PERI_I2C, "I2C", 0, 0, NULL),
+ VCLK(SPI0, DIV_CLK_PERI_SPI0, "SPI0", 0, 0, NULL),
+ VCLK(SPI1, DIV_CLK_PERI_SPI1, "SPI1", 0, 0, NULL),
+ VCLK(SPI2, DIV_CLK_PERI_SPI2, "SPI2", 0, 0, NULL),
+ VCLK(USI_I2C, DIV_CLK_PERI_USI_I2C, "USI_I2C", 0, 0, NULL),
+ VCLK(USI_USI, DIV_CLK_PERI_USI_USI, "USI_USI", 0, 0, NULL),
+};
+
+struct init_vclk exynos9610_top_vclks[] __initdata = {
+ VCLK(CIS_CLK0, CLKCMU_CIS_CLK0, "CIS_CLK0", 0, 0, NULL),
+ VCLK(CIS_CLK1, CLKCMU_CIS_CLK1, "CIS_CLK1", 0, 0, NULL),
+ VCLK(CIS_CLK2, CLKCMU_CIS_CLK2, "CIS_CLK2", 0, 0, NULL),
+ VCLK(CIS_CLK3, CLKCMU_CIS_CLK3, "CIS_CLK3", 0, 0, NULL),
+};
+
+static struct init_vclk exynos9610_clkout_vclks[] __initdata = {
+ VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
+ VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ {.compatible = "samsung,exynos9610-oscclk", .data = (void *)0},
+ {},
+};
+
+void exynos9610_vclk_init(void)
+{
+ cal_clk_setrate(DIV_CLK_AUD_FM, 40000);
+}
+
+/* register exynos9610 clocks */
+void __init exynos9610_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ int ret;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ ret = cal_if_init(np);
+ if (ret)
+ panic("%s: unable to initialize cal-if\n", __func__);
+
+ exynos9610_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (!exynos9610_clk_provider)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_register_of_fixed_ext(exynos9610_clk_provider, exynos9610_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos9610_fixed_rate_ext_clks),
+ ext_clk_match);
+ /* register HWACG vclk */
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_apm_hwacg_vclks, ARRAY_SIZE(exynos9610_apm_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_cam_hwacg_vclks, ARRAY_SIZE(exynos9610_cam_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_cmgp_hwacg_vclks, ARRAY_SIZE(exynos9610_cmgp_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_top_hwacg_vclks, ARRAY_SIZE(exynos9610_top_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_core_hwacg_vclks, ARRAY_SIZE(exynos9610_core_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_dispaud_hwacg_vclks, ARRAY_SIZE(exynos9610_dispaud_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_fsys_hwacg_vclks, ARRAY_SIZE(exynos9610_fsys_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_g2d_hwacg_vclks, ARRAY_SIZE(exynos9610_g2d_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_g3d_hwacg_vclks, ARRAY_SIZE(exynos9610_g3d_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_isp_hwacg_vclks, ARRAY_SIZE(exynos9610_isp_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_mfc_hwacg_vclks, ARRAY_SIZE(exynos9610_mfc_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_peri_hwacg_vclks, ARRAY_SIZE(exynos9610_peri_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_shub_hwacg_vclks, ARRAY_SIZE(exynos9610_shub_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_usb_hwacg_vclks, ARRAY_SIZE(exynos9610_usb_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_vipx1_hwacg_vclks, ARRAY_SIZE(exynos9610_vipx1_hwacg_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_vipx2_hwacg_vclks, ARRAY_SIZE(exynos9610_vipx2_hwacg_vclks));
+
+ /* register special vclk */
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_dispaud_vclks, ARRAY_SIZE(exynos9610_dispaud_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_cmgp_vclks, ARRAY_SIZE(exynos9610_cmgp_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_fsys_vclks, ARRAY_SIZE(exynos9610_fsys_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_usb_vclks, ARRAY_SIZE(exynos9610_usb_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_peri_vclks, ARRAY_SIZE(exynos9610_peri_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_top_vclks, ARRAY_SIZE(exynos9610_top_vclks));
+ samsung_register_vclk(exynos9610_clk_provider, exynos9610_clkout_vclks, ARRAY_SIZE(exynos9610_clkout_vclks));
+
+ clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
+
+ samsung_clk_of_add_provider(np, exynos9610_clk_provider);
+
+ late_time_init = exynos9610_vclk_init;
+
+ pr_info("EXYNOS9610: Clock setup completed\n");
+}
+
+CLK_OF_DECLARE(exynos9610_clk, "samsung,exynos9610-clock", exynos9610_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos9810 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <soc/samsung/cal-if.h>
+#include <dt-bindings/clock/exynos9810.h>
+
+#include "../../soc/samsung/cal-if/exynos9810/cmucal-vclk.h"
+#include "../../soc/samsung/cal-if/exynos9810/cmucal-node.h"
+#include "../../soc/samsung/cal-if/exynos9810/cmucal-qch.h"
+#include "../../soc/samsung/cal-if/exynos9810/clkout_exynos9810.h"
+#include "composite.h"
+
+static struct samsung_clk_provider *exynos9810_clk_provider;
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate exynos9810_fixed_rate_ext_clks[] __initdata = {
+ FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
+};
+
+/* HWACG VCLK */
+struct init_vclk exynos9810_apm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_DLL, MUX_DLL_USER, "UMUX_DLL", NULL, 0, VCLK_GATE, NULL),
+
+ HWACG_VCLK(GATE_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBE", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GREBE_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBE_DBG", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_INTMEM, INTMEM_QCH, "GATE_INTMEM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CHUB, MAILBOX_AP2CHUB_QCH, "GATE_MAILBOX_AP2CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP, MAILBOX_AP2CP_QCH, "GATE_MAILBOX_AP2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP_S, MAILBOX_AP2CP_S_QCH, "GATE_MAILBOX_AP2CP_S", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2GNSS, MAILBOX_AP2GNSS_QCH, "GATE_MAILBOX_AP2GNSS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2VTS, MAILBOX_AP2VTS_QCH, "GATE_MAILBOX_AP2VTS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2AP, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CHUB, MAILBOX_APM2CHUB_QCH, "GATE_MAILBOX_APM2CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CP, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2GNSS, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CHUB2CP, MAILBOX_CHUB2CP_QCH, "GATE_MAILBOX_CHUB2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_GNSS2CHUB, MAILBOX_GNSS2CHUB_QCH, "GATE_MAILBOX_GNSS2CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_GNSS2CP, MAILBOX_GNSS2CP_QCH, "GATE_MAILBOX_GNSS2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PEM, PEM_QCH, "GATE_PEM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_APM, SPEEDY_APM_QCH, "GATE_SPEEDY_APM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_SUB_APM, SPEEDY_SUB_APM_QCH, "GATE_SPEEDY_SUB_APM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_APM, WDT_APM_QCH, "GATE_WDT_APM", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_abox_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_ABOX_ACLK, ABOX_QCH_ACLK, "GATE_ABOX_ACLK", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK_DSIF, ABOX_QCH_BCLK_DSIF, "GATE_ABOX_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK0, ABOX_QCH_BCLK0, "GATE_ABOX_BCLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK1, ABOX_QCH_BCLK1, "GATE_ABOX_BCLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK2, ABOX_QCH_BCLK2, "GATE_ABOX_BCLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK3, ABOX_QCH_BCLK3, "GATE_ABOX_BCLK3", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_DUMMY, ABOX_QCH_DUMMY, "GATE_ABOX_DUMMY", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_DMIC, DMIC_QCH, "GATE_ABOX_DMIC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_ABOX, SYSMMU_AUD_QCH, "GATE_SYSMMU_AUD", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_ABOXCPU, WDT_AUD_QCH, "GATE_WDT_AUD", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_bus1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_TREX_P_BUS1, TREX_P_BUS1_QCH, "GATE_TREX_P_BUS1", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_busc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_PDMA0, PDMA0_QCH, "GATE_PDMA0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW, PPFW_QCH, "GATE_PPFW", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SBIC, SBIC_QCH, "GATE_SBIC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SIREX, SIREX_QCH, "GATE_SIREX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPDMA, SPDMA_QCH, "GATE_SPDMA", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_D_BUSC, TREX_D_BUSC_QCH, "GATE_TREX_D_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P_BUSC, TREX_P_BUSC_QCH, "GATE_TREX_P_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_RB_BUSC, TREX_RB_BUSC_QCH, "GATE_TREX_RB_BUSC", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_chub_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_CM4_CHUB, CM4_CHUB_QCH, "GATE_CM4_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CHUB00, I2C_CHUB00_QCH, "GATE_I2C_CHUB00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CHUB01, I2C_CHUB01_QCH, "GATE_I2C_CHUB01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA_CHUB, PDMA_CHUB_QCH, "GATE_PDMA_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM_CHUB, PWM_CHUB_QCH, "GATE_PWM_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TIMER_CHUB, TIMER_CHUB_QCH, "GATE_TIMER_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CHUB00, USI_CHUB00_QCH, "GATE_USI_CHUB00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CHUB01, USI_CHUB01_QCH, "GATE_USI_CHUB01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CHUB, WDT_CHUB_QCH, "GATE_WDT_CHUB", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_cmgp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_ADC_CMGP_S0, ADC_CMGP_QCH_S0, "GATE_ADC_CMGP_S0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_S1, ADC_CMGP_QCH_S1, "GATE_ADC_CMGP_S1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP, ADC_CMGP_QCH_ADC, "GATE_ADC_CMGP_ADC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP00, I2C_CMGP00_QCH, "GATE_I2C_CMGP00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP01, I2C_CMGP01_QCH, "GATE_I2C_CMGP01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP02, I2C_CMGP02_QCH, "GATE_I2C_CMGP02", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP03, I2C_CMGP03_QCH, "GATE_I2C_CMGP03", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP00, USI_CMGP00_QCH, "GATE_USI_CMGP00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP01, USI_CMGP01_QCH, "GATE_USI_CMGP01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP02, USI_CMGP02_QCH, "GATE_USI_CMGP02", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP03, USI_CMGP03_QCH, "GATE_USI_CMGP03", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_cmu_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_CMU_CMUREF, CMU_CMU_CMUREF_QCH, "GATE_CMU_CMUREF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK0, "GATE_CIS_CLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK1, "GATE_CIS_CLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK2, "GATE_CIS_CLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK3, DFTMUX_TOP_QCH_CIS_CLK3, "GATE_CIS_CLK3", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP, OTP_QCH, "GATE_OTP", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_core_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_TREX_D_CORE, TREX_D_CORE_QCH, "GATE_TREX_D_CORE", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P0_CORE, TREX_P0_CORE_QCH, "GATE_TREX_P0_CORE", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P1_CORE, TREX_P1_CORE_QCH, "GATE_TREX_P1_CORE", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dcf_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCF_BUS, MUX_CLKCMU_DCF_BUS_USER, "UMUX_CLKCMU_DCF_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_DCF_CIP, IS_DCF_QCH_CIP, "GATE_IS_DCF_CIP", "UMUX_CLKCMU_DCF_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCF_C2SYNC_2SLV, IS_DCF_QCH_C2SYNC_2SLV, "GATE_IS_DCF_C2SYNC_2SLV", "UMUX_CLKCMU_DCF_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCF_SYSMMU, IS_DCF_QCH_SYSMMU, "GATE_IS_DCF_SYSMMU", "UMUX_CLKCMU_DCF_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dcpost_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCPOST_BUS, MUX_CLKCMU_DCPOST_BUS_USER, "UMUX_CLKCMU_DCPOST_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_DCPOST_CIP2, IS_DCPOST_QCH_CIP2, "GATE_IS_DCPOST_CIP2", "UMUX_CLKCMU_DCPOST_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCPOST_C2SYNC_1SLV_CLK, IS_DCPOST_QCH_C2SYNC_1SLV_CLK, "GATE_IS_DCPOST_C2SYNC_1SLV_CLK", "UMUX_CLKCMU_DCPOST_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dcrd_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCRD_BUS, MUX_CLKCMU_DCRD_BUS_USER, "UMUX_CLKCMU_DCRD_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_DCRD_DCP, IS_DCRD_QCH_DCP, "GATE_IS_DCRD_DCP", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCRD_SYSMMU, IS_DCRD_QCH_SYSMMU, "GATE_IS_DCRD_SYSMMU", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCRD_DCP_C2C, IS_DCRD_QCH_DCP_C2C, "GATE_IS_DCRD_DCP_C2C", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCRD_DCP_DIV2, IS_DCRD_QCH_DCP_DIV2, "GATE_IS_DCRD_DCP_DIV2", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dpu_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS_USER, "UMUX_CLKCMU_DPU_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_DPU, DPU_QCH_DPU, "GATE_DPU_DPU", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_DMA, DPU_QCH_DPU_DMA, "GATE_DPU_DMA", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_DPP, DPU_QCH_DPU_DPP, "GATE_DPU_DPP", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_WB_MUX, DPU_QCH_DPU_WB_MUX, "GATE_DPU_WB_MUX", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD0, SYSMMU_DPUD0_QCH, "GATE_SYSMMU_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD1, SYSMMU_DPUD1_QCH, "GATE_SYSMMU_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD2, SYSMMU_DPUD2_QCH, "GATE_SYSMMU_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dspm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DSPM_BUS, MUX_CLKCMU_DSPM_BUS_USER, "UMUX_CLKCMU_DSPM_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_SCORE_MASTER, SCORE_MASTER_QCH, "GATE_SCORE_MASTER", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DSPM0, SYSMMU_DSPM0_QCH, "GATE_SMMU_DSPM0", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DSPM1, SYSMMU_DSPM1_QCH, "GATE_SMMU_DSPM1", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dsps_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DSPS_BUS, MUX_CLKCMU_DSPS_BUS_USER, "UMUX_CLKCMU_DSPS_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DSPS_AUD, MUX_CLKCMU_DSPS_AUD_USER, "UMUX_CLKCMU_DSPS_AUD", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_SCORE_KNIGHT, SCORE_KNIGHT_QCH, "GATE_SCORE_KNIGHT", "UMUX_CLKCMU_DSPS_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_fsys0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS_USER, "UMUX_CLKCMU_FSYS0_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_UFS_EMBD, MUX_CLKCMU_FSYS0_UFS_EMBD_USER, "UMUX_CLKCMU_FSYS0_UFS_EMBD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_USB30DRD, MUX_CLKCMU_FSYS0_USB30DRD_USER, "UMUX_CLKCMU_FSYS0_USB30DRD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC_USER, "UMUX_CLKCMU_FSYS0_DPGTC", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_USBDP_DEBUG, MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER, "UMUX_CLKCMU_FSYS0_USBDP_DEBUG", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_DP_LINK, DP_LINK_QCH, "GATE_DP_LINK", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DP_LINK_GTC, DP_LINK_QCH_GTC, "GATE_DP_LINK_GTC", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD, UFS_EMBD_QCH, "GATE_UFS_EMBD", "UMUX_CLKCMU_FSYS0_UFS_EMBD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_FMP", "UMUX_CLKCMU_FSYS0_UFS_EMBD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USB30DRD_LINK, USB30DRD_QCH_USB30DRD_LINK, "GATE_USB30DRD_USB30DRD_LINK", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USBPCS, USB30DRD_QCH_USBPCS, "GATE_USB30DRD_USBPCS", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USB30DRD_CTRL, USB30DRD_QCH_USB30DRD_CTRL, "GATE_USB30DRD_USB30DRD_CTRL", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USBDPPHY, USB30DRD_QCH_USBDPPHY, "GATE_USB30DRD_USBDPPHY", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_SOC_PLL, USB30DRD_QCH_SOC_PLL, "GATE_USB30DRD_SOC_PLL", "UMUX_CLKCMU_FSYS0_USBDP_DEBUG", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_fsys1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS_USER, "UMUX_CLKCMU_FSYS1_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE_USER, "UMUX_CLKCMU_FSYS1_PCIE", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD_USER, "UMUX_CLKCMU_FSYS1_MMC_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD_USER, "UMUX_CLKCMU_FSYS1_UFS_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_MMC_CARD, MMC_CARD_QCH, "GATE_MMC_CARD", "UMUX_CLKCMU_FSYS1_MMC_CARD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_MSTR, PCIE_GEN2_QCH_MSTR, "GATE_PCIE_GEN2_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_PCS, PCIE_GEN2_QCH_PCS, "GATE_PCIE_GEN2_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_PHY, PCIE_GEN2_QCH_PHY, "GATE_PCIE_GEN2_PHY", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_DBI, PCIE_GEN2_QCH_DBI, "GATE_PCIE_GEN2_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_APB, PCIE_GEN2_QCH_APB, "GATE_PCIE_GEN2_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_SOCPLL, PCIE_GEN2_QCH_SOCPLL, "GATE_PCIE_GEN2_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_MSTR, PCIE_GEN3_QCH_MSTR, "GATE_PCIE_GEN3_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_PCS, PCIE_GEN3_QCH_PCS, "GATE_PCIE_GEN3_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_DBI, PCIE_GEN3_QCH_DBI, "GATE_PCIE_GEN3_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_APB, PCIE_GEN3_QCH_APB, "GATE_PCIE_GEN3_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_SOCPLL, PCIE_GEN3_QCH_SOCPLL, "GATE_PCIE_GEN3_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_PHY, PCIE_GEN3_QCH_PHY, "GATE_PCIE_GEN3", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_IA_GEN2, PCIE_IA_GEN2_QCH, "GATE_PCIE_IA_GEN2", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_IA_GEN3, PCIE_IA_GEN3_QCH, "GATE_PCIE_IA_GEN3", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_RTIC, RTIC_QCH, "GATE_RTIC", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SSS, SSS_QCH, "GATE_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_FSYS1, SYSMMU_FSYS1_QCH, "GATE_SYSMMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_CARD, UFS_CARD_QCH, "GATE_UFS_CARD", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_CARD_FMP, UFS_CARD_QCH_FMP, "GATE_UFS_CARD_FMP", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_g2d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, "UMUX_CLKCMU_G2D_MSCL", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "UMUX_CLKCMU_G2D_G2D", "UMUX_CLKCMU_G2D_MSCL", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_ASTC, ASTC_QCH, "GATE_ASTC", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_G2D, G2D_QCH, "GATE_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_JPEG, JPEG_QCH, "GATE_JPEG", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MSCL, MSCL_QCH, "GATE_MSCL", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD0, SYSMMU_G2DD0_QCH, "GATE_SMMU_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD1, SYSMMU_G2DD1_QCH, "GATE_SMMU_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD2, SYSMMU_G2DD2_QCH, "GATE_SMMU_G2DD2", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_g3d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_GPU, GPU_QCH, "GATE_GPU", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_isphq_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS_USER, "UMUX_CLKCMU_ISPHQ_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_ISPHQ, IS_ISPHQ_QCH_ISPHQ, "GATE_IS_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_C2COM, IS_ISPHQ_QCH_ISPHQ_C2COM, "GATE_IS_ISPHQ_C2COM", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_SYSMMU, IS_ISPHQ_QCH_SYSMMU_ISPHQ, "GATE_IS_ISPHQ_SYSMMU", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_isplp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS_USER, "UMUX_CLKCMU_ISPLP_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_VRA, MUX_CLKCMU_ISPLP_VRA_USER, "UMUX_CLKCMU_ISPLP_VRA", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_GDC, MUX_CLKCMU_ISPLP_GDC_USER, "UMUX_CLKCMU_ISPLP_GDC", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_ISPLP_MC_SCALER, IS_ISPLP_QCH_MC_SCALER, "GATE_IS_ISPLP_MC_SCALER", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP, IS_ISPLP_QCH_ISPLP, "GATE_IS_ISPLP_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_VRA, IS_ISPLP_QCH_VRA, "GATE_IS_ISPLP_VRA", "UMUX_CLKCMU_ISPLP_VRA", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_GDC, IS_ISPLP_QCH_GDC, "GATE_IS_ISPLP_GDC", "UMUX_CLKCMU_ISPLP_GDC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_C2, IS_ISPLP_QCH_ISPLP_C2, "GATE_IS_ISPLP_ISPLP_C2", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_SYSMMU_ISPLP0, IS_ISPLP_QCH_SYSMMU_ISPLP0, "GATE_IS_ISPLP_SYSMMU_ISPLP0", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_SYSMMU_ISPLP1, IS_ISPLP_QCH_SYSMMU_ISPLP1, "GATE_IS_ISPLP_SYSMMU_ISPLP1", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_isppre_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPPRE_BUS, MUX_CLKCMU_ISPPRE_BUS_USER, "UMUX_CLKCMU_ISPPRE_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS0, IS_ISPPRE_QCH_CSIS0, "GATE_IS_ISPPRE_CSIS0", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS1, IS_ISPPRE_QCH_CSIS1, "GATE_IS_ISPPRE_CSIS1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS2, IS_ISPPRE_QCH_CSIS2, "GATE_IS_ISPPRE_CSIS2", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS3, IS_ISPPRE_QCH_CSIS3, "GATE_IS_ISPPRE_CSIS3", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_PDP_DMA, IS_ISPPRE_QCH_PDP_DMA, "GATE_IS_ISPPRE_PDP_DMA", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_SYSMMU, IS_ISPPRE_QCH_SYSMMU_ISPPRE, "GATE_IS_ISPPRE_SYSMMU", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_3AA, IS_ISPPRE_QCH_3AA, "GATE_IS_ISPPRE_3AA", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_3AAM, IS_ISPPRE_QCH_3AAM, "GATE_IS_ISPPRE_3AAM", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_PDP_CORE0, IS_ISPPRE_QCH_PDP_CORE0, "GATE_IS_ISPPRE_PDP_CORE0", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_PDP_CORE1, IS_ISPPRE_QCH_PDP_CORE1, "GATE_IS_ISPPRE_PDP_CORE1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_iva_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS_USER, "UMUX_CLKCMU_IVA_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IVA, IVA_QCH_IVA, "GATE_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA_DEBUG, IVA_QCH_IVA_DEBUG, "GATE_IVA_DEBUG", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA_INTMEM, IVA_INTMEM_QCH, "GATE_IVA_INTMEM", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_IVA, SYSMMU_IVA_QCH, "GATE_SMMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_RB_IVA, TREX_RB_IVA_QCH, "GATE_TREX_RB_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_mfc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_MFC_BUS, MUX_CLKCMU_MFC_BUS_USER, "UMUX_CLKCMU_MFC_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, "UMUX_CLKCMU_MFC_WFD", "UMUX_CLKCMU_MFC_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_MFC, MFC_QCH, "GATE_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WFD, WFD_QCH, "GATE_WFD", "UMUX_CLKCMU_MFC_WFD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_MFCD0, SYSMMU_MFCD0_QCH, "GATE_SMMU_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_MFCD1, SYSMMU_MFCD1_QCH, "GATE_SMMU_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_peric0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS_USER, "UMUX_CLKCMU_PERIC0_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_IP, MUX_CLKCMU_PERIC0_IP_USER, "UMUX_CLKCMU_PERIC0_IP", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_PWM, PWM_QCH, "GATE_PWM", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_DBG, UART_DBG_QCH, "GATE_UART_DBG", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, "console-pclk0"),
+ HWACG_VCLK(GATE_USI00_I2C, USI00_I2C_QCH, "GATE_USI00_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI00, USI00_USI_QCH, "GATE_USI00_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI01_I2C, USI01_I2C_QCH, "GATE_USI01_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI01, USI01_USI_QCH, "GATE_USI01_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI02_I2C, USI02_I2C_QCH, "GATE_USI02_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI02, USI02_USI_QCH, "GATE_USI02_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI03_I2C, USI03_I2C_QCH, "GATE_USI03_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI03, USI03_USI_QCH, "GATE_USI03_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI04_I2C, USI04_I2C_QCH, "GATE_USI04_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI04, USI04_USI_QCH, "GATE_USI04_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI05_I2C, USI05_I2C_QCH, "GATE_USI05_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI05, USI05_USI_QCH, "GATE_USI05_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI12_I2C, USI12_I2C_QCH, "GATE_USI12_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI12, USI12_USI_QCH, "GATE_USI12_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI13_I2C, USI13_I2C_QCH, "GATE_USI13_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI13, USI13_USI_QCH, "GATE_USI13_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI14_I2C, USI14_I2C_QCH, "GATE_USI14_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI14, USI14_USI_QCH, "GATE_USI14_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_peric1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS_USER, "UMUX_CLKCMU_PERIC1_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_IP, MUX_CLKCMU_PERIC1_IP_USER, "UMUX_CLKCMU_PERIC1_IP", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_I2C_CAM0, I2C_CAM0_QCH, "GATE_I2C_CAM0", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CAM1, I2C_CAM1_QCH, "GATE_I2C_CAM1", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CAM2, I2C_CAM2_QCH, "GATE_I2C_CAM2", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CAM3, I2C_CAM3_QCH, "GATE_I2C_CAM3", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_CAM0, SPI_CAM0_QCH, "GATE_SPI_CAM0", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_BT, UART_BT_QCH, "GATE_UART_BT", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI06_I2C, USI06_I2C_QCH, "GATE_USI06_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI06, USI06_USI_QCH, "GATE_USI06", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI07_I2C, USI07_I2C_QCH, "GATE_USI07_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI07, USI07_USI_QCH, "GATE_USI07", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI08_I2C, USI08_I2C_QCH, "GATE_USI08_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI08, USI08_USI_QCH, "GATE_USI08", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI09_I2C, USI09_I2C_QCH, "GATE_USI09_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI09, USI09_USI_QCH, "GATE_USI09", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI10_I2C, USI10_I2C_QCH, "GATE_USI10_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI10, USI10_USI_QCH, "GATE_USI10", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI11_I2C, USI11_I2C_QCH, "GATE_USI11_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI11, USI11_USI_QCH, "GATE_USI11", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_peris_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS_USER, "UMUX_CLKCMU_PERIS_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BUSIF_TMU, BUSIF_TMU_QCH, "GATE_BUSIF_TMU", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GIC, GIC_QCH, "GATE_GIC", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MCT, MCT_QCH, "GATE_MCT", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_BIRA, OTP_CON_BIRA_QCH, "GATE_OTP_CON_BIRA", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_TOP, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER0, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER1, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_vts_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VTS_BUS, MUX_CLKCMU_VTS_BUS_USER, "UMUX_CLKCMU_VTS_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_VTS_DLL, MUX_CLKCMU_VTS_DLL_USER, "UMUX_CLKCMU_VTS_DLL", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_VTS_CPU, CORTEXM4INTEGRATION_QCH_CPU, "GATE_CORTEXM4_CPU", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VTS_DMIC_IF, DMIC_IF_QCH_DMIC_CLK, "GATE_DMIC_IF", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HWACG_SYS_DMIC0, HWACG_SYS_DMIC0_QCH, "GATE_HWACG_SYS_DMIC0", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HWACG_SYS_DMIC1, HWACG_SYS_DMIC1_QCH, "GATE_HWACG_SYS_DMIC1", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_VTS2CHUB, MAILBOX_VTS2CHUB_QCH, "GATE_MAILBOX_VTS2CHUB", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_VTS, WDT_VTS_QCH, "GATE_WDT_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_U_DMIC_CLK_MUX, U_DMIC_CLK_MUX_QCH, "GATE_U_DMIC_CLK_MUX", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+};
+
+/* Special VCLK */
+struct init_vclk exynos9810_apm_vclks[] __initdata = {
+ VCLK(APM_DLL_CMGP, CLKCMU_APM_DLL_CMGP, "APM_DLL_CMGP", 0, 0, NULL),
+ VCLK(APM_DLL_VTS, CLKCMU_APM_DLL_VTS, "APM_DLL_VTS", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_abox_vclks[] __initdata = {
+ VCLK(DOUT_CLK_ABOX_ACLK, DIV_CLK_AUD_BUS, "DOUT_CLK_ABOX_ACLK", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_CLK_ABOX_AUDIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_DSIF, DIV_CLK_AUD_DSIF, "DOUT_CLK_ABOX_DSIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_DMIC, DIV_CLK_AUD_DMIC, "DOUT_CLK_ABOX_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_CLK_ABOX_UAIF0", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_CLK_ABOX_UAIF1", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_ABOX_UAIF2", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF3, DIV_CLK_AUD_UAIF3, "DOUT_CLK_ABOX_UAIF3", 0, 0, NULL),
+ VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_chub_vclks[] __initdata = {
+ VCLK(CHUB_USI00, DIV_CLK_CHUB_USI00, "CHUB_USI00", 0, 0, NULL),
+ VCLK(CHUB_USI01, DIV_CLK_CHUB_USI01, "CHUB_USI01", 0, 0, NULL),
+ VCLK(CHUB_USI_I2C, DIV_CLK_CHUB_I2C, "CHUB_USI_I2C", 0, 0, NULL),
+ VCLK(CHUB_TIMER_FCLK, CLK_CHUB_TIMER_FCLK, "CHUB_TIMER_FCLK", 0, 0, NULL),
+ VCLK(CHUB_BUS, DIV_CLK_CHUB_BUS, "CHUB_BUS", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_cmgp_vclks[] __initdata = {
+ VCLK(USI_CMGP00, DIV_CLK_USI_CMGP00, "USI_CMGP00", 0, 0, NULL),
+ VCLK(USI_CMGP01, DIV_CLK_USI_CMGP01, "USI_CMGP01", 0, 0, NULL),
+ VCLK(USI_CMGP02, DIV_CLK_USI_CMGP02, "USI_CMGP02", 0, 0, NULL),
+ VCLK(USI_CMGP03, DIV_CLK_USI_CMGP03, "USI_CMGP03", 0, 0, NULL),
+ VCLK(CMGP_USI_I2C, DIV_CLK_I2C_CMGP, "CMGP_USI_I2C", 0, 0, NULL),
+ VCLK(CMGP_ADC, DIV_CLK_CMGP_ADC, "CMGP_ADC", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_fsys0_vclks[] __initdata = {
+ VCLK(UFS_EMBD, VCLK_CLK_FSYS0_UFS_EMBD_BLK_CMU, "UFS_EMBD", 0, 0, NULL),
+ VCLK(DPGTC, VCLK_CLK_FSYS0_DPGTC_BLK_CMU, "DPGTC", 0, 0, NULL),
+ VCLK(USB30DRD, VCLK_CLK_FSYS0_USB30DRD_BLK_CMU, "USB30DRD", 0, 0, NULL),
+ VCLK(USBDP_DEBUG_USER, VCLK_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_BLK_CMU, "USBDP_DEBUG_USER", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_fsys1_vclks[] __initdata = {
+ VCLK(MMC_CARD, CLKCMU_FSYS1_MMC_CARD, "MMC_CARD", 0, 0, NULL),
+ VCLK(UFS_CARD, VCLK_CLK_FSYS1_UFS_CARD_BLK_CMU, "UFS_CARD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_peric0_vclks[] __initdata = {
+ VCLK(UART_DBG, DIV_CLK_PERIC0_UART_DBG, "UART_DBG", 0, 0, "console-sclk0"),
+ VCLK(USI00, DIV_CLK_PERIC0_USI00_USI, "USI00_USI", 0, 0, NULL),
+ VCLK(USI01, DIV_CLK_PERIC0_USI01_USI, "USI01_USI", 0, 0, NULL),
+ VCLK(USI02, DIV_CLK_PERIC0_USI02_USI, "USI02_USI", 0, 0, NULL),
+ VCLK(USI03, DIV_CLK_PERIC0_USI03_USI, "USI03_USI", 0, 0, NULL),
+ VCLK(USI04, DIV_CLK_PERIC0_USI04_USI, "USI04_USI", 0, 0, NULL),
+ VCLK(USI05, DIV_CLK_PERIC0_USI05_USI, "USI05_USI", 0, 0, NULL),
+ VCLK(USI12, DIV_CLK_PERIC0_USI12_USI, "USI12_USI", 0, 0, NULL),
+ VCLK(USI13, DIV_CLK_PERIC0_USI13_USI, "USI13_USI", 0, 0, NULL),
+ VCLK(USI14, DIV_CLK_PERIC0_USI14_USI, "USI14_USI", 0, 0, NULL),
+ VCLK(PERIC0_USI_I2C, DIV_CLK_PERIC0_USI_I2C, "PERIC0_USI_I2C", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_peric1_vclks[] __initdata = {
+ VCLK(UART_BT, DIV_CLK_PERIC1_UART_BT, "UART_BT", 0, 0, NULL),
+ VCLK(I2C_CAM0, DIV_CLK_PERIC1_I2C_CAM0, "I2C_CAM0", 0, 0, NULL),
+ VCLK(I2C_CAM1, DIV_CLK_PERIC1_I2C_CAM1, "I2C_CAM1", 0, 0, NULL),
+ VCLK(I2C_CAM2, DIV_CLK_PERIC1_I2C_CAM2, "I2C_CAM2", 0, 0, NULL),
+ VCLK(I2C_CAM3, DIV_CLK_PERIC1_I2C_CAM3, "I2C_CAM3", 0, 0, NULL),
+ VCLK(SPI_CAM0, DIV_CLK_PERIC1_SPI_CAM0, "SPI_CAM0", 0, 0, NULL),
+ VCLK(USI06, DIV_CLK_PERIC1_USI06_USI, "USI06", 0, 0, NULL),
+ VCLK(USI07, DIV_CLK_PERIC1_USI07_USI, "USI07", 0, 0, NULL),
+ VCLK(USI08, DIV_CLK_PERIC1_USI08_USI, "USI08", 0, 0, NULL),
+ VCLK(USI09, DIV_CLK_PERIC1_USI09_USI, "USI09", 0, 0, NULL),
+ VCLK(USI10, DIV_CLK_PERIC1_USI10_USI, "USI10", 0, 0, NULL),
+ VCLK(USI11, DIV_CLK_PERIC1_USI11_USI, "USI11", 0, 0, NULL),
+ VCLK(PERIC1_USI_I2C, DIV_CLK_PERIC1_USI_I2C, "PERIC1_USI_I2C", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_cmu_vclks[] __initdata = {
+ VCLK(CIS_CLK0, CLKCMU_CIS_CLK0, "CIS_CLK0", 0, 0, NULL),
+ VCLK(CIS_CLK1, CLKCMU_CIS_CLK1, "CIS_CLK1", 0, 0, NULL),
+ VCLK(CIS_CLK2, CLKCMU_CIS_CLK2, "CIS_CLK2", 0, 0, NULL),
+ VCLK(CIS_CLK3, CLKCMU_CIS_CLK3, "CIS_CLK3", 0, 0, NULL),
+ VCLK(HPM, VCLK_CLKCMU_HPM_BLK_CMU, "HPM", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_vts_vclks[] __initdata = {
+ VCLK(DOUT_CLK_VTS_DMICIF, DIV_CLK_VTS_DMIC_IF, "DOUT_CLK_VTS_DMICIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC, "DOUT_CLK_VTS_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMIC_DIV2, "DOUT_CLK_VTS_DMIC_DIV2", 0, 0, NULL),
+};
+
+static struct init_vclk exynos9810_clkout_vclks[] __initdata = {
+ VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
+ VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ {.compatible = "samsung,exynos9810-oscclk", .data = (void *)0},
+ {},
+};
+
+void exynos9810_vclk_init(void)
+{
+ /* Common clock init */
+}
+
+/* register exynos9810 clocks */
+void __init exynos9810_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ int ret;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ ret = cal_if_init(np);
+ if (ret)
+ panic("%s: unable to initialize cal-if\n", __func__);
+
+ exynos9810_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (!exynos9810_clk_provider)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_register_of_fixed_ext(exynos9810_clk_provider, exynos9810_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos9810_fixed_rate_ext_clks),
+ ext_clk_match);
+ /* register HWACG vclk */
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_apm_hwacg_vclks, ARRAY_SIZE(exynos9810_apm_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_abox_hwacg_vclks, ARRAY_SIZE(exynos9810_abox_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_bus1_hwacg_vclks, ARRAY_SIZE(exynos9810_bus1_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_busc_hwacg_vclks, ARRAY_SIZE(exynos9810_busc_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_chub_hwacg_vclks, ARRAY_SIZE(exynos9810_chub_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmgp_hwacg_vclks, ARRAY_SIZE(exynos9810_cmgp_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmu_hwacg_vclks, ARRAY_SIZE(exynos9810_cmu_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_core_hwacg_vclks, ARRAY_SIZE(exynos9810_core_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dcf_hwacg_vclks, ARRAY_SIZE(exynos9810_dcf_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dcpost_hwacg_vclks, ARRAY_SIZE(exynos9810_dcpost_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dcrd_hwacg_vclks, ARRAY_SIZE(exynos9810_dcrd_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dpu_hwacg_vclks, ARRAY_SIZE(exynos9810_dpu_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dspm_hwacg_vclks, ARRAY_SIZE(exynos9810_dspm_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dsps_hwacg_vclks, ARRAY_SIZE(exynos9810_dsps_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys0_hwacg_vclks, ARRAY_SIZE(exynos9810_fsys0_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys1_hwacg_vclks, ARRAY_SIZE(exynos9810_fsys1_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_g2d_hwacg_vclks, ARRAY_SIZE(exynos9810_g2d_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_g3d_hwacg_vclks, ARRAY_SIZE(exynos9810_g3d_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_isphq_hwacg_vclks, ARRAY_SIZE(exynos9810_isphq_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_isplp_hwacg_vclks, ARRAY_SIZE(exynos9810_isplp_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_isppre_hwacg_vclks, ARRAY_SIZE(exynos9810_isppre_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_iva_hwacg_vclks, ARRAY_SIZE(exynos9810_iva_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_mfc_hwacg_vclks, ARRAY_SIZE(exynos9810_mfc_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric0_hwacg_vclks, ARRAY_SIZE(exynos9810_peric0_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric1_hwacg_vclks, ARRAY_SIZE(exynos9810_peric1_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peris_hwacg_vclks, ARRAY_SIZE(exynos9810_peris_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_vts_hwacg_vclks, ARRAY_SIZE(exynos9810_vts_hwacg_vclks));
+
+ /* register special vclk */
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_apm_vclks, ARRAY_SIZE(exynos9810_apm_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_abox_vclks, ARRAY_SIZE(exynos9810_abox_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_chub_vclks, ARRAY_SIZE(exynos9810_chub_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmgp_vclks, ARRAY_SIZE(exynos9810_cmgp_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmu_vclks, ARRAY_SIZE(exynos9810_cmu_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys0_vclks, ARRAY_SIZE(exynos9810_fsys0_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys1_vclks, ARRAY_SIZE(exynos9810_fsys1_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric0_vclks, ARRAY_SIZE(exynos9810_peric0_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric1_vclks, ARRAY_SIZE(exynos9810_peric1_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_vts_vclks, ARRAY_SIZE(exynos9810_vts_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_clkout_vclks, ARRAY_SIZE(exynos9810_clkout_vclks));
+
+ clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
+
+ samsung_clk_of_add_provider(np, exynos9810_clk_provider);
+
+ late_time_init = exynos9810_vclk_init;
+
+ pr_info("EXYNOS9810: Clock setup completed\n");
+}
+
+CLK_OF_DECLARE(exynos9810_clk, "samsung,exynos9810-clock", exynos9810_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos9810 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <soc/samsung/cal-if.h>
+#include <dt-bindings/clock/exynos9810.h>
+
+#include "../../soc/samsung/cal-if/exynos9810_evt0/cmucal-vclk.h"
+#include "../../soc/samsung/cal-if/exynos9810_evt0/cmucal-node.h"
+#include "../../soc/samsung/cal-if/exynos9810_evt0/cmucal-qch.h"
+#include "../../soc/samsung/cal-if/exynos9810_evt0/clkout_exynos9810.h"
+#include "composite.h"
+
+static struct samsung_clk_provider *exynos9810_clk_provider;
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate exynos9810_fixed_rate_ext_clks[] __initdata = {
+ FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
+};
+
+/* HWACG VCLK */
+struct init_vclk exynos9810_apm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_DLL, MUX_DLL_USER, "UMUX_DLL", NULL, 0, VCLK_GATE, NULL),
+
+ HWACG_VCLK(GATE_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBE", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GREBE_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBE_DBG", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_INTMEM, INTMEM_QCH, "GATE_INTMEM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CHUB, MAILBOX_AP2CHUB_QCH, "GATE_MAILBOX_AP2CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP, MAILBOX_AP2CP_QCH, "GATE_MAILBOX_AP2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2CP_S, MAILBOX_AP2CP_S_QCH, "GATE_MAILBOX_AP2CP_S", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2GNSS, MAILBOX_AP2GNSS_QCH, "GATE_MAILBOX_AP2GNSS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_AP2VTS, MAILBOX_AP2VTS_QCH, "GATE_MAILBOX_AP2VTS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2AP, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CHUB, MAILBOX_APM2CHUB_QCH, "GATE_MAILBOX_APM2CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2CP, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_APM2GNSS, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_CHUB2CP, MAILBOX_CHUB2CP_QCH, "GATE_MAILBOX_CHUB2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_GNSS2CHUB, MAILBOX_GNSS2CHUB_QCH, "GATE_MAILBOX_GNSS2CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_GNSS2CP, MAILBOX_GNSS2CP_QCH, "GATE_MAILBOX_GNSS2CP", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PEM, PEM_QCH, "GATE_PEM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_APM, SPEEDY_APM_QCH, "GATE_SPEEDY_APM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPEEDY_SUB_APM, SPEEDY_SUB_APM_QCH, "GATE_SPEEDY_SUB_APM", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_APM, WDT_APM_QCH, "GATE_WDT_APM", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_abox_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_ABOX_ACLK, ABOX_QCH_ACLK, "GATE_ABOX_ACLK", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK_DSIF, ABOX_QCH_BCLK_DSIF, "GATE_ABOX_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK0, ABOX_QCH_BCLK0, "GATE_ABOX_BCLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK1, ABOX_QCH_BCLK1, "GATE_ABOX_BCLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK2, ABOX_QCH_BCLK2, "GATE_ABOX_BCLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_BCLK3, ABOX_QCH_BCLK3, "GATE_ABOX_BCLK3", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_DUMMY, ABOX_QCH_DUMMY, "GATE_ABOX_DUMMY", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ABOX_DMIC, DMIC_QCH, "GATE_ABOX_DMIC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_ABOX, SYSMMU_AUD_QCH, "GATE_SYSMMU_AUD", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_ABOXCPU, WDT_AUD_QCH, "GATE_WDT_AUD", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_bus1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_TREX_P_BUS1, TREX_P_BUS1_QCH, "GATE_TREX_P_BUS1", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_busc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_PDMA0, PDMA0_QCH, "GATE_PDMA0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PPFW, PPFW_QCH, "GATE_PPFW", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SBIC, SBIC_QCH, "GATE_SBIC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SIREX, SIREX_QCH, "GATE_SIREX", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPDMA, SPDMA_QCH, "GATE_SPDMA", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_D_BUSC, TREX_D_BUSC_QCH, "GATE_TREX_D_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P_BUSC, TREX_P_BUSC_QCH, "GATE_TREX_P_BUSC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_RB_BUSC, TREX_RB_BUSC_QCH, "GATE_TREX_RB_BUSC", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_chub_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_CM4_CHUB, CM4_CHUB_QCH, "GATE_CM4_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CHUB00, I2C_CHUB00_QCH, "GATE_I2C_CHUB00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CHUB01, I2C_CHUB01_QCH, "GATE_I2C_CHUB01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PDMA_CHUB, PDMA_CHUB_QCH, "GATE_PDMA_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PWM_CHUB, PWM_CHUB_QCH, "GATE_PWM_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TIMER_CHUB, TIMER_CHUB_QCH, "GATE_TIMER_CHUB", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CHUB00, USI_CHUB00_QCH, "GATE_USI_CHUB00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CHUB01, USI_CHUB01_QCH, "GATE_USI_CHUB01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CHUB, WDT_CHUB_QCH, "GATE_WDT_CHUB", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_cmgp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_ADC_CMGP_S0, ADC_CMGP_QCH_S0, "GATE_ADC_CMGP_S0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP_S1, ADC_CMGP_QCH_S1, "GATE_ADC_CMGP_S1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_ADC_CMGP, ADC_CMGP_QCH_ADC, "GATE_ADC_CMGP_ADC", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP00, I2C_CMGP00_QCH, "GATE_I2C_CMGP00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP01, I2C_CMGP01_QCH, "GATE_I2C_CMGP01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP02, I2C_CMGP02_QCH, "GATE_I2C_CMGP02", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CMGP03, I2C_CMGP03_QCH, "GATE_I2C_CMGP03", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP00, USI_CMGP00_QCH, "GATE_USI_CMGP00", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP01, USI_CMGP01_QCH, "GATE_USI_CMGP01", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP02, USI_CMGP02_QCH, "GATE_USI_CMGP02", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI_CMGP03, USI_CMGP03_QCH, "GATE_USI_CMGP03", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_cmu_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_CMU_CMUREF, CMU_CMU_CMUREF_QCH, "GATE_CMU_CMUREF", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK0, "GATE_CIS_CLK0", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK1, "GATE_CIS_CLK1", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK2, "GATE_CIS_CLK2", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK3, DFTMUX_TOP_QCH_CIS_CLK3, "GATE_CIS_CLK3", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP, OTP_QCH, "GATE_OTP", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_core_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_TREX_D_CORE, TREX_D_CORE_QCH, "GATE_TREX_D_CORE", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P0_CORE, TREX_P0_CORE_QCH, "GATE_TREX_P0_CORE", NULL, 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_P1_CORE, TREX_P1_CORE_QCH, "GATE_TREX_P1_CORE", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dcf_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCF_BUS, MUX_CLKCMU_DCF_BUS_USER, "UMUX_CLKCMU_DCF_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_DCF_CIP, IS_DCF_QCH_CIP, "GATE_IS_DCF_CIP", "UMUX_CLKCMU_DCF_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCF_C2SYNC_2SLV, IS_DCF_QCH_C2SYNC_2SLV, "GATE_IS_DCF_C2SYNC_2SLV", "UMUX_CLKCMU_DCF_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCF_SYSMMU, IS_DCF_QCH_SYSMMU, "GATE_IS_DCF_SYSMMU", "UMUX_CLKCMU_DCF_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dcpost_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCPOST_BUS, MUX_CLKCMU_DCPOST_BUS_USER, "UMUX_CLKCMU_DCPOST_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_DCPOST_CIP2, IS_DCPOST_QCH_CIP2, "GATE_IS_DCPOST_CIP2", "UMUX_CLKCMU_DCPOST_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCPOST_C2SYNC_1SLV_CLK, IS_DCPOST_QCH_C2SYNC_1SLV_CLK, "GATE_IS_DCPOST_C2SYNC_1SLV_CLK", "UMUX_CLKCMU_DCPOST_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dcrd_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DCRD_BUS, MUX_CLKCMU_DCRD_BUS_USER, "UMUX_CLKCMU_DCRD_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_DCRD_DCP, IS_DCRD_QCH_DCP, "GATE_IS_DCRD_DCP", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCRD_SYSMMU, IS_DCRD_QCH_SYSMMU, "GATE_IS_DCRD_SYSMMU", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCRD_DCP_C2C, IS_DCRD_QCH_DCP_C2C, "GATE_IS_DCRD_DCP_C2C", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_DCRD_DCP_DIV2, IS_DCRD_QCH_DCP_DIV2, "GATE_IS_DCRD_DCP_DIV2", "UMUX_CLKCMU_DCRD_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dpu_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS_USER, "UMUX_CLKCMU_DPU_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_DPU, DPU_QCH_DPU, "GATE_DPU_DPU", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_DMA, DPU_QCH_DPU_DMA, "GATE_DPU_DMA", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_DPP, DPU_QCH_DPU_DPP, "GATE_DPU_DPP", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DPU_WB_MUX, DPU_QCH_DPU_WB_MUX, "GATE_DPU_WB_MUX", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD0, SYSMMU_DPUD0_QCH, "GATE_SYSMMU_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD1, SYSMMU_DPUD1_QCH, "GATE_SYSMMU_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_DPUD2, SYSMMU_DPUD2_QCH, "GATE_SYSMMU_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dspm_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DSPM_BUS, MUX_CLKCMU_DSPM_BUS_USER, "UMUX_CLKCMU_DSPM_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_CNN, CNN_QCH, "GATE_CNN", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SCORE_MASTER, SCORE_MASTER_QCH, "GATE_SCORE_MASTER", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DSPM0, SYSMMU_DSPM0_QCH, "GATE_SMMU_DSPM0", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DSPM1, SYSMMU_DSPM1_QCH, "GATE_SMMU_DSPM1", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_DSPM2, SYSMMU_DSPM2_QCH, "GATE_SMMU_DSPM2", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_dsps_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_DSPS_BUS, MUX_CLKCMU_DSPS_BUS_USER, "UMUX_CLKCMU_DSPS_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_DSPS_AUD, MUX_CLKCMU_DSPS_AUD_USER, "UMUX_CLKCMU_DSPS_AUD", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_SCORE_KNIGHT, SCORE_KNIGHT_QCH, "GATE_SCORE_KNIGHT", "UMUX_CLKCMU_DSPS_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_fsys0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS_USER, "UMUX_CLKCMU_FSYS0_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_UFS_EMBD, MUX_CLKCMU_FSYS0_UFS_EMBD_USER, "UMUX_CLKCMU_FSYS0_UFS_EMBD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_USB30DRD, MUX_CLKCMU_FSYS0_USB30DRD_USER, "UMUX_CLKCMU_FSYS0_USB30DRD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC_USER, "UMUX_CLKCMU_FSYS0_DPGTC", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS0_USBDP_DEBUG, MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER, "UMUX_CLKCMU_FSYS0_USBDP_DEBUG", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_DP_LINK, DP_LINK_QCH, "GATE_DP_LINK", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_DP_LINK_GTC, DP_LINK_QCH_GTC, "GATE_DP_LINK_GTC", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD, UFS_EMBD_QCH, "GATE_UFS_EMBD", "UMUX_CLKCMU_FSYS0_UFS_EMBD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_EMBD_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_FMP", "UMUX_CLKCMU_FSYS0_UFS_EMBD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USB30DRD_LINK, USB30DRD_QCH_USB30DRD_LINK, "GATE_USB30DRD_USB30DRD_LINK", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USBPCS, USB30DRD_QCH_USBPCS, "GATE_USB30DRD_USBPCS", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USB30DRD_CTRL, USB30DRD_QCH_USB30DRD_CTRL, "GATE_USB30DRD_USB30DRD_CTRL", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_USBDPPHY, USB30DRD_QCH_USBDPPHY, "GATE_USB30DRD_USBDPPHY", "UMUX_CLKCMU_FSYS0_USB30DRD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USB30DRD_SOC_PLL, USB30DRD_QCH_SOC_PLL, "GATE_USB30DRD_SOC_PLL", "UMUX_CLKCMU_FSYS0_USBDP_DEBUG", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_fsys1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS_USER, "UMUX_CLKCMU_FSYS1_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE_USER, "UMUX_CLKCMU_FSYS1_PCIE", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD_USER, "UMUX_CLKCMU_FSYS1_MMC_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD_USER, "UMUX_CLKCMU_FSYS1_UFS_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_MMC_CARD, MMC_CARD_QCH, "GATE_MMC_CARD", "UMUX_CLKCMU_FSYS1_MMC_CARD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_MSTR, PCIE_GEN2_QCH_MSTR, "GATE_PCIE_GEN2_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_PCS, PCIE_GEN2_QCH_PCS, "GATE_PCIE_GEN2_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_PHY, PCIE_GEN2_QCH_PHY, "GATE_PCIE_GEN2_PHY", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_DBI, PCIE_GEN2_QCH_DBI, "GATE_PCIE_GEN2_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_APB, PCIE_GEN2_QCH_APB, "GATE_PCIE_GEN2_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN2_SOCPLL, PCIE_GEN2_QCH_SOCPLL, "GATE_PCIE_GEN2_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_MSTR, PCIE_GEN3_QCH_MSTR, "GATE_PCIE_GEN3_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_PCS, PCIE_GEN3_QCH_PCS, "GATE_PCIE_GEN3_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_DBI, PCIE_GEN3_QCH_DBI, "GATE_PCIE_GEN3_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_APB, PCIE_GEN3_QCH_APB, "GATE_PCIE_GEN3_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_SOCPLL, PCIE_GEN3_QCH_SOCPLL, "GATE_PCIE_GEN3_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_GEN3_PHY, PCIE_GEN3_QCH_PHY, "GATE_PCIE_GEN3", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_IA_GEN2, PCIE_IA_GEN2_QCH, "GATE_PCIE_IA_GEN2", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_PCIE_IA_GEN3, PCIE_IA_GEN3_QCH, "GATE_PCIE_IA_GEN3", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_RTIC, RTIC_QCH, "GATE_RTIC", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SSS, SSS_QCH, "GATE_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SYSMMU_FSYS1, SYSMMU_FSYS1_QCH, "GATE_SYSMMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_CARD, UFS_CARD_QCH, "GATE_UFS_CARD", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UFS_CARD_FMP, UFS_CARD_QCH_FMP, "GATE_UFS_CARD_FMP", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_g2d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, "UMUX_CLKCMU_G2D_MSCL", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "UMUX_CLKCMU_G2D_G2D", "UMUX_CLKCMU_G2D_MSCL", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_ASTC, ASTC_QCH, "GATE_ASTC", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_G2D, G2D_QCH, "GATE_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_JPEG, JPEG_QCH, "GATE_JPEG", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MSCL, MSCL_QCH, "GATE_MSCL", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD0, SYSMMU_G2DD0_QCH, "GATE_SMMU_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD1, SYSMMU_G2DD1_QCH, "GATE_SMMU_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_G2DD2, SYSMMU_G2DD2_QCH, "GATE_SMMU_G2DD2", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_g3d_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(GATE_GPU, GPU_QCH, "GATE_GPU", NULL, 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_isphq_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS_USER, "UMUX_CLKCMU_ISPHQ_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_ISPHQ, IS_ISPHQ_QCH_ISPHQ, "GATE_IS_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_C2COM, IS_ISPHQ_QCH_ISPHQ_C2COM, "GATE_IS_ISPHQ_C2COM", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPHQ_SYSMMU, IS_ISPHQ_QCH_SYSMMU_ISPHQ, "GATE_IS_ISPHQ_SYSMMU", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_isplp_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS_USER, "UMUX_CLKCMU_ISPLP_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_VRA, MUX_CLKCMU_ISPLP_VRA_USER, "UMUX_CLKCMU_ISPLP_VRA", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_ISPLP_GDC, MUX_CLKCMU_ISPLP_GDC_USER, "UMUX_CLKCMU_ISPLP_GDC", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_ISPLP_MC_SCALER, IS_ISPLP_QCH_MC_SCALER, "GATE_IS_ISPLP_MC_SCALER", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP, IS_ISPLP_QCH_ISPLP, "GATE_IS_ISPLP_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_VRA, IS_ISPLP_QCH_VRA, "GATE_IS_ISPLP_VRA", "UMUX_CLKCMU_ISPLP_VRA", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_GDC, IS_ISPLP_QCH_GDC, "GATE_IS_ISPLP_GDC", "UMUX_CLKCMU_ISPLP_GDC", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPLP_C2, IS_ISPLP_QCH_ISPLP_C2, "GATE_IS_ISPLP_ISPLP_C2", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_SYSMMU_ISPLP0, IS_ISPLP_QCH_SYSMMU_ISPLP0, "GATE_IS_ISPLP_SYSMMU_ISPLP0", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_SYSMMU_ISPLP1, IS_ISPLP_QCH_SYSMMU_ISPLP1, "GATE_IS_ISPLP_SYSMMU_ISPLP1", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_isppre_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_ISPPRE_BUS, MUX_CLKCMU_ISPPRE_BUS_USER, "UMUX_CLKCMU_ISPPRE_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS0, IS_ISPPRE_QCH_CSIS0, "GATE_IS_ISPPRE_CSIS0", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS1, IS_ISPPRE_QCH_CSIS1, "GATE_IS_ISPPRE_CSIS1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS2, IS_ISPPRE_QCH_CSIS2, "GATE_IS_ISPPRE_CSIS2", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_CSIS3, IS_ISPPRE_QCH_CSIS3, "GATE_IS_ISPPRE_CSIS3", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_PDP_DMA, IS_ISPPRE_QCH_PDP_DMA, "GATE_IS_ISPPRE_PDP_DMA", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_SYSMMU, IS_ISPPRE_QCH_SYSMMU_ISPPRE, "GATE_IS_ISPPRE_SYSMMU", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_3AA, IS_ISPPRE_QCH_3AA, "GATE_IS_ISPPRE_3AA", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_3AAM, IS_ISPPRE_QCH_3AAM, "GATE_IS_ISPPRE_3AAM", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_PDP_CORE0, IS_ISPPRE_QCH_PDP_CORE0, "GATE_IS_ISPPRE_PDP_CORE0", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IS_ISPPRE_PDP_CORE1, IS_ISPPRE_QCH_PDP_CORE1, "GATE_IS_ISPPRE_PDP_CORE1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_iva_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS_USER, "UMUX_CLKCMU_IVA_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_IVA, IVA_QCH_IVA, "GATE_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA_DEBUG, IVA_QCH_IVA_DEBUG, "GATE_IVA_DEBUG", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_IVA_INTMEM, IVA_INTMEM_QCH, "GATE_IVA_INTMEM", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_IVA, SYSMMU_IVA_QCH, "GATE_SMMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_TREX_RB_IVA, TREX_RB_IVA_QCH, "GATE_TREX_RB_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_mfc_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_MFC_BUS, MUX_CLKCMU_MFC_BUS_USER, "UMUX_CLKCMU_MFC_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, "UMUX_CLKCMU_MFC_WFD", "UMUX_CLKCMU_MFC_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_MFC, MFC_QCH, "GATE_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WFD, WFD_QCH, "GATE_WFD", "UMUX_CLKCMU_MFC_WFD", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_MFCD0, SYSMMU_MFCD0_QCH, "GATE_SMMU_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SMMU_MFCD1, SYSMMU_MFCD1_QCH, "GATE_SMMU_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_peric0_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS_USER, "UMUX_CLKCMU_PERIC0_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC0_IP, MUX_CLKCMU_PERIC0_IP_USER, "UMUX_CLKCMU_PERIC0_IP", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_PWM, PWM_QCH, "GATE_PWM", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_DBG, UART_DBG_QCH, "GATE_UART_DBG", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, "console-pclk0"),
+ HWACG_VCLK(GATE_USI00_I2C, USI00_I2C_QCH, "GATE_USI00_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI00, USI00_USI_QCH, "GATE_USI00_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI01_I2C, USI01_I2C_QCH, "GATE_USI01_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI01, USI01_USI_QCH, "GATE_USI01_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI02_I2C, USI02_I2C_QCH, "GATE_USI02_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI02, USI02_USI_QCH, "GATE_USI02_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI03_I2C, USI03_I2C_QCH, "GATE_USI03_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI03, USI03_USI_QCH, "GATE_USI03_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI04_I2C, USI04_I2C_QCH, "GATE_USI04_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI04, USI04_USI_QCH, "GATE_USI04_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI05_I2C, USI05_I2C_QCH, "GATE_USI05_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI05, USI05_USI_QCH, "GATE_USI05_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI12_I2C, USI12_I2C_QCH, "GATE_USI12_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI12, USI12_USI_QCH, "GATE_USI12_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI13_I2C, USI13_I2C_QCH, "GATE_USI13_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI13, USI13_USI_QCH, "GATE_USI13_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI14_I2C, USI14_I2C_QCH, "GATE_USI14_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI14, USI14_USI_QCH, "GATE_USI14_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_peric1_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS_USER, "UMUX_CLKCMU_PERIC1_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_PERIC1_IP, MUX_CLKCMU_PERIC1_IP_USER, "UMUX_CLKCMU_PERIC1_IP", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
+
+ HWACG_VCLK(GATE_I2C_CAM0, I2C_CAM0_QCH, "GATE_I2C_CAM0", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CAM1, I2C_CAM1_QCH, "GATE_I2C_CAM1", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CAM2, I2C_CAM2_QCH, "GATE_I2C_CAM2", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_I2C_CAM3, I2C_CAM3_QCH, "GATE_I2C_CAM3", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_SPI_CAM0, SPI_CAM0_QCH, "GATE_SPI_CAM0", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_UART_BT, UART_BT_QCH, "GATE_UART_BT", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI06_I2C, USI06_I2C_QCH, "GATE_USI06_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI06, USI06_USI_QCH, "GATE_USI06", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI07_I2C, USI07_I2C_QCH, "GATE_USI07_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI07, USI07_USI_QCH, "GATE_USI07", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI08_I2C, USI08_I2C_QCH, "GATE_USI08_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI08, USI08_USI_QCH, "GATE_USI08", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI09_I2C, USI09_I2C_QCH, "GATE_USI09_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI09, USI09_USI_QCH, "GATE_USI09", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI10_I2C, USI10_I2C_QCH, "GATE_USI10_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI10, USI10_USI_QCH, "GATE_USI10", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI11_I2C, USI11_I2C_QCH, "GATE_USI11_I2C", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_USI11, USI11_USI_QCH, "GATE_USI11", "UMUX_CLKCMU_PERIC1_IP", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_peris_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS_USER, "UMUX_CLKCMU_PERIS_BUS", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_BUSIF_TMU, BUSIF_TMU_QCH, "GATE_BUSIF_TMU", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_GIC, GIC_QCH, "GATE_GIC", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MCT, MCT_QCH, "GATE_MCT", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_BIRA, OTP_CON_BIRA_QCH, "GATE_OTP_CON_BIRA", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_OTP_CON_TOP, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER0, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_CLUSTER1, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
+};
+
+struct init_vclk exynos9810_vts_hwacg_vclks[] __initdata = {
+ HWACG_VCLK(UMUX_CLKCMU_VTS_BUS, MUX_CLKCMU_VTS_BUS_USER, "UMUX_CLKCMU_VTS_BUS", NULL, 0, 0, NULL),
+ HWACG_VCLK(UMUX_CLKCMU_VTS_DLL, MUX_CLKCMU_VTS_DLL_USER, "UMUX_CLKCMU_VTS_DLL", NULL, 0, 0, NULL),
+
+ HWACG_VCLK(GATE_VTS_CPU, CORTEXM4INTEGRATION_QCH_CPU, "GATE_CORTEXM4_CPU", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_VTS_DMIC_IF, DMIC_IF_QCH_DMIC_CLK, "GATE_DMIC_IF", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HWACG_SYS_DMIC0, HWACG_SYS_DMIC0_QCH, "GATE_HWACG_SYS_DMIC0", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_HWACG_SYS_DMIC1, HWACG_SYS_DMIC1_QCH, "GATE_HWACG_SYS_DMIC1", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_MAILBOX_VTS2CHUB, MAILBOX_VTS2CHUB_QCH, "GATE_MAILBOX_VTS2CHUB", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_WDT_VTS, WDT_VTS_QCH, "GATE_WDT_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+ HWACG_VCLK(GATE_U_DMIC_CLK_MUX, U_DMIC_CLK_MUX_QCH, "GATE_U_DMIC_CLK_MUX", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
+};
+
+/* Special VCLK */
+struct init_vclk exynos9810_apm_vclks[] __initdata = {
+ VCLK(APM_DLL_CMGP, CLKCMU_APM_DLL_CMGP, "APM_DLL_CMGP", 0, 0, NULL),
+ VCLK(APM_DLL_VTS, CLKCMU_APM_DLL_VTS, "APM_DLL_VTS", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_abox_vclks[] __initdata = {
+ VCLK(DOUT_CLK_ABOX_ACLK, DIV_CLK_AUD_BUS, "DOUT_CLK_ABOX_ACLK", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_CLK_ABOX_AUDIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_DSIF, DIV_CLK_AUD_DSIF, "DOUT_CLK_ABOX_DSIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_DMIC, DIV_CLK_AUD_DMIC, "DOUT_CLK_ABOX_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_CLK_ABOX_UAIF0", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_CLK_ABOX_UAIF1", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_ABOX_UAIF2", 0, 0, NULL),
+ VCLK(DOUT_CLK_ABOX_UAIF3, DIV_CLK_AUD_UAIF3, "DOUT_CLK_ABOX_UAIF3", 0, 0, NULL),
+ VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_chub_vclks[] __initdata = {
+ VCLK(CHUB_USI00, DIV_CLK_CHUB_USI00, "CHUB_USI00", 0, 0, NULL),
+ VCLK(CHUB_USI01, DIV_CLK_CHUB_USI01, "CHUB_USI01", 0, 0, NULL),
+ VCLK(CHUB_USI_I2C, DIV_CLK_CHUB_I2C, "CHUB_USI_I2C", 0, 0, NULL),
+ VCLK(CHUB_TIMER_FCLK, CLK_CHUB_TIMER_FCLK, "CHUB_TIMER_FCLK", 0, 0, NULL),
+ VCLK(CHUB_BUS, DIV_CLK_CHUB_BUS, "CHUB_BUS", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_cmgp_vclks[] __initdata = {
+ VCLK(USI_CMGP00, DIV_CLK_USI_CMGP00, "USI_CMGP00", 0, 0, NULL),
+ VCLK(USI_CMGP01, DIV_CLK_USI_CMGP01, "USI_CMGP01", 0, 0, NULL),
+ VCLK(USI_CMGP02, DIV_CLK_USI_CMGP02, "USI_CMGP02", 0, 0, NULL),
+ VCLK(USI_CMGP03, DIV_CLK_USI_CMGP03, "USI_CMGP03", 0, 0, NULL),
+ VCLK(CMGP_USI_I2C, DIV_CLK_I2C_CMGP, "CMGP_USI_I2C", 0, 0, NULL),
+ VCLK(CMGP_ADC, DIV_CLK_CMGP_ADC, "CMGP_ADC", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_fsys0_vclks[] __initdata = {
+ VCLK(UFS_EMBD, VCLK_CLK_FSYS0_UFS_EMBD_BLK_CMU, "UFS_EMBD", 0, 0, NULL),
+ VCLK(DPGTC, VCLK_CLK_FSYS0_DPGTC_BLK_CMU, "DPGTC", 0, 0, NULL),
+ VCLK(USB30DRD, VCLK_CLK_FSYS0_USB30DRD_BLK_CMU, "USB30DRD", 0, 0, NULL),
+ VCLK(USBDP_DEBUG_USER, VCLK_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_BLK_CMU, "USBDP_DEBUG_USER", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_fsys1_vclks[] __initdata = {
+ VCLK(MMC_CARD, CLKCMU_FSYS1_MMC_CARD, "MMC_CARD", 0, 0, NULL),
+ VCLK(UFS_CARD, VCLK_CLK_FSYS1_UFS_CARD_BLK_CMU, "UFS_CARD", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_peric0_vclks[] __initdata = {
+ VCLK(UART_DBG, DIV_CLK_PERIC0_UART_DBG, "UART_DBG", 0, 0, "console-sclk0"),
+ VCLK(USI00, DIV_CLK_PERIC0_USI00_USI, "USI00_USI", 0, 0, NULL),
+ VCLK(USI01, DIV_CLK_PERIC0_USI01_USI, "USI01_USI", 0, 0, NULL),
+ VCLK(USI02, DIV_CLK_PERIC0_USI02_USI, "USI02_USI", 0, 0, NULL),
+ VCLK(USI03, DIV_CLK_PERIC0_USI03_USI, "USI03_USI", 0, 0, NULL),
+ VCLK(USI04, DIV_CLK_PERIC0_USI04_USI, "USI04_USI", 0, 0, NULL),
+ VCLK(USI05, DIV_CLK_PERIC0_USI05_USI, "USI05_USI", 0, 0, NULL),
+ VCLK(USI12, DIV_CLK_PERIC0_USI12_USI, "USI12_USI", 0, 0, NULL),
+ VCLK(USI13, DIV_CLK_PERIC0_USI13_USI, "USI13_USI", 0, 0, NULL),
+ VCLK(USI14, DIV_CLK_PERIC0_USI14_USI, "USI14_USI", 0, 0, NULL),
+ VCLK(PERIC0_USI_I2C, DIV_CLK_PERIC0_USI_I2C, "PERIC0_USI_I2C", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_peric1_vclks[] __initdata = {
+ VCLK(UART_BT, DIV_CLK_PERIC1_UART_BT, "UART_BT", 0, 0, NULL),
+ VCLK(I2C_CAM0, DIV_CLK_PERIC1_I2C_CAM0, "I2C_CAM0", 0, 0, NULL),
+ VCLK(I2C_CAM1, DIV_CLK_PERIC1_I2C_CAM1, "I2C_CAM1", 0, 0, NULL),
+ VCLK(I2C_CAM2, DIV_CLK_PERIC1_I2C_CAM2, "I2C_CAM2", 0, 0, NULL),
+ VCLK(I2C_CAM3, DIV_CLK_PERIC1_I2C_CAM3, "I2C_CAM3", 0, 0, NULL),
+ VCLK(SPI_CAM0, DIV_CLK_PERIC1_SPI_CAM0, "SPI_CAM0", 0, 0, NULL),
+ VCLK(USI06, DIV_CLK_PERIC1_USI06_USI, "USI06", 0, 0, NULL),
+ VCLK(USI07, DIV_CLK_PERIC1_USI07_USI, "USI07", 0, 0, NULL),
+ VCLK(USI08, DIV_CLK_PERIC1_USI08_USI, "USI08", 0, 0, NULL),
+ VCLK(USI09, DIV_CLK_PERIC1_USI09_USI, "USI09", 0, 0, NULL),
+ VCLK(USI10, DIV_CLK_PERIC1_USI10_USI, "USI10", 0, 0, NULL),
+ VCLK(USI11, DIV_CLK_PERIC1_USI11_USI, "USI11", 0, 0, NULL),
+ VCLK(PERIC1_USI_I2C, DIV_CLK_PERIC1_USI_I2C, "PERIC1_USI_I2C", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_cmu_vclks[] __initdata = {
+ VCLK(CIS_CLK0, CLKCMU_CIS_CLK0, "CIS_CLK0", 0, 0, NULL),
+ VCLK(CIS_CLK1, CLKCMU_CIS_CLK1, "CIS_CLK1", 0, 0, NULL),
+ VCLK(CIS_CLK2, CLKCMU_CIS_CLK2, "CIS_CLK2", 0, 0, NULL),
+ VCLK(CIS_CLK3, CLKCMU_CIS_CLK3, "CIS_CLK3", 0, 0, NULL),
+ VCLK(HPM, VCLK_CLKCMU_HPM_BLK_CMU, "HPM", 0, 0, NULL),
+};
+
+struct init_vclk exynos9810_vts_vclks[] __initdata = {
+ VCLK(DOUT_CLK_VTS_DMICIF, DIV_CLK_VTS_DMIC_IF, "DOUT_CLK_VTS_DMICIF", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC, "DOUT_CLK_VTS_DMIC", 0, 0, NULL),
+ VCLK(DOUT_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMIC_DIV2, "DOUT_CLK_VTS_DMIC_DIV2", 0, 0, NULL),
+};
+
+static struct init_vclk exynos9810_clkout_vclks[] __initdata = {
+ VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
+ VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ {.compatible = "samsung,exynos9810-oscclk", .data = (void *)0},
+ {},
+};
+
+void exynos9810_vclk_init(void)
+{
+ /* Common clock init */
+}
+
+/* register exynos9810 clocks */
+void __init exynos9810_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ int ret;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ ret = cal_if_init(np);
+ if (ret)
+ panic("%s: unable to initialize cal-if\n", __func__);
+
+ exynos9810_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (!exynos9810_clk_provider)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_register_of_fixed_ext(exynos9810_clk_provider, exynos9810_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos9810_fixed_rate_ext_clks),
+ ext_clk_match);
+ /* register HWACG vclk */
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_apm_hwacg_vclks, ARRAY_SIZE(exynos9810_apm_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_abox_hwacg_vclks, ARRAY_SIZE(exynos9810_abox_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_bus1_hwacg_vclks, ARRAY_SIZE(exynos9810_bus1_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_busc_hwacg_vclks, ARRAY_SIZE(exynos9810_busc_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_chub_hwacg_vclks, ARRAY_SIZE(exynos9810_chub_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmgp_hwacg_vclks, ARRAY_SIZE(exynos9810_cmgp_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmu_hwacg_vclks, ARRAY_SIZE(exynos9810_cmu_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_core_hwacg_vclks, ARRAY_SIZE(exynos9810_core_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dcf_hwacg_vclks, ARRAY_SIZE(exynos9810_dcf_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dcpost_hwacg_vclks, ARRAY_SIZE(exynos9810_dcpost_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dcrd_hwacg_vclks, ARRAY_SIZE(exynos9810_dcrd_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dpu_hwacg_vclks, ARRAY_SIZE(exynos9810_dpu_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dspm_hwacg_vclks, ARRAY_SIZE(exynos9810_dspm_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_dsps_hwacg_vclks, ARRAY_SIZE(exynos9810_dsps_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys0_hwacg_vclks, ARRAY_SIZE(exynos9810_fsys0_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys1_hwacg_vclks, ARRAY_SIZE(exynos9810_fsys1_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_g2d_hwacg_vclks, ARRAY_SIZE(exynos9810_g2d_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_g3d_hwacg_vclks, ARRAY_SIZE(exynos9810_g3d_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_isphq_hwacg_vclks, ARRAY_SIZE(exynos9810_isphq_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_isplp_hwacg_vclks, ARRAY_SIZE(exynos9810_isplp_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_isppre_hwacg_vclks, ARRAY_SIZE(exynos9810_isppre_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_iva_hwacg_vclks, ARRAY_SIZE(exynos9810_iva_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_mfc_hwacg_vclks, ARRAY_SIZE(exynos9810_mfc_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric0_hwacg_vclks, ARRAY_SIZE(exynos9810_peric0_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric1_hwacg_vclks, ARRAY_SIZE(exynos9810_peric1_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peris_hwacg_vclks, ARRAY_SIZE(exynos9810_peris_hwacg_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_vts_hwacg_vclks, ARRAY_SIZE(exynos9810_vts_hwacg_vclks));
+
+ /* register special vclk */
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_apm_vclks, ARRAY_SIZE(exynos9810_apm_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_abox_vclks, ARRAY_SIZE(exynos9810_abox_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_chub_vclks, ARRAY_SIZE(exynos9810_chub_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmgp_vclks, ARRAY_SIZE(exynos9810_cmgp_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_cmu_vclks, ARRAY_SIZE(exynos9810_cmu_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys0_vclks, ARRAY_SIZE(exynos9810_fsys0_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_fsys1_vclks, ARRAY_SIZE(exynos9810_fsys1_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric0_vclks, ARRAY_SIZE(exynos9810_peric0_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_peric1_vclks, ARRAY_SIZE(exynos9810_peric1_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_vts_vclks, ARRAY_SIZE(exynos9810_vts_vclks));
+ samsung_register_vclk(exynos9810_clk_provider, exynos9810_clkout_vclks, ARRAY_SIZE(exynos9810_clkout_vclks));
+
+ clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
+
+ samsung_clk_of_add_provider(np, exynos9810_clk_provider);
+
+ late_time_init = exynos9810_vclk_init;
+
+ pr_info("EXYNOS9810: Clock setup completed\n");
+}
+
+CLK_OF_DECLARE(exynos9810_clk, "samsung,exynos9810-clock", exynos9810_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the pll clocks.
+*/
+
+#include <linux/errno.h>
+#include <linux/hrtimer.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/clkdev.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define PLL_TIMEOUT_MS 10
+
+struct samsung_clk_pll {
+ struct clk_hw hw;
+ void __iomem *lock_reg;
+ void __iomem *con_reg;
+ enum samsung_pll_type type;
+ unsigned int rate_count;
+ const struct samsung_pll_rate_table *rate_table;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_clk_pll *pll, unsigned long rate)
+{
+ const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ for (i = 0; i < pll->rate_count; i++) {
+ if (rate == rate_table[i].rate)
+ return &rate_table[i];
+ }
+
+ return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ /* Assumming rate_table is in descending order */
+ for (i = 0; i < pll->rate_count; i++) {
+ if (drate >= rate_table[i].rate)
+ return rate_table[i].rate;
+ }
+
+ /* return minimum supported value */
+ return rate_table[i - 1].rate;
+}
+
+/*
+ * PLL2126 Clock Type
+ */
+
+#define PLL2126_MDIV_MASK (0xff)
+#define PLL2126_PDIV_MASK (0x3f)
+#define PLL2126_SDIV_MASK (0x3)
+#define PLL2126_MDIV_SHIFT (16)
+#define PLL2126_PDIV_SHIFT (8)
+#define PLL2126_SDIV_SHIFT (0)
+
+static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
+ pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
+ sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
+
+ fvco *= (mdiv + 8);
+ do_div(fvco, (pdiv + 2) << sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126_clk_ops = {
+ .recalc_rate = samsung_pll2126_recalc_rate,
+};
+
+/*
+ * PLL3000 Clock Type
+ */
+
+#define PLL3000_MDIV_MASK (0xff)
+#define PLL3000_PDIV_MASK (0x3)
+#define PLL3000_SDIV_MASK (0x3)
+#define PLL3000_MDIV_SHIFT (16)
+#define PLL3000_PDIV_SHIFT (8)
+#define PLL3000_SDIV_SHIFT (0)
+
+static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
+ pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
+ sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
+
+ fvco *= (2 * (mdiv + 8));
+ do_div(fvco, pdiv << sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000_clk_ops = {
+ .recalc_rate = samsung_pll3000_recalc_rate,
+};
+
+/*
+ * PLL35xx Clock Type
+ */
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR (270)
+
+#define PLL35XX_MDIV_MASK (0x3FF)
+#define PLL35XX_PDIV_MASK (0x3F)
+#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_LOCK_STAT_MASK (0x1)
+#define PLL35XX_MDIV_SHIFT (16)
+#define PLL35XX_PDIV_SHIFT (8)
+#define PLL35XX_SDIV_SHIFT (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
+
+static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll35xx_mp_change(
+ const struct samsung_pll_rate_table *rate, u32 pll_con)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+
+ return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ tmp = readl_relaxed(pll->con_reg);
+
+ if (!(samsung_pll35xx_mp_change(rate, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
+ tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
+ writel_relaxed(tmp, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+ pll->lock_reg);
+
+ /* Change PLL PMS values */
+ tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
+ (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
+ (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
+ tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL35XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL35XX_SDIV_SHIFT);
+ writel_relaxed(tmp, pll->con_reg);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = readl_relaxed(pll->con_reg);
+ } while (!(tmp & (PLL35XX_LOCK_STAT_MASK
+ << PLL35XX_LOCK_STAT_SHIFT)));
+ return 0;
+}
+
+static const struct clk_ops samsung_pll35xx_clk_ops = {
+ .recalc_rate = samsung_pll35xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll35xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll35xx_clk_min_ops = {
+ .recalc_rate = samsung_pll35xx_recalc_rate,
+};
+
+/*
+ * PLL36xx Clock Type
+ */
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR (3000)
+
+#define PLL36XX_KDIV_MASK (0xFFFF)
+#define PLL36XX_MDIV_MASK (0x1FF)
+#define PLL36XX_PDIV_MASK (0x3F)
+#define PLL36XX_SDIV_MASK (0x7)
+#define PLL36XX_MDIV_SHIFT (16)
+#define PLL36XX_PDIV_SHIFT (8)
+#define PLL36XX_SDIV_SHIFT (0)
+#define PLL36XX_KDIV_SHIFT (0)
+#define PLL36XX_LOCK_STAT_SHIFT (29)
+
+static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+ kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll36xx_mpk_change(
+ const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+ old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+ old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
+
+ return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+ rate->kdiv != old_kdiv);
+}
+
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
+
+ if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
+ /* If only s change, change just s value only*/
+ pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
+ pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
+ writel_relaxed(pll_con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
+
+ /* Change PLL PMS values */
+ pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
+ (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
+ (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
+ pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL36XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL36XX_SDIV_SHIFT);
+ writel_relaxed(pll_con0, pll->con_reg);
+
+ pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
+ pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
+ writel_relaxed(pll_con1, pll->con_reg + 4);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = readl_relaxed(pll->con_reg);
+ } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll36xx_clk_ops = {
+ .recalc_rate = samsung_pll36xx_recalc_rate,
+ .set_rate = samsung_pll36xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+ .recalc_rate = samsung_pll36xx_recalc_rate,
+};
+
+/*
+ * PLL45xx Clock Type
+ */
+#define PLL4502_LOCK_FACTOR 400
+#define PLL4508_LOCK_FACTOR 240
+
+#define PLL45XX_MDIV_MASK (0x3FF)
+#define PLL45XX_PDIV_MASK (0x3F)
+#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_AFC_MASK (0x1F)
+#define PLL45XX_MDIV_SHIFT (16)
+#define PLL45XX_PDIV_SHIFT (8)
+#define PLL45XX_SDIV_SHIFT (0)
+#define PLL45XX_AFC_SHIFT (0)
+
+#define PLL45XX_ENABLE BIT(31)
+#define PLL45XX_LOCKED BIT(29)
+
+static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+ if (pll->type == pll_4508)
+ sdiv = sdiv - 1;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_afc;
+
+ old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+ old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+ old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
+
+ return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
+ || old_afc != rate->afc);
+}
+
+static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
+
+ if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
+ con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
+ writel_relaxed(con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL PMS values. */
+ con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
+ (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
+ (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
+ con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL45XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL45XX_SDIV_SHIFT);
+
+ /* Set PLL AFC value. */
+ con1 = readl_relaxed(pll->con_reg + 0x4);
+ con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
+ con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
+
+ /* Set PLL lock time. */
+ switch (pll->type) {
+ case pll_4502:
+ writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
+ break;
+ case pll_4508:
+ writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
+ break;
+ default:
+ break;
+ }
+
+ /* Set new configuration. */
+ writel_relaxed(con1, pll->con_reg + 0x4);
+ writel_relaxed(con0, pll->con_reg);
+
+ /* Wait for locking. */
+ start = ktime_get();
+ while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) {
+ ktime_t delta = ktime_sub(ktime_get(), start);
+
+ if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
+ pr_err("%s: could not lock PLL %s\n",
+ __func__, clk_hw_get_name(hw));
+ return -EFAULT;
+ }
+
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll45xx_clk_ops = {
+ .recalc_rate = samsung_pll45xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll45xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll45xx_clk_min_ops = {
+ .recalc_rate = samsung_pll45xx_recalc_rate,
+};
+
+/*
+ * PLL46xx Clock Type
+ */
+#define PLL46XX_LOCK_FACTOR 3000
+
+#define PLL46XX_VSEL_MASK (1)
+#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL1460X_MDIV_MASK (0x3FF)
+
+#define PLL46XX_PDIV_MASK (0x3F)
+#define PLL46XX_SDIV_MASK (0x7)
+#define PLL46XX_VSEL_SHIFT (27)
+#define PLL46XX_MDIV_SHIFT (16)
+#define PLL46XX_PDIV_SHIFT (8)
+#define PLL46XX_SDIV_SHIFT (0)
+
+#define PLL46XX_KDIV_MASK (0xFFFF)
+#define PLL4650C_KDIV_MASK (0xFFF)
+#define PLL46XX_KDIV_SHIFT (0)
+#define PLL46XX_MFR_MASK (0x3F)
+#define PLL46XX_MRR_MASK (0x1F)
+#define PLL46XX_KDIV_SHIFT (0)
+#define PLL46XX_MFR_SHIFT (16)
+#define PLL46XX_MRR_SHIFT (24)
+
+#define PLL46XX_ENABLE BIT(31)
+#define PLL46XX_LOCKED BIT(29)
+#define PLL46XX_VSEL BIT(27)
+
+static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
+ pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+ kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
+ pll_con1 & PLL46XX_KDIV_MASK;
+
+ shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+
+ fvco *= (mdiv << shift) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= shift;
+
+ return (unsigned long)fvco;
+}
+
+static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+ old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+ old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
+
+ return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
+ || old_kdiv != rate->kdiv);
+}
+
+static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1, lock;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
+
+ if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+ con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
+ writel_relaxed(con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
+ if (lock > 0xffff)
+ /* Maximum lock time bitfield is 16-bit. */
+ lock = 0xffff;
+
+ /* Set PLL PMS and VSEL values. */
+ if (pll->type == pll_1460x) {
+ con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
+ } else {
+ con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
+ (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+ con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
+ }
+
+ con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL46XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL46XX_SDIV_SHIFT);
+
+ /* Set PLL K, MFR and MRR values. */
+ con1 = readl_relaxed(pll->con_reg + 0x4);
+ con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
+ (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
+ (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
+ con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
+ (rate->mfr << PLL46XX_MFR_SHIFT) |
+ (rate->mrr << PLL46XX_MRR_SHIFT);
+
+ /* Write configuration to PLL */
+ writel_relaxed(lock, pll->lock_reg);
+ writel_relaxed(con0, pll->con_reg);
+ writel_relaxed(con1, pll->con_reg + 0x4);
+
+ /* Wait for locking. */
+ start = ktime_get();
+ while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) {
+ ktime_t delta = ktime_sub(ktime_get(), start);
+
+ if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
+ pr_err("%s: could not lock PLL %s\n",
+ __func__, clk_hw_get_name(hw));
+ return -EFAULT;
+ }
+
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll46xx_clk_ops = {
+ .recalc_rate = samsung_pll46xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll46xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll46xx_clk_min_ops = {
+ .recalc_rate = samsung_pll46xx_recalc_rate,
+};
+
+/*
+ * PLL6552 Clock Type
+ */
+
+#define PLL6552_MDIV_MASK 0x3ff
+#define PLL6552_PDIV_MASK 0x3f
+#define PLL6552_SDIV_MASK 0x7
+#define PLL6552_MDIV_SHIFT 16
+#define PLL6552_MDIV_SHIFT_2416 14
+#define PLL6552_PDIV_SHIFT 8
+#define PLL6552_PDIV_SHIFT_2416 5
+#define PLL6552_SDIV_SHIFT 0
+
+static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ if (pll->type == pll_6552_s3c2416) {
+ mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
+ pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
+ } else {
+ mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
+ pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
+ }
+ sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll6552_clk_ops = {
+ .recalc_rate = samsung_pll6552_recalc_rate,
+};
+
+/*
+ * PLL6553 Clock Type
+ */
+
+#define PLL6553_MDIV_MASK 0xff
+#define PLL6553_PDIV_MASK 0x3f
+#define PLL6553_SDIV_MASK 0x7
+#define PLL6553_KDIV_MASK 0xffff
+#define PLL6553_MDIV_SHIFT 16
+#define PLL6553_PDIV_SHIFT 8
+#define PLL6553_SDIV_SHIFT 0
+#define PLL6553_KDIV_SHIFT 0
+
+static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 0x4);
+ mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
+ kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll6553_clk_ops = {
+ .recalc_rate = samsung_pll6553_recalc_rate,
+};
+
+/*
+ * PLL Clock Type of S3C24XX before S3C2443
+ */
+
+#define PLLS3C2410_MDIV_MASK (0xff)
+#define PLLS3C2410_PDIV_MASK (0x1f)
+#define PLLS3C2410_SDIV_MASK (0x3)
+#define PLLS3C2410_MDIV_SHIFT (12)
+#define PLLS3C2410_PDIV_SHIFT (4)
+#define PLLS3C2410_SDIV_SHIFT (0)
+
+#define PLLS3C2410_ENABLE_REG_OFFSET 0x10
+
+static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
+ pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
+ sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
+
+ fvco *= (mdiv + 8);
+ do_div(fvco, (pdiv + 2) << sdiv);
+
+ return (unsigned int)fvco;
+}
+
+static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
+ pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
+ sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
+
+ fvco *= (2 * (mdiv + 8));
+ do_div(fvco, (pdiv + 2) << sdiv);
+
+ return (unsigned int)fvco;
+}
+
+static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ tmp = readl_relaxed(pll->con_reg);
+
+ /* Change PLL PMS values */
+ tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
+ (PLLS3C2410_PDIV_MASK << PLLS3C2410_PDIV_SHIFT) |
+ (PLLS3C2410_SDIV_MASK << PLLS3C2410_SDIV_SHIFT));
+ tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
+ (rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
+ (rate->sdiv << PLLS3C2410_SDIV_SHIFT);
+ writel_relaxed(tmp, pll->con_reg);
+
+ /* Time to settle according to the manual */
+ udelay(300);
+
+ return 0;
+}
+
+static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
+ u32 pll_en_orig = pll_en;
+
+ if (enable)
+ pll_en &= ~BIT(bit);
+ else
+ pll_en |= BIT(bit);
+
+ writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
+
+ /* if we started the UPLL, then allow to settle */
+ if (enable && (pll_en_orig & BIT(bit)))
+ udelay(300);
+
+ return 0;
+}
+
+static int samsung_s3c2410_mpll_enable(struct clk_hw *hw)
+{
+ return samsung_s3c2410_pll_enable(hw, 5, true);
+}
+
+static void samsung_s3c2410_mpll_disable(struct clk_hw *hw)
+{
+ samsung_s3c2410_pll_enable(hw, 5, false);
+}
+
+static int samsung_s3c2410_upll_enable(struct clk_hw *hw)
+{
+ return samsung_s3c2410_pll_enable(hw, 7, true);
+}
+
+static void samsung_s3c2410_upll_disable(struct clk_hw *hw)
+{
+ samsung_s3c2410_pll_enable(hw, 7, false);
+}
+
+static const struct clk_ops samsung_s3c2410_mpll_clk_min_ops = {
+ .recalc_rate = samsung_s3c2410_pll_recalc_rate,
+ .enable = samsung_s3c2410_mpll_enable,
+ .disable = samsung_s3c2410_mpll_disable,
+};
+
+static const struct clk_ops samsung_s3c2410_upll_clk_min_ops = {
+ .recalc_rate = samsung_s3c2410_pll_recalc_rate,
+ .enable = samsung_s3c2410_upll_enable,
+ .disable = samsung_s3c2410_upll_disable,
+};
+
+static const struct clk_ops samsung_s3c2440_mpll_clk_min_ops = {
+ .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
+ .enable = samsung_s3c2410_mpll_enable,
+ .disable = samsung_s3c2410_mpll_disable,
+};
+
+static const struct clk_ops samsung_s3c2410_mpll_clk_ops = {
+ .recalc_rate = samsung_s3c2410_pll_recalc_rate,
+ .enable = samsung_s3c2410_mpll_enable,
+ .disable = samsung_s3c2410_mpll_disable,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_s3c2410_pll_set_rate,
+};
+
+static const struct clk_ops samsung_s3c2410_upll_clk_ops = {
+ .recalc_rate = samsung_s3c2410_pll_recalc_rate,
+ .enable = samsung_s3c2410_upll_enable,
+ .disable = samsung_s3c2410_upll_disable,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_s3c2410_pll_set_rate,
+};
+
+static const struct clk_ops samsung_s3c2440_mpll_clk_ops = {
+ .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
+ .enable = samsung_s3c2410_mpll_enable,
+ .disable = samsung_s3c2410_mpll_disable,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_s3c2410_pll_set_rate,
+};
+
+/*
+ * PLL2550x Clock Type
+ */
+
+#define PLL2550X_R_MASK (0x1)
+#define PLL2550X_P_MASK (0x3F)
+#define PLL2550X_M_MASK (0x3FF)
+#define PLL2550X_S_MASK (0x7)
+#define PLL2550X_R_SHIFT (20)
+#define PLL2550X_P_SHIFT (14)
+#define PLL2550X_M_SHIFT (4)
+#define PLL2550X_S_SHIFT (0)
+
+static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 r, p, m, s, pll_stat;
+ u64 fvco = parent_rate;
+
+ pll_stat = readl_relaxed(pll->con_reg);
+ r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
+ if (!r)
+ return 0;
+ p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
+ m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
+ s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
+
+ fvco *= m;
+ do_div(fvco, (p << s));
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2550x_clk_ops = {
+ .recalc_rate = samsung_pll2550x_recalc_rate,
+};
+
+/*
+ * PLL2550xx Clock Type
+ */
+
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL2550XX_LOCK_FACTOR 270
+
+#define PLL2550XX_M_MASK 0x3FF
+#define PLL2550XX_P_MASK 0x3F
+#define PLL2550XX_S_MASK 0x7
+#define PLL2550XX_LOCK_STAT_MASK 0x1
+#define PLL2550XX_M_SHIFT 9
+#define PLL2550XX_P_SHIFT 3
+#define PLL2550XX_S_SHIFT 0
+#define PLL2550XX_LOCK_STAT_SHIFT 21
+
+static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+ pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+ sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+ old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+
+ return mdiv != old_mdiv || pdiv != old_pdiv;
+}
+
+static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ tmp = readl_relaxed(pll->con_reg);
+
+ if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
+ tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
+ writel_relaxed(tmp, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+
+ /* Change PLL PMS values */
+ tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
+ (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
+ (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
+ tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
+ (rate->pdiv << PLL2550XX_P_SHIFT) |
+ (rate->sdiv << PLL2550XX_S_SHIFT);
+ writel_relaxed(tmp, pll->con_reg);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = readl_relaxed(pll->con_reg);
+ } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
+ << PLL2550XX_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2550xx_clk_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll2550xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+};
+
+/*
+ * PLL2650x Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650X_LOCK_FACTOR 3000
+
+#define PLL2650X_M_MASK 0x1ff
+#define PLL2650X_P_MASK 0x3f
+#define PLL2650X_S_MASK 0x7
+#define PLL2650X_K_MASK 0xffff
+#define PLL2650X_LOCK_STAT_MASK 0x1
+#define PLL2650X_M_SHIFT 16
+#define PLL2650X_P_SHIFT 8
+#define PLL2650X_S_SHIFT 0
+#define PLL2650X_K_SHIFT 0
+#define PLL2650X_LOCK_STAT_SHIFT 29
+#define PLL2650X_PLL_ENABLE_SHIFT 31
+
+static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u64 fout = parent_rate;
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+ s16 kdiv;
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
+ pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
+ sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
+
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
+ kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK);
+
+ fout *= (mdiv << 16) + kdiv;
+ do_div(fout, (pdiv << sdiv));
+ fout >>= 16;
+
+ return (unsigned long)fout;
+}
+
+static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 4);
+
+ /* Set PLL lock time. */
+ writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
+
+ /* Change PLL PMS values */
+ con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
+ (PLL2650X_P_MASK << PLL2650X_P_SHIFT) |
+ (PLL2650X_S_MASK << PLL2650X_S_SHIFT));
+ con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
+ (rate->pdiv << PLL2650X_P_SHIFT) |
+ (rate->sdiv << PLL2650X_S_SHIFT);
+ con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
+ writel_relaxed(con0, pll->con_reg);
+
+ con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT);
+ con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT);
+ writel_relaxed(con1, pll->con_reg + 4);
+
+ do {
+ cpu_relax();
+ con0 = readl_relaxed(pll->con_reg);
+ } while (!(con0 & (PLL2650X_LOCK_STAT_MASK
+ << PLL2650X_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650x_clk_ops = {
+ .recalc_rate = samsung_pll2650x_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll2650x_set_rate,
+};
+
+static const struct clk_ops samsung_pll2650x_clk_min_ops = {
+ .recalc_rate = samsung_pll2650x_recalc_rate,
+};
+
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR 3000
+
+#define PLL2650XX_MDIV_SHIFT 9
+#define PLL2650XX_PDIV_SHIFT 3
+#define PLL2650XX_SDIV_SHIFT 0
+#define PLL2650XX_KDIV_SHIFT 0
+#define PLL2650XX_MDIV_MASK 0x1ff
+#define PLL2650XX_PDIV_MASK 0x3f
+#define PLL2650XX_SDIV_MASK 0x7
+#define PLL2650XX_KDIV_MASK 0xffff
+#define PLL2650XX_PLL_ENABLE_SHIFT 23
+#define PLL2650XX_PLL_LOCKTIME_SHIFT 21
+#define PLL2650XX_PLL_FOUTMASK_SHIFT 31
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con2 = readl_relaxed(pll->con_reg + 8);
+ mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+ kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con2;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con2 = readl_relaxed(pll->con_reg + 8);
+
+ /* Change PLL PMS values */
+ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+ PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+ PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+ pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+ pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+ pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+ pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+ pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+ << PLL2650XX_KDIV_SHIFT;
+
+ /* Set PLL lock time. */
+ writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+ writel_relaxed(pll_con0, pll->con_reg);
+ writel_relaxed(pll_con2, pll->con_reg + 8);
+
+ do {
+ tmp = readl_relaxed(pll->con_reg);
+ } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+ .set_rate = samsung_pll2650xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
+static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+ const struct samsung_pll_clock *pll_clk,
+ void __iomem *base)
+{
+ struct samsung_clk_pll *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+ int ret, len;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n",
+ __func__, pll_clk->name);
+ return;
+ }
+
+ init.name = pll_clk->name;
+ init.flags = pll_clk->flags;
+ init.parent_names = &pll_clk->parent_name;
+ init.num_parents = 1;
+
+ if (pll_clk->rate_table) {
+ /* find count of rates in rate_table */
+ for (len = 0; pll_clk->rate_table[len].rate != 0; )
+ len++;
+
+ pll->rate_count = len;
+ pll->rate_table = kmemdup(pll_clk->rate_table,
+ pll->rate_count *
+ sizeof(struct samsung_pll_rate_table),
+ GFP_KERNEL);
+ WARN(!pll->rate_table,
+ "%s: could not allocate rate table for %s\n",
+ __func__, pll_clk->name);
+ }
+
+ switch (pll_clk->type) {
+ case pll_2126:
+ init.ops = &samsung_pll2126_clk_ops;
+ break;
+ case pll_3000:
+ init.ops = &samsung_pll3000_clk_ops;
+ break;
+ /* clk_ops for 35xx and 2550 are similar */
+ case pll_35xx:
+ case pll_2550:
+ case pll_1450x:
+ case pll_1451x:
+ case pll_1452x:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll35xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll35xx_clk_ops;
+ break;
+ case pll_4500:
+ init.ops = &samsung_pll45xx_clk_min_ops;
+ break;
+ case pll_4502:
+ case pll_4508:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll45xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll45xx_clk_ops;
+ break;
+ /* clk_ops for 36xx and 2650 are similar */
+ case pll_36xx:
+ case pll_2650:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll36xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll36xx_clk_ops;
+ break;
+ case pll_6552:
+ case pll_6552_s3c2416:
+ init.ops = &samsung_pll6552_clk_ops;
+ break;
+ case pll_6553:
+ init.ops = &samsung_pll6553_clk_ops;
+ break;
+ case pll_4600:
+ case pll_4650:
+ case pll_4650c:
+ case pll_1460x:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll46xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll46xx_clk_ops;
+ break;
+ case pll_s3c2410_mpll:
+ if (!pll->rate_table)
+ init.ops = &samsung_s3c2410_mpll_clk_min_ops;
+ else
+ init.ops = &samsung_s3c2410_mpll_clk_ops;
+ break;
+ case pll_s3c2410_upll:
+ if (!pll->rate_table)
+ init.ops = &samsung_s3c2410_upll_clk_min_ops;
+ else
+ init.ops = &samsung_s3c2410_upll_clk_ops;
+ break;
+ case pll_s3c2440_mpll:
+ if (!pll->rate_table)
+ init.ops = &samsung_s3c2440_mpll_clk_min_ops;
+ else
+ init.ops = &samsung_s3c2440_mpll_clk_ops;
+ break;
+ case pll_2550x:
+ init.ops = &samsung_pll2550x_clk_ops;
+ break;
+ case pll_2550xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2550xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2550xx_clk_ops;
+ break;
+ case pll_2650x:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2650x_clk_min_ops;
+ else
+ init.ops = &samsung_pll2650x_clk_ops;
+ break;
+ case pll_2650xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2650xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2650xx_clk_ops;
+ break;
+ default:
+ pr_warn("%s: Unknown pll type for pll clk %s\n",
+ __func__, pll_clk->name);
+ }
+
+ pll->hw.init = &init;
+ pll->type = pll_clk->type;
+ pll->lock_reg = base + pll_clk->lock_offset;
+ pll->con_reg = base + pll_clk->con_offset;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s : %ld\n",
+ __func__, pll_clk->name, PTR_ERR(clk));
+ kfree(pll);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, pll_clk->id);
+
+ if (!pll_clk->alias)
+ return;
+
+ ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup for %s : %d",
+ __func__, pll_clk->name, ret);
+}
+
+void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+ const struct samsung_pll_clock *pll_list,
+ unsigned int nr_pll, void __iomem *base)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_pll; cnt++)
+ _samsung_clk_register_pll(ctx, &pll_list[cnt], base);
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all PLL's in Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_PLL_H
+#define __SAMSUNG_CLK_PLL_H
+
+enum samsung_pll_type {
+ pll_2126,
+ pll_3000,
+ pll_35xx,
+ pll_36xx,
+ pll_2550,
+ pll_2650,
+ pll_4500,
+ pll_4502,
+ pll_4508,
+ pll_4600,
+ pll_4650,
+ pll_4650c,
+ pll_6552,
+ pll_6552_s3c2416,
+ pll_6553,
+ pll_s3c2410_mpll,
+ pll_s3c2410_upll,
+ pll_s3c2440_mpll,
+ pll_2550x,
+ pll_2550xx,
+ pll_2650x,
+ pll_2650xx,
+ pll_1450x,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
+};
+
+#define PLL_35XX_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .afc = (_afc), \
+ }
+
+#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ .vsel = (_vsel), \
+ }
+
+#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ .mfr = (_mfr), \
+ .mrr = (_mrr), \
+ .vsel = (_vsel), \
+ }
+
+/* NOTE: Rate table should be kept sorted in descending order. */
+
+struct samsung_pll_rate_table {
+ unsigned int rate;
+ unsigned int pdiv;
+ unsigned int mdiv;
+ unsigned int sdiv;
+ unsigned int kdiv;
+ unsigned int afc;
+ unsigned int mfr;
+ unsigned int mrr;
+ unsigned int vsel;
+};
+
+extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
+ const char *pname, const void __iomem *reg_base,
+ const unsigned long offset);
+
+#endif /* __SAMSUNG_CLK_PLL_H */
--- /dev/null
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for s3c24xx external clock output.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include "clk.h"
+
+/* legacy access to misccr, until dt conversion is finished */
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+
+#define MUX_DCLK0 0
+#define MUX_DCLK1 1
+#define DIV_DCLK0 2
+#define DIV_DCLK1 3
+#define GATE_DCLK0 4
+#define GATE_DCLK1 5
+#define MUX_CLKOUT0 6
+#define MUX_CLKOUT1 7
+#define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
+
+enum supported_socs {
+ S3C2410,
+ S3C2412,
+ S3C2440,
+ S3C2443,
+};
+
+struct s3c24xx_dclk_drv_data {
+ const char **clkout0_parent_names;
+ int clkout0_num_parents;
+ const char **clkout1_parent_names;
+ int clkout1_num_parents;
+ const char **mux_parent_names;
+ int mux_num_parents;
+};
+
+/*
+ * Clock for output-parent selection in misccr
+ */
+
+struct s3c24xx_clkout {
+ struct clk_hw hw;
+ u32 mask;
+ u8 shift;
+};
+
+#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
+
+static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
+{
+ struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ u32 val;
+
+ val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
+ val >>= clkout->shift;
+ val &= clkout->mask;
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
+
+ s3c2410_modify_misccr((clkout->mask << clkout->shift),
+ (index << clkout->shift));
+
+ return 0;
+}
+
+static const struct clk_ops s3c24xx_clkout_ops = {
+ .get_parent = s3c24xx_clkout_get_parent,
+ .set_parent = s3c24xx_clkout_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+};
+
+static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
+ const char **parent_names, u8 num_parents,
+ u8 shift, u32 mask)
+{
+ struct s3c24xx_clkout *clkout;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the clkout */
+ clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
+ if (!clkout)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &s3c24xx_clkout_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ clkout->shift = shift;
+ clkout->mask = mask;
+ clkout->hw.init = &init;
+
+ clk = clk_register(dev, &clkout->hw);
+
+ return clk;
+}
+
+/*
+ * dclk and clkout init
+ */
+
+struct s3c24xx_dclk {
+ struct device *dev;
+ void __iomem *base;
+ struct clk_onecell_data clk_data;
+ struct notifier_block dclk0_div_change_nb;
+ struct notifier_block dclk1_div_change_nb;
+ spinlock_t dclk_lock;
+ unsigned long reg_save;
+};
+
+#define to_s3c24xx_dclk0(x) \
+ container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
+
+#define to_s3c24xx_dclk1(x) \
+ container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
+
+static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
+static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
+ "gate_dclk0" };
+static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
+ "gate_dclk1" };
+
+static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
+ "hclk", "pclk", "gate_dclk0" };
+static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
+ "gate_dclk1" };
+
+static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
+ "gate_dclk0" };
+static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
+ "hclk", "pclk", "gate_dclk1" };
+
+static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
+static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
+ "gate_dclk0" };
+static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
+ "hclk", "pclk", "gate_dclk1" };
+
+#define DCLKCON_DCLK_DIV_MASK 0xf
+#define DCLKCON_DCLK0_DIV_SHIFT 4
+#define DCLKCON_DCLK0_CMP_SHIFT 8
+#define DCLKCON_DCLK1_DIV_SHIFT 20
+#define DCLKCON_DCLK1_CMP_SHIFT 24
+
+static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
+ int div_shift, int cmp_shift)
+{
+ unsigned long flags = 0;
+ u32 dclk_con, div, cmp;
+
+ spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
+
+ dclk_con = readl_relaxed(s3c24xx_dclk->base);
+
+ div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
+ cmp = ((div + 1) / 2) - 1;
+
+ dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
+ dclk_con |= (cmp << cmp_shift);
+
+ writel_relaxed(dclk_con, s3c24xx_dclk->base);
+
+ spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
+}
+
+static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
+
+ if (event == POST_RATE_CHANGE) {
+ s3c24xx_dclk_update_cmp(s3c24xx_dclk,
+ DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
+
+ if (event == POST_RATE_CHANGE) {
+ s3c24xx_dclk_update_cmp(s3c24xx_dclk,
+ DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
+ }
+
+ return NOTIFY_DONE;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int s3c24xx_dclk_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+
+ s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
+ return 0;
+}
+
+static int s3c24xx_dclk_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+
+ writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
+ s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
+
+static int s3c24xx_dclk_probe(struct platform_device *pdev)
+{
+ struct s3c24xx_dclk *s3c24xx_dclk;
+ struct resource *mem;
+ struct clk **clk_table;
+ struct s3c24xx_dclk_drv_data *dclk_variant;
+ int ret, i;
+
+ s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk),
+ GFP_KERNEL);
+ if (!s3c24xx_dclk)
+ return -ENOMEM;
+
+ s3c24xx_dclk->dev = &pdev->dev;
+ platform_set_drvdata(pdev, s3c24xx_dclk);
+ spin_lock_init(&s3c24xx_dclk->dclk_lock);
+
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * DCLK_MAX_CLKS,
+ GFP_KERNEL);
+ if (!clk_table)
+ return -ENOMEM;
+
+ s3c24xx_dclk->clk_data.clks = clk_table;
+ s3c24xx_dclk->clk_data.clk_num = DCLK_MAX_CLKS;
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(s3c24xx_dclk->base))
+ return PTR_ERR(s3c24xx_dclk->base);
+
+ dclk_variant = (struct s3c24xx_dclk_drv_data *)
+ platform_get_device_id(pdev)->driver_data;
+
+
+ clk_table[MUX_DCLK0] = clk_register_mux(&pdev->dev, "mux_dclk0",
+ dclk_variant->mux_parent_names,
+ dclk_variant->mux_num_parents, 0,
+ s3c24xx_dclk->base, 1, 1, 0,
+ &s3c24xx_dclk->dclk_lock);
+ clk_table[MUX_DCLK1] = clk_register_mux(&pdev->dev, "mux_dclk1",
+ dclk_variant->mux_parent_names,
+ dclk_variant->mux_num_parents, 0,
+ s3c24xx_dclk->base, 17, 1, 0,
+ &s3c24xx_dclk->dclk_lock);
+
+ clk_table[DIV_DCLK0] = clk_register_divider(&pdev->dev, "div_dclk0",
+ "mux_dclk0", 0, s3c24xx_dclk->base,
+ 4, 4, 0, &s3c24xx_dclk->dclk_lock);
+ clk_table[DIV_DCLK1] = clk_register_divider(&pdev->dev, "div_dclk1",
+ "mux_dclk1", 0, s3c24xx_dclk->base,
+ 20, 4, 0, &s3c24xx_dclk->dclk_lock);
+
+ clk_table[GATE_DCLK0] = clk_register_gate(&pdev->dev, "gate_dclk0",
+ "div_dclk0", CLK_SET_RATE_PARENT,
+ s3c24xx_dclk->base, 0, 0,
+ &s3c24xx_dclk->dclk_lock);
+ clk_table[GATE_DCLK1] = clk_register_gate(&pdev->dev, "gate_dclk1",
+ "div_dclk1", CLK_SET_RATE_PARENT,
+ s3c24xx_dclk->base, 16, 0,
+ &s3c24xx_dclk->dclk_lock);
+
+ clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
+ "clkout0", dclk_variant->clkout0_parent_names,
+ dclk_variant->clkout0_num_parents, 4, 7);
+ clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
+ "clkout1", dclk_variant->clkout1_parent_names,
+ dclk_variant->clkout1_num_parents, 8, 7);
+
+ for (i = 0; i < DCLK_MAX_CLKS; i++)
+ if (IS_ERR(clk_table[i])) {
+ dev_err(&pdev->dev, "clock %d failed to register\n", i);
+ ret = PTR_ERR(clk_table[i]);
+ goto err_clk_register;
+ }
+
+ ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
+ if (!ret)
+ ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL);
+ if (!ret)
+ ret = clk_register_clkdev(clk_table[MUX_CLKOUT0],
+ "clkout0", NULL);
+ if (!ret)
+ ret = clk_register_clkdev(clk_table[MUX_CLKOUT1],
+ "clkout1", NULL);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
+ goto err_clk_register;
+ }
+
+ s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
+ s3c24xx_dclk0_div_notify;
+
+ s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
+ s3c24xx_dclk1_div_notify;
+
+ ret = clk_notifier_register(clk_table[DIV_DCLK0],
+ &s3c24xx_dclk->dclk0_div_change_nb);
+ if (ret)
+ goto err_clk_register;
+
+ ret = clk_notifier_register(clk_table[DIV_DCLK1],
+ &s3c24xx_dclk->dclk1_div_change_nb);
+ if (ret)
+ goto err_dclk_notify;
+
+ return 0;
+
+err_dclk_notify:
+ clk_notifier_unregister(clk_table[DIV_DCLK0],
+ &s3c24xx_dclk->dclk0_div_change_nb);
+err_clk_register:
+ for (i = 0; i < DCLK_MAX_CLKS; i++)
+ if (clk_table[i] && !IS_ERR(clk_table[i]))
+ clk_unregister(clk_table[i]);
+
+ return ret;
+}
+
+static int s3c24xx_dclk_remove(struct platform_device *pdev)
+{
+ struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+ struct clk **clk_table = s3c24xx_dclk->clk_data.clks;
+ int i;
+
+ clk_notifier_unregister(clk_table[DIV_DCLK1],
+ &s3c24xx_dclk->dclk1_div_change_nb);
+ clk_notifier_unregister(clk_table[DIV_DCLK0],
+ &s3c24xx_dclk->dclk0_div_change_nb);
+
+ for (i = 0; i < DCLK_MAX_CLKS; i++)
+ clk_unregister(clk_table[i]);
+
+ return 0;
+}
+
+static struct s3c24xx_dclk_drv_data dclk_variants[] = {
+ [S3C2410] = {
+ .clkout0_parent_names = clkout0_s3c2410_p,
+ .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
+ .clkout1_parent_names = clkout1_s3c2410_p,
+ .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
+ .mux_parent_names = dclk_s3c2410_p,
+ .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
+ },
+ [S3C2412] = {
+ .clkout0_parent_names = clkout0_s3c2412_p,
+ .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
+ .clkout1_parent_names = clkout1_s3c2412_p,
+ .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
+ .mux_parent_names = dclk_s3c2410_p,
+ .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
+ },
+ [S3C2440] = {
+ .clkout0_parent_names = clkout0_s3c2440_p,
+ .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
+ .clkout1_parent_names = clkout1_s3c2440_p,
+ .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
+ .mux_parent_names = dclk_s3c2410_p,
+ .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
+ },
+ [S3C2443] = {
+ .clkout0_parent_names = clkout0_s3c2443_p,
+ .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
+ .clkout1_parent_names = clkout1_s3c2443_p,
+ .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
+ .mux_parent_names = dclk_s3c2443_p,
+ .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
+ },
+};
+
+static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
+ {
+ .name = "s3c2410-dclk",
+ .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
+ }, {
+ .name = "s3c2412-dclk",
+ .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
+ }, {
+ .name = "s3c2440-dclk",
+ .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
+ }, {
+ .name = "s3c2443-dclk",
+ .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
+ },
+ { }
+};
+
+MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
+
+static struct platform_driver s3c24xx_dclk_driver = {
+ .driver = {
+ .name = "s3c24xx-dclk",
+ .pm = &s3c24xx_dclk_pm_ops,
+ .suppress_bind_attrs = true,
+ },
+ .probe = s3c24xx_dclk_probe,
+ .remove = s3c24xx_dclk_remove,
+ .id_table = s3c24xx_dclk_driver_ids,
+};
+module_platform_driver(s3c24xx_dclk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
+MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
--- /dev/null
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for S3C2410 and following SoCs.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/s3c2410.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define LOCKTIME 0x00
+#define MPLLCON 0x04
+#define UPLLCON 0x08
+#define CLKCON 0x0c
+#define CLKSLOW 0x10
+#define CLKDIVN 0x14
+#define CAMDIVN 0x18
+
+/* the soc types */
+enum supported_socs {
+ S3C2410,
+ S3C2440,
+ S3C2442,
+};
+
+/* list of PLLs to be registered */
+enum s3c2410_plls {
+ mpll, upll,
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s3c2410_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long s3c2410_clk_regs[] __initdata = {
+ LOCKTIME,
+ MPLLCON,
+ UPLLCON,
+ CLKCON,
+ CLKSLOW,
+ CLKDIVN,
+ CAMDIVN,
+};
+
+static int s3c2410_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, s3c2410_save,
+ ARRAY_SIZE(s3c2410_clk_regs));
+
+ return 0;
+}
+
+static void s3c2410_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, s3c2410_save,
+ ARRAY_SIZE(s3c2410_clk_regs));
+}
+
+static struct syscore_ops s3c2410_clk_syscore_ops = {
+ .suspend = s3c2410_clk_suspend,
+ .resume = s3c2410_clk_resume,
+};
+
+static void s3c2410_clk_sleep_init(void)
+{
+ s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
+ ARRAY_SIZE(s3c2410_clk_regs));
+ if (!s3c2410_save) {
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+ return;
+ }
+
+ register_syscore_ops(&s3c2410_clk_syscore_ops);
+ return;
+}
+#else
+static void s3c2410_clk_sleep_init(void) {}
+#endif
+
+PNAME(fclk_p) = { "mpll", "div_slow" };
+
+struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
+ MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
+};
+
+static struct clk_div_table divslow_d[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 6 },
+ { .val = 4, .div = 8 },
+ { .val = 5, .div = 10 },
+ { .val = 6, .div = 12 },
+ { .val = 7, .div = 14 },
+ { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
+ DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
+ DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
+};
+
+struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
+ GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
+ GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
+ GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
+ GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
+ GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
+ GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
+ GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
+ GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
+ GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
+ GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
+ GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
+ GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
+ GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
+ GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
+};
+
+/* should be added _after_ the soc-specific clocks are created */
+struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
+ ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
+ ALIAS(PCLK_ADC, NULL, "adc"),
+ ALIAS(PCLK_RTC, NULL, "rtc"),
+ ALIAS(PCLK_PWM, NULL, "timers"),
+ ALIAS(HCLK_LCD, NULL, "lcd"),
+ ALIAS(HCLK_USBD, NULL, "usb-device"),
+ ALIAS(HCLK_USBH, NULL, "usb-host"),
+ ALIAS(UCLK, NULL, "usb-bus-host"),
+ ALIAS(UCLK, NULL, "usb-bus-gadget"),
+ ALIAS(ARMCLK, NULL, "armclk"),
+ ALIAS(UCLK, NULL, "uclk"),
+ ALIAS(HCLK, NULL, "hclk"),
+ ALIAS(MPLL, NULL, "mpll"),
+ ALIAS(FCLK, NULL, "fclk"),
+ ALIAS(PCLK, NULL, "watchdog"),
+ ALIAS(PCLK_SDI, NULL, "sdi"),
+ ALIAS(HCLK_NAND, NULL, "nand"),
+ ALIAS(PCLK_I2S, NULL, "iis"),
+ ALIAS(PCLK_I2C, NULL, "i2c"),
+};
+
+/* S3C2410 specific clocks */
+
+static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* 2410A extras */
+ PLL_35XX_RATE(270000000, 127, 1, 1),
+ PLL_35XX_RATE(268000000, 126, 1, 1),
+ PLL_35XX_RATE(266000000, 125, 1, 1),
+ PLL_35XX_RATE(226000000, 105, 1, 1),
+ PLL_35XX_RATE(210000000, 132, 2, 1),
+ /* 2410 common */
+ PLL_35XX_RATE(203000000, 161, 3, 1),
+ PLL_35XX_RATE(192000000, 88, 1, 1),
+ PLL_35XX_RATE(186000000, 85, 1, 1),
+ PLL_35XX_RATE(180000000, 82, 1, 1),
+ PLL_35XX_RATE(170000000, 77, 1, 1),
+ PLL_35XX_RATE(158000000, 71, 1, 1),
+ PLL_35XX_RATE(152000000, 68, 1, 1),
+ PLL_35XX_RATE(147000000, 90, 2, 1),
+ PLL_35XX_RATE(135000000, 82, 2, 1),
+ PLL_35XX_RATE(124000000, 116, 1, 2),
+ PLL_35XX_RATE(118000000, 150, 2, 2),
+ PLL_35XX_RATE(113000000, 105, 1, 2),
+ PLL_35XX_RATE(101000000, 127, 2, 2),
+ PLL_35XX_RATE(90000000, 112, 2, 2),
+ PLL_35XX_RATE(85000000, 105, 2, 2),
+ PLL_35XX_RATE(79000000, 71, 1, 2),
+ PLL_35XX_RATE(68000000, 82, 2, 2),
+ PLL_35XX_RATE(56000000, 142, 2, 3),
+ PLL_35XX_RATE(48000000, 120, 2, 3),
+ PLL_35XX_RATE(51000000, 161, 3, 3),
+ PLL_35XX_RATE(45000000, 82, 1, 3),
+ PLL_35XX_RATE(34000000, 82, 2, 3),
+ { /* sentinel */ },
+};
+
+static struct samsung_pll_clock s3c2410_plls[] __initdata = {
+ [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
+ LOCKTIME, MPLLCON, NULL),
+ [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
+ LOCKTIME, UPLLCON, NULL),
+};
+
+struct samsung_div_clock s3c2410_dividers[] __initdata = {
+ DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
+};
+
+struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
+ /*
+ * armclk is directly supplied by the fclk, without
+ * switching possibility like on the s3c244x below.
+ */
+ FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
+
+ /* uclk is fed from the unmodified upll */
+ FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
+};
+
+struct samsung_clock_alias s3c2410_aliases[] __initdata = {
+ ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
+ ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
+ ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
+ ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
+ ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
+ ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
+ ALIAS(UCLK, NULL, "clk_uart_baud1"),
+};
+
+/* S3C244x specific clocks */
+
+static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ PLL_35XX_RATE(400000000, 0x5c, 1, 1),
+ PLL_35XX_RATE(390000000, 0x7a, 2, 1),
+ PLL_35XX_RATE(380000000, 0x57, 1, 1),
+ PLL_35XX_RATE(370000000, 0xb1, 4, 1),
+ PLL_35XX_RATE(360000000, 0x70, 2, 1),
+ PLL_35XX_RATE(350000000, 0xa7, 4, 1),
+ PLL_35XX_RATE(340000000, 0x4d, 1, 1),
+ PLL_35XX_RATE(330000000, 0x66, 2, 1),
+ PLL_35XX_RATE(320000000, 0x98, 4, 1),
+ PLL_35XX_RATE(310000000, 0x93, 4, 1),
+ PLL_35XX_RATE(300000000, 0x75, 3, 1),
+ PLL_35XX_RATE(240000000, 0x70, 1, 2),
+ PLL_35XX_RATE(230000000, 0x6b, 1, 2),
+ PLL_35XX_RATE(220000000, 0x66, 1, 2),
+ PLL_35XX_RATE(210000000, 0x84, 2, 2),
+ PLL_35XX_RATE(200000000, 0x5c, 1, 2),
+ PLL_35XX_RATE(190000000, 0x57, 1, 2),
+ PLL_35XX_RATE(180000000, 0x70, 2, 2),
+ PLL_35XX_RATE(170000000, 0x4d, 1, 2),
+ PLL_35XX_RATE(160000000, 0x98, 4, 2),
+ PLL_35XX_RATE(150000000, 0x75, 3, 2),
+ PLL_35XX_RATE(120000000, 0x70, 1, 3),
+ PLL_35XX_RATE(110000000, 0x66, 1, 3),
+ PLL_35XX_RATE(100000000, 0x5c, 1, 3),
+ PLL_35XX_RATE(90000000, 0x70, 2, 3),
+ PLL_35XX_RATE(80000000, 0x98, 4, 3),
+ PLL_35XX_RATE(75000000, 0x75, 3, 3),
+ { /* sentinel */ },
+};
+
+static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
+ [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
+ LOCKTIME, MPLLCON, NULL),
+ [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
+ LOCKTIME, UPLLCON, NULL),
+};
+
+PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
+PNAME(armclk_p) = { "fclk", "hclk" };
+
+struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
+ MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
+ MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
+};
+
+struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
+ FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
+ FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_div_table div_hclk_4_d[] = {
+ { .val = 0, .div = 4 },
+ { .val = 1, .div = 8 },
+ { /* sentinel */ },
+};
+
+static struct clk_div_table div_hclk_3_d[] = {
+ { .val = 0, .div = 3 },
+ { .val = 1, .div = 6 },
+ { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
+ DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
+ DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
+ DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
+ DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
+ DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
+};
+
+struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
+ GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
+};
+
+struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
+ ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
+ ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
+ ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
+ ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
+ ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
+ ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
+ ALIAS(HCLK_CAM, NULL, "camif"),
+ ALIAS(CAMIF, NULL, "camif-upll"),
+};
+
+/* S3C2440 specific clocks */
+
+PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
+
+struct samsung_mux_clock s3c2440_muxes[] __initdata = {
+ MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
+};
+
+struct samsung_gate_clock s3c2440_gates[] __initdata = {
+ GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
+};
+
+/* S3C2442 specific clocks */
+
+struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
+ FFACTOR(0, "upll_3", "upll", 1, 3, 0),
+};
+
+PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
+
+struct samsung_mux_clock s3c2442_muxes[] __initdata = {
+ MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
+};
+
+/*
+ * fixed rate clocks generated outside the soc
+ * Only necessary until the devicetree-move is complete
+ */
+#define XTI 1
+struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
+ FRATE(XTI, "xti", NULL, 0, 0),
+};
+
+static void __init s3c2410_common_clk_register_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ unsigned long xti_f)
+{
+ struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
+
+ s3c2410_common_frate_clks[0].fixed_rate = xti_f;
+ samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
+ ARRAY_SIZE(s3c2410_common_frate_clks));
+
+ samsung_clk_register_alias(ctx, &xti_alias, 1);
+}
+
+void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
+ int current_soc,
+ void __iomem *base)
+{
+ struct samsung_clk_provider *ctx;
+ reg_base = base;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ }
+
+ ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+
+ /* Register external clocks only in non-dt cases */
+ if (!np)
+ s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
+
+ if (current_soc == S3C2410) {
+ if (_get_rate("xti") == 12 * MHZ) {
+ s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
+ s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
+ }
+
+ /* Register PLLs. */
+ samsung_clk_register_pll(ctx, s3c2410_plls,
+ ARRAY_SIZE(s3c2410_plls), reg_base);
+
+ } else { /* S3C2440, S3C2442 */
+ if (_get_rate("xti") == 12 * MHZ) {
+ /*
+ * plls follow different calculation schemes, with the
+ * upll following the same scheme as the s3c2410 plls
+ */
+ s3c244x_common_plls[mpll].rate_table =
+ pll_s3c244x_12mhz_tbl;
+ s3c244x_common_plls[upll].rate_table =
+ pll_s3c2410_12mhz_tbl;
+ }
+
+ /* Register PLLs. */
+ samsung_clk_register_pll(ctx, s3c244x_common_plls,
+ ARRAY_SIZE(s3c244x_common_plls), reg_base);
+ }
+
+ /* Register common internal clocks. */
+ samsung_clk_register_mux(ctx, s3c2410_common_muxes,
+ ARRAY_SIZE(s3c2410_common_muxes));
+ samsung_clk_register_div(ctx, s3c2410_common_dividers,
+ ARRAY_SIZE(s3c2410_common_dividers));
+ samsung_clk_register_gate(ctx, s3c2410_common_gates,
+ ARRAY_SIZE(s3c2410_common_gates));
+
+ if (current_soc == S3C2440 || current_soc == S3C2442) {
+ samsung_clk_register_div(ctx, s3c244x_common_dividers,
+ ARRAY_SIZE(s3c244x_common_dividers));
+ samsung_clk_register_gate(ctx, s3c244x_common_gates,
+ ARRAY_SIZE(s3c244x_common_gates));
+ samsung_clk_register_mux(ctx, s3c244x_common_muxes,
+ ARRAY_SIZE(s3c244x_common_muxes));
+ samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
+ ARRAY_SIZE(s3c244x_common_ffactor));
+ }
+
+ /* Register SoC-specific clocks. */
+ switch (current_soc) {
+ case S3C2410:
+ samsung_clk_register_div(ctx, s3c2410_dividers,
+ ARRAY_SIZE(s3c2410_dividers));
+ samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
+ ARRAY_SIZE(s3c2410_ffactor));
+ samsung_clk_register_alias(ctx, s3c2410_aliases,
+ ARRAY_SIZE(s3c2410_aliases));
+ break;
+ case S3C2440:
+ samsung_clk_register_mux(ctx, s3c2440_muxes,
+ ARRAY_SIZE(s3c2440_muxes));
+ samsung_clk_register_gate(ctx, s3c2440_gates,
+ ARRAY_SIZE(s3c2440_gates));
+ break;
+ case S3C2442:
+ samsung_clk_register_mux(ctx, s3c2442_muxes,
+ ARRAY_SIZE(s3c2442_muxes));
+ samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
+ ARRAY_SIZE(s3c2442_ffactor));
+ break;
+ }
+
+ /*
+ * Register common aliases at the end, as some of the aliased clocks
+ * are SoC specific.
+ */
+ samsung_clk_register_alias(ctx, s3c2410_common_aliases,
+ ARRAY_SIZE(s3c2410_common_aliases));
+
+ if (current_soc == S3C2440 || current_soc == S3C2442) {
+ samsung_clk_register_alias(ctx, s3c244x_common_aliases,
+ ARRAY_SIZE(s3c244x_common_aliases));
+ }
+
+ s3c2410_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+}
+
+static void __init s3c2410_clk_init(struct device_node *np)
+{
+ s3c2410_common_clk_init(np, 0, S3C2410, 0);
+}
+CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
+
+static void __init s3c2440_clk_init(struct device_node *np)
+{
+ s3c2410_common_clk_init(np, 0, S3C2440, 0);
+}
+CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
+
+static void __init s3c2442_clk_init(struct device_node *np)
+{
+ s3c2410_common_clk_init(np, 0, S3C2442, 0);
+}
+CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for S3C2412 and S3C2413.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <linux/reboot.h>
+
+#include <dt-bindings/clock/s3c2412.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define LOCKTIME 0x00
+#define MPLLCON 0x04
+#define UPLLCON 0x08
+#define CLKCON 0x0c
+#define CLKDIVN 0x14
+#define CLKSRC 0x1c
+#define SWRST 0x30
+
+/* list of PLLs to be registered */
+enum s3c2412_plls {
+ mpll, upll,
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s3c2412_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long s3c2412_clk_regs[] __initdata = {
+ LOCKTIME,
+ MPLLCON,
+ UPLLCON,
+ CLKCON,
+ CLKDIVN,
+ CLKSRC,
+};
+
+static int s3c2412_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, s3c2412_save,
+ ARRAY_SIZE(s3c2412_clk_regs));
+
+ return 0;
+}
+
+static void s3c2412_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, s3c2412_save,
+ ARRAY_SIZE(s3c2412_clk_regs));
+}
+
+static struct syscore_ops s3c2412_clk_syscore_ops = {
+ .suspend = s3c2412_clk_suspend,
+ .resume = s3c2412_clk_resume,
+};
+
+static void s3c2412_clk_sleep_init(void)
+{
+ s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
+ ARRAY_SIZE(s3c2412_clk_regs));
+ if (!s3c2412_save) {
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+ return;
+ }
+
+ register_syscore_ops(&s3c2412_clk_syscore_ops);
+ return;
+}
+#else
+static void s3c2412_clk_sleep_init(void) {}
+#endif
+
+static struct clk_div_table divxti_d[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 6 },
+ { .val = 4, .div = 8 },
+ { .val = 5, .div = 10 },
+ { .val = 6, .div = 12 },
+ { .val = 7, .div = 14 },
+ { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2412_dividers[] __initdata = {
+ DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
+ DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
+ DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
+ DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
+ DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
+ DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
+ DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
+ DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
+ DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
+};
+
+struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
+ FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
+};
+
+/*
+ * The first two use the OM[4] setting, which is not readable from
+ * software, so assume it is set to xti.
+ */
+PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
+PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
+
+PNAME(camclk_p) = { "usysclk", "hclk" };
+PNAME(usbclk_p) = { "usysclk", "hclk" };
+PNAME(i2sclk_p) = { "erefclk", "mpll" };
+PNAME(uartclk_p) = { "erefclk", "mpll" };
+PNAME(usysclk_p) = { "urefclk", "upll" };
+PNAME(msysclk_p) = { "mdivclk", "mpll" };
+PNAME(mdivclk_p) = { "xti", "div_xti" };
+PNAME(armclk_p) = { "armdiv", "hclk" };
+
+struct samsung_mux_clock s3c2412_muxes[] __initdata = {
+ MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
+ MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
+ MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
+ MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
+ MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
+ MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
+ MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
+ MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
+ MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
+ MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
+};
+
+static struct samsung_pll_clock s3c2412_plls[] __initdata = {
+ [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
+ LOCKTIME, MPLLCON, NULL),
+ [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
+ LOCKTIME, UPLLCON, NULL),
+};
+
+struct samsung_gate_clock s3c2412_gates[] __initdata = {
+ GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
+ GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
+ GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
+ GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
+ GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
+ GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
+ GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
+ GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
+ GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
+ GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
+ GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
+ GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
+ GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
+ GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
+ GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
+ GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
+ GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
+ GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
+ GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
+ GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
+ GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
+ GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+struct samsung_clock_alias s3c2412_aliases[] __initdata = {
+ ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
+ ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
+ ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
+ ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
+ ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
+ ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
+ ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
+ ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
+ ALIAS(PCLK_ADC, NULL, "adc"),
+ ALIAS(PCLK_RTC, NULL, "rtc"),
+ ALIAS(PCLK_PWM, NULL, "timers"),
+ ALIAS(HCLK_LCD, NULL, "lcd"),
+ ALIAS(PCLK_USBD, NULL, "usb-device"),
+ ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
+ ALIAS(HCLK_USBH, NULL, "usb-host"),
+ ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
+ ALIAS(ARMCLK, NULL, "armclk"),
+ ALIAS(HCLK, NULL, "hclk"),
+ ALIAS(MPLL, NULL, "mpll"),
+ ALIAS(MSYSCLK, NULL, "fclk"),
+};
+
+static int s3c2412_restart(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ /* errata "Watch-dog/Software Reset Problem" specifies that
+ * this reset must be done with the SYSCLK sourced from
+ * EXTCLK instead of FOUT to avoid a glitch in the reset
+ * mechanism.
+ *
+ * See the watchdog section of the S3C2412 manual for more
+ * information on this fix.
+ */
+
+ __raw_writel(0x00, reg_base + CLKSRC);
+ __raw_writel(0x533C2412, reg_base + SWRST);
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block s3c2412_restart_handler = {
+ .notifier_call = s3c2412_restart,
+ .priority = 129,
+};
+
+/*
+ * fixed rate clocks generated outside the soc
+ * Only necessary until the devicetree-move is complete
+ */
+#define XTI 1
+struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
+ FRATE(XTI, "xti", NULL, 0, 0),
+ FRATE(0, "ext", NULL, 0, 0),
+};
+
+static void __init s3c2412_common_clk_register_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ unsigned long xti_f, unsigned long ext_f)
+{
+ /* xtal alias is necessary for the current cpufreq driver */
+ struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
+
+ s3c2412_common_frate_clks[0].fixed_rate = xti_f;
+ s3c2412_common_frate_clks[1].fixed_rate = ext_f;
+ samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
+ ARRAY_SIZE(s3c2412_common_frate_clks));
+
+ samsung_clk_register_alias(ctx, &xti_alias, 1);
+}
+
+void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
+ unsigned long ext_f, void __iomem *base)
+{
+ struct samsung_clk_provider *ctx;
+ int ret;
+ reg_base = base;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ }
+
+ ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+
+ /* Register external clocks only in non-dt cases */
+ if (!np)
+ s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
+
+ /* Register PLLs. */
+ samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
+ reg_base);
+
+ /* Register common internal clocks. */
+ samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
+ samsung_clk_register_div(ctx, s3c2412_dividers,
+ ARRAY_SIZE(s3c2412_dividers));
+ samsung_clk_register_gate(ctx, s3c2412_gates,
+ ARRAY_SIZE(s3c2412_gates));
+ samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
+ ARRAY_SIZE(s3c2412_ffactor));
+ samsung_clk_register_alias(ctx, s3c2412_aliases,
+ ARRAY_SIZE(s3c2412_aliases));
+
+ s3c2412_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ ret = register_restart_handler(&s3c2412_restart_handler);
+ if (ret)
+ pr_warn("cannot register restart handler, %d\n", ret);
+}
+
+static void __init s3c2412_clk_init(struct device_node *np)
+{
+ s3c2412_common_clk_init(np, 0, 0, 0);
+}
+CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for S3C2443 and following SoCs.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <linux/reboot.h>
+
+#include <dt-bindings/clock/s3c2443.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+/* S3C2416 clock controller register offsets */
+#define LOCKCON0 0x00
+#define LOCKCON1 0x04
+#define MPLLCON 0x10
+#define EPLLCON 0x18
+#define EPLLCON_K 0x1C
+#define CLKSRC 0x20
+#define CLKDIV0 0x24
+#define CLKDIV1 0x28
+#define CLKDIV2 0x2C
+#define HCLKCON 0x30
+#define PCLKCON 0x34
+#define SCLKCON 0x38
+#define SWRST 0x44
+
+/* the soc types */
+enum supported_socs {
+ S3C2416,
+ S3C2443,
+ S3C2450,
+};
+
+/* list of PLLs to be registered */
+enum s3c2443_plls {
+ mpll, epll,
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s3c2443_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long s3c2443_clk_regs[] __initdata = {
+ LOCKCON0,
+ LOCKCON1,
+ MPLLCON,
+ EPLLCON,
+ EPLLCON_K,
+ CLKSRC,
+ CLKDIV0,
+ CLKDIV1,
+ CLKDIV2,
+ PCLKCON,
+ HCLKCON,
+ SCLKCON,
+};
+
+static int s3c2443_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, s3c2443_save,
+ ARRAY_SIZE(s3c2443_clk_regs));
+
+ return 0;
+}
+
+static void s3c2443_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, s3c2443_save,
+ ARRAY_SIZE(s3c2443_clk_regs));
+}
+
+static struct syscore_ops s3c2443_clk_syscore_ops = {
+ .suspend = s3c2443_clk_suspend,
+ .resume = s3c2443_clk_resume,
+};
+
+static void s3c2443_clk_sleep_init(void)
+{
+ s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs,
+ ARRAY_SIZE(s3c2443_clk_regs));
+ if (!s3c2443_save) {
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+ return;
+ }
+
+ register_syscore_ops(&s3c2443_clk_syscore_ops);
+ return;
+}
+#else
+static void s3c2443_clk_sleep_init(void) {}
+#endif
+
+PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
+PNAME(esysclk_p) = { "epllref", "epll" };
+PNAME(mpllref_p) = { "xti", "mdivclk" };
+PNAME(msysclk_p) = { "mpllref", "mpll" };
+PNAME(armclk_p) = { "armdiv" , "hclk" };
+PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
+
+struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
+ MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
+ MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
+ MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
+ MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"),
+ MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"),
+ MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
+};
+
+static struct clk_div_table hclk_d[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 3, .div = 4 },
+ { /* sentinel */ },
+};
+
+static struct clk_div_table mdivclk_d[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 3 },
+ { .val = 2, .div = 5 },
+ { .val = 3, .div = 7 },
+ { .val = 4, .div = 9 },
+ { .val = 5, .div = 11 },
+ { .val = 6, .div = 13 },
+ { .val = 7, .div = 15 },
+ { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
+ DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
+ DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
+ DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
+ DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
+ DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
+ DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
+ DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
+ DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
+ DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
+ DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
+};
+
+struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
+ GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
+ GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
+ GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
+ GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
+ GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
+ GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
+ GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
+ GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
+ GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
+ GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
+ GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
+ GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
+ GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
+ GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
+ GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
+ GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
+ GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
+ GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
+ GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
+ GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
+ GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
+ GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
+ GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
+};
+
+struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
+ ALIAS(HCLK, NULL, "hclk"),
+ ALIAS(HCLK_SSMC, NULL, "nand"),
+ ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
+ ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
+ ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
+ ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
+ ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
+ ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
+ ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
+ ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
+ ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
+ ALIAS(PCLK_PWM, NULL, "timers"),
+ ALIAS(PCLK_RTC, NULL, "rtc"),
+ ALIAS(PCLK_WDT, NULL, "watchdog"),
+ ALIAS(PCLK_ADC, NULL, "adc"),
+ ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
+ ALIAS(HCLK_USBD, NULL, "usb-device"),
+ ALIAS(HCLK_USBH, NULL, "usb-host"),
+ ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
+ ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
+ ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
+ ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
+ ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
+ ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
+ ALIAS(SCLK_I2S0, NULL, "i2s-if"),
+ ALIAS(HCLK_LCD, NULL, "lcd"),
+ ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
+};
+
+/* S3C2416 specific clocks */
+
+static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
+ [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
+ LOCKCON0, MPLLCON, NULL),
+ [epll] = PLL(pll_6553, 0, "epll", "epllref",
+ LOCKCON1, EPLLCON, NULL),
+};
+
+PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
+PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
+PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
+
+static struct clk_div_table armdiv_s3c2416_d[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 3 },
+ { .val = 3, .div = 4 },
+ { .val = 5, .div = 6 },
+ { .val = 7, .div = 8 },
+ { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2416_dividers[] __initdata = {
+ DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
+ DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
+ DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
+};
+
+struct samsung_mux_clock s3c2416_muxes[] __initdata = {
+ MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
+ MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
+ MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
+};
+
+struct samsung_gate_clock s3c2416_gates[] __initdata = {
+ GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
+ GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
+ GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
+ GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
+ GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
+ GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
+};
+
+struct samsung_clock_alias s3c2416_aliases[] __initdata = {
+ ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
+ ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
+ ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
+ ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
+ ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
+ ALIAS(ARMDIV, NULL, "armdiv"),
+};
+
+/* S3C2443 specific clocks */
+
+static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
+ [mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
+ LOCKCON0, MPLLCON, NULL),
+ [epll] = PLL(pll_2126, 0, "epll", "epllref",
+ LOCKCON1, EPLLCON, NULL),
+};
+
+static struct clk_div_table armdiv_s3c2443_d[] = {
+ { .val = 0, .div = 1 },
+ { .val = 8, .div = 2 },
+ { .val = 2, .div = 3 },
+ { .val = 9, .div = 4 },
+ { .val = 10, .div = 6 },
+ { .val = 11, .div = 8 },
+ { .val = 13, .div = 12 },
+ { .val = 15, .div = 16 },
+ { /* sentinel */ },
+};
+
+struct samsung_div_clock s3c2443_dividers[] __initdata = {
+ DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
+ DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
+};
+
+struct samsung_gate_clock s3c2443_gates[] __initdata = {
+ GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
+ GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
+ GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
+ GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
+ GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
+};
+
+struct samsung_clock_alias s3c2443_aliases[] __initdata = {
+ ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
+ ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
+ ALIAS(SCLK_CAM, NULL, "camif-upll"),
+ ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
+ ALIAS(PCLK_SDI, NULL, "sdi"),
+ ALIAS(HCLK_CFC, NULL, "cfc"),
+ ALIAS(ARMDIV, NULL, "armdiv"),
+};
+
+/* S3C2450 specific clocks */
+
+PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
+PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
+PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
+
+struct samsung_div_clock s3c2450_dividers[] __initdata = {
+ DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
+ DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
+ DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
+ DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
+};
+
+struct samsung_mux_clock s3c2450_muxes[] __initdata = {
+ MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
+ MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
+ MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
+};
+
+struct samsung_gate_clock s3c2450_gates[] __initdata = {
+ GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
+ GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
+ GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
+ GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
+ GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
+ GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
+};
+
+struct samsung_clock_alias s3c2450_aliases[] __initdata = {
+ ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
+ ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
+ ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
+ ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
+};
+
+static int s3c2443_restart(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ __raw_writel(0x533c2443, reg_base + SWRST);
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block s3c2443_restart_handler = {
+ .notifier_call = s3c2443_restart,
+ .priority = 129,
+};
+
+/*
+ * fixed rate clocks generated outside the soc
+ * Only necessary until the devicetree-move is complete
+ */
+struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
+ FRATE(0, "xti", NULL, 0, 0),
+ FRATE(0, "ext", NULL, 0, 0),
+ FRATE(0, "ext_i2s", NULL, 0, 0),
+ FRATE(0, "ext_uart", NULL, 0, 0),
+};
+
+static void __init s3c2443_common_clk_register_fixed_ext(
+ struct samsung_clk_provider *ctx, unsigned long xti_f)
+{
+ s3c2443_common_frate_clks[0].fixed_rate = xti_f;
+ samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
+ ARRAY_SIZE(s3c2443_common_frate_clks));
+}
+
+void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
+ int current_soc,
+ void __iomem *base)
+{
+ struct samsung_clk_provider *ctx;
+ int ret;
+ reg_base = base;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ }
+
+ ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+
+ /* Register external clocks only in non-dt cases */
+ if (!np)
+ s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
+
+ /* Register PLLs. */
+ if (current_soc == S3C2416 || current_soc == S3C2450)
+ samsung_clk_register_pll(ctx, s3c2416_pll_clks,
+ ARRAY_SIZE(s3c2416_pll_clks), reg_base);
+ else
+ samsung_clk_register_pll(ctx, s3c2443_pll_clks,
+ ARRAY_SIZE(s3c2443_pll_clks), reg_base);
+
+ /* Register common internal clocks. */
+ samsung_clk_register_mux(ctx, s3c2443_common_muxes,
+ ARRAY_SIZE(s3c2443_common_muxes));
+ samsung_clk_register_div(ctx, s3c2443_common_dividers,
+ ARRAY_SIZE(s3c2443_common_dividers));
+ samsung_clk_register_gate(ctx, s3c2443_common_gates,
+ ARRAY_SIZE(s3c2443_common_gates));
+ samsung_clk_register_alias(ctx, s3c2443_common_aliases,
+ ARRAY_SIZE(s3c2443_common_aliases));
+
+ /* Register SoC-specific clocks. */
+ switch (current_soc) {
+ case S3C2450:
+ samsung_clk_register_div(ctx, s3c2450_dividers,
+ ARRAY_SIZE(s3c2450_dividers));
+ samsung_clk_register_mux(ctx, s3c2450_muxes,
+ ARRAY_SIZE(s3c2450_muxes));
+ samsung_clk_register_gate(ctx, s3c2450_gates,
+ ARRAY_SIZE(s3c2450_gates));
+ samsung_clk_register_alias(ctx, s3c2450_aliases,
+ ARRAY_SIZE(s3c2450_aliases));
+ /* fall through, as s3c2450 extends the s3c2416 clocks */
+ case S3C2416:
+ samsung_clk_register_div(ctx, s3c2416_dividers,
+ ARRAY_SIZE(s3c2416_dividers));
+ samsung_clk_register_mux(ctx, s3c2416_muxes,
+ ARRAY_SIZE(s3c2416_muxes));
+ samsung_clk_register_gate(ctx, s3c2416_gates,
+ ARRAY_SIZE(s3c2416_gates));
+ samsung_clk_register_alias(ctx, s3c2416_aliases,
+ ARRAY_SIZE(s3c2416_aliases));
+ break;
+ case S3C2443:
+ samsung_clk_register_div(ctx, s3c2443_dividers,
+ ARRAY_SIZE(s3c2443_dividers));
+ samsung_clk_register_gate(ctx, s3c2443_gates,
+ ARRAY_SIZE(s3c2443_gates));
+ samsung_clk_register_alias(ctx, s3c2443_aliases,
+ ARRAY_SIZE(s3c2443_aliases));
+ break;
+ }
+
+ s3c2443_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ ret = register_restart_handler(&s3c2443_restart_handler);
+ if (ret)
+ pr_warn("cannot register restart handler, %d\n", ret);
+}
+
+static void __init s3c2416_clk_init(struct device_node *np)
+{
+ s3c2443_common_clk_init(np, 0, S3C2416, 0);
+}
+CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
+
+static void __init s3c2443_clk_init(struct device_node *np)
+{
+ s3c2443_common_clk_init(np, 0, S3C2443, 0);
+}
+CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
+
+static void __init s3c2450_clk_init(struct device_node *np)
+{
+ s3c2443_common_clk_init(np, 0, S3C2450, 0);
+}
+CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all S3C64xx SoCs.
+*/
+
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+/* S3C64xx clock controller register offsets. */
+#define APLL_LOCK 0x000
+#define MPLL_LOCK 0x004
+#define EPLL_LOCK 0x008
+#define APLL_CON 0x00c
+#define MPLL_CON 0x010
+#define EPLL_CON0 0x014
+#define EPLL_CON1 0x018
+#define CLK_SRC 0x01c
+#define CLK_DIV0 0x020
+#define CLK_DIV1 0x024
+#define CLK_DIV2 0x028
+#define HCLK_GATE 0x030
+#define PCLK_GATE 0x034
+#define SCLK_GATE 0x038
+#define MEM0_GATE 0x03c
+#define CLK_SRC2 0x10c
+#define OTHERS 0x900
+
+/* Helper macros to define clock arrays. */
+#define FIXED_RATE_CLOCKS(name) \
+ static struct samsung_fixed_rate_clock name[]
+#define MUX_CLOCKS(name) \
+ static struct samsung_mux_clock name[]
+#define DIV_CLOCKS(name) \
+ static struct samsung_div_clock name[]
+#define GATE_CLOCKS(name) \
+ static struct samsung_gate_clock name[]
+
+/* Helper macros for gate types present on S3C64xx. */
+#define GATE_BUS(_id, cname, pname, o, b) \
+ GATE(_id, cname, pname, o, b, 0, 0)
+#define GATE_SCLK(_id, cname, pname, o, b) \
+ GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
+#define GATE_ON(_id, cname, pname, o, b) \
+ GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
+
+/* list of PLLs to be registered */
+enum s3c64xx_plls {
+ apll, mpll, epll,
+};
+
+static void __iomem *reg_base;
+static bool is_s3c6400;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s3c64xx_save_common;
+static struct samsung_clk_reg_dump *s3c64xx_save_soc;
+
+/*
+ * List of controller registers to be saved and restored during
+ * a suspend/resume cycle.
+ */
+static unsigned long s3c64xx_clk_regs[] __initdata = {
+ APLL_LOCK,
+ MPLL_LOCK,
+ EPLL_LOCK,
+ APLL_CON,
+ MPLL_CON,
+ EPLL_CON0,
+ EPLL_CON1,
+ CLK_SRC,
+ CLK_DIV0,
+ CLK_DIV1,
+ CLK_DIV2,
+ HCLK_GATE,
+ PCLK_GATE,
+ SCLK_GATE,
+};
+
+static unsigned long s3c6410_clk_regs[] __initdata = {
+ CLK_SRC2,
+ MEM0_GATE,
+};
+
+static int s3c64xx_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, s3c64xx_save_common,
+ ARRAY_SIZE(s3c64xx_clk_regs));
+
+ if (!is_s3c6400)
+ samsung_clk_save(reg_base, s3c64xx_save_soc,
+ ARRAY_SIZE(s3c6410_clk_regs));
+
+ return 0;
+}
+
+static void s3c64xx_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, s3c64xx_save_common,
+ ARRAY_SIZE(s3c64xx_clk_regs));
+
+ if (!is_s3c6400)
+ samsung_clk_restore(reg_base, s3c64xx_save_soc,
+ ARRAY_SIZE(s3c6410_clk_regs));
+}
+
+static struct syscore_ops s3c64xx_clk_syscore_ops = {
+ .suspend = s3c64xx_clk_suspend,
+ .resume = s3c64xx_clk_resume,
+};
+
+static void s3c64xx_clk_sleep_init(void)
+{
+ s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
+ ARRAY_SIZE(s3c64xx_clk_regs));
+ if (!s3c64xx_save_common)
+ goto err_warn;
+
+ if (!is_s3c6400) {
+ s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
+ ARRAY_SIZE(s3c6410_clk_regs));
+ if (!s3c64xx_save_soc)
+ goto err_soc;
+ }
+
+ register_syscore_ops(&s3c64xx_clk_syscore_ops);
+ return;
+
+err_soc:
+ kfree(s3c64xx_save_common);
+err_warn:
+ pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
+ __func__);
+}
+#else
+static void s3c64xx_clk_sleep_init(void) {}
+#endif
+
+/* List of parent clocks common for all S3C64xx SoCs. */
+PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
+PNAME(uart_p) = { "mout_epll", "dout_mpll" };
+PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
+ "pcmcdclk0", "none", "none", "none" };
+PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
+ "pcmcdclk0", "none", "none", "none" };
+PNAME(mfc_p) = { "hclkx2", "mout_epll" };
+PNAME(apll_p) = { "fin_pll", "fout_apll" };
+PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
+PNAME(epll_p) = { "fin_pll", "fout_epll" };
+PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
+
+/* S3C6400-specific parent clocks. */
+PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
+PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
+PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
+
+/* S3C6410-specific parent clocks. */
+PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
+PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
+PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
+PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
+PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
+ "pcmcdclk1", "none", "none", "none" };
+
+/* Fixed rate clocks generated outside the SoC. */
+FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
+ FRATE(0, "fin_pll", NULL, 0, 0),
+ FRATE(0, "xusbxti", NULL, 0, 0),
+};
+
+/* Fixed rate clocks generated inside the SoC. */
+FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
+ FRATE(CLK27M, "clk27m", NULL, 0, 27000000),
+ FRATE(CLK48M, "clk48m", NULL, 0, 48000000),
+};
+
+/* List of clock muxes present on all S3C64xx SoCs. */
+MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
+ MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
+ MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
+ MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
+ MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
+ MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
+ MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
+ MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
+ MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
+ MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
+ MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
+ MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
+ MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
+ MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
+};
+
+/* List of clock muxes present on S3C6400. */
+MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
+ MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
+ MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
+ MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
+ MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
+};
+
+/* List of clock muxes present on S3C6410. */
+MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
+ MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
+ MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
+ MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
+ MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
+ MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
+ MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
+ MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
+};
+
+/* List of clock dividers present on all S3C64xx SoCs. */
+DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
+ DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
+ DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
+ DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
+ DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
+ DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
+ DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
+ DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
+ DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
+ DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
+ DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
+ DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
+ DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
+ DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
+ DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
+ DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
+ DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
+ DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
+ DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
+ DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
+ DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
+};
+
+/* List of clock dividers present on S3C6400. */
+DIV_CLOCKS(s3c6400_div_clks) __initdata = {
+ DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
+};
+
+/* List of clock dividers present on S3C6410. */
+DIV_CLOCKS(s3c6410_div_clks) __initdata = {
+ DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
+ DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
+ DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
+};
+
+/* List of clock gates present on all S3C64xx SoCs. */
+GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
+ GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
+ GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
+ GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
+ GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
+ GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
+ GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
+ GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
+ GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
+ GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
+ GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
+ GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
+ GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
+ GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
+ GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
+ GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
+ GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
+ GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
+ GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
+ GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
+ GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
+ GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
+ GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
+ GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
+ GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
+ GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
+ GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
+ GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
+ GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
+ GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
+ GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
+ GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
+ GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
+ GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
+ GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
+ GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
+ GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
+ GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
+ GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
+ GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
+ GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
+ GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
+ GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
+ GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
+ GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
+ GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
+ GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
+ GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
+ GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
+ GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
+ GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
+ GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
+ GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
+ GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
+ GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
+ GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
+ GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
+ GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
+ GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
+ GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
+ GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
+ GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
+ GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
+ GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
+ GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
+ GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
+ GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
+ GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
+ GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
+ GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
+ GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
+ GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
+ GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
+ GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
+ GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
+ GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
+ GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
+};
+
+/* List of clock gates present on S3C6400. */
+GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
+ GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
+ GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
+};
+
+/* List of clock gates present on S3C6410. */
+GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
+ GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
+ GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
+ GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
+ GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
+ GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
+ GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
+ GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
+ GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
+ GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
+ GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
+ GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
+ GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
+ GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
+ GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
+};
+
+/* List of PLL clocks. */
+static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
+ [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON, NULL),
+ [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
+ MPLL_LOCK, MPLL_CON, NULL),
+ [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, NULL),
+};
+
+/* Aliases for common s3c64xx clocks. */
+static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
+ ALIAS(FOUT_APLL, NULL, "fout_apll"),
+ ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
+ ALIAS(FOUT_EPLL, NULL, "fout_epll"),
+ ALIAS(MOUT_EPLL, NULL, "mout_epll"),
+ ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
+ ALIAS(HCLKX2, NULL, "hclk2"),
+ ALIAS(HCLK, NULL, "hclk"),
+ ALIAS(PCLK, NULL, "pclk"),
+ ALIAS(PCLK, NULL, "clk_uart_baud2"),
+ ALIAS(ARMCLK, NULL, "armclk"),
+ ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
+ ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
+ ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
+ ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
+ ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
+ ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
+ ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
+ ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
+ ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
+ ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
+ ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
+ ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
+ ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
+ ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
+ ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
+ ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
+ ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
+ ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
+ ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
+ ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
+ ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
+ ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
+ ALIAS(PCLK_PWM, NULL, "timers"),
+ ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
+ ALIAS(PCLK_WDT, NULL, "watchdog"),
+ ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
+ ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
+ ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
+ ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
+ ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
+ ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
+ ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
+ ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
+ ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
+ ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
+ ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
+ ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
+ ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
+ ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
+ ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
+ ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
+ ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
+ ALIAS(SCLK_CAM, "s3c-camif", "camera"),
+};
+
+/* Aliases for s3c6400-specific clocks. */
+static struct samsung_clock_alias s3c6400_clock_aliases[] = {
+ /* Nothing to place here yet. */
+};
+
+/* Aliases for s3c6410-specific clocks. */
+static struct samsung_clock_alias s3c6410_clock_aliases[] = {
+ ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
+ ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
+ ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
+ ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
+ ALIAS(MEM0_SROM, NULL, "srom"),
+};
+
+static void __init s3c64xx_clk_register_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ unsigned long fin_pll_f,
+ unsigned long xusbxti_f)
+{
+ s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
+ s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
+ samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
+ ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
+}
+
+/* Register s3c64xx clocks. */
+void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
+ unsigned long xusbxti_f, bool s3c6400,
+ void __iomem *base)
+{
+ struct samsung_clk_provider *ctx;
+
+ reg_base = base;
+ is_s3c6400 = s3c6400;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ }
+
+ ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+
+ /* Register external clocks. */
+ if (!np)
+ s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
+
+ /* Register PLLs. */
+ samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
+ ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
+
+ /* Register common internal clocks. */
+ samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
+ ARRAY_SIZE(s3c64xx_fixed_rate_clks));
+ samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
+ ARRAY_SIZE(s3c64xx_mux_clks));
+ samsung_clk_register_div(ctx, s3c64xx_div_clks,
+ ARRAY_SIZE(s3c64xx_div_clks));
+ samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
+ ARRAY_SIZE(s3c64xx_gate_clks));
+
+ /* Register SoC-specific clocks. */
+ if (is_s3c6400) {
+ samsung_clk_register_mux(ctx, s3c6400_mux_clks,
+ ARRAY_SIZE(s3c6400_mux_clks));
+ samsung_clk_register_div(ctx, s3c6400_div_clks,
+ ARRAY_SIZE(s3c6400_div_clks));
+ samsung_clk_register_gate(ctx, s3c6400_gate_clks,
+ ARRAY_SIZE(s3c6400_gate_clks));
+ samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
+ ARRAY_SIZE(s3c6400_clock_aliases));
+ } else {
+ samsung_clk_register_mux(ctx, s3c6410_mux_clks,
+ ARRAY_SIZE(s3c6410_mux_clks));
+ samsung_clk_register_div(ctx, s3c6410_div_clks,
+ ARRAY_SIZE(s3c6410_div_clks));
+ samsung_clk_register_gate(ctx, s3c6410_gate_clks,
+ ARRAY_SIZE(s3c6410_gate_clks));
+ samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
+ ARRAY_SIZE(s3c6410_clock_aliases));
+ }
+
+ samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
+ ARRAY_SIZE(s3c64xx_clock_aliases));
+ s3c64xx_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ pr_info("%s clocks: apll = %lu, mpll = %lu\n"
+ "\tepll = %lu, arm_clk = %lu\n",
+ is_s3c6400 ? "S3C6400" : "S3C6410",
+ _get_rate("fout_apll"), _get_rate("fout_mpll"),
+ _get_rate("fout_epll"), _get_rate("armclk"));
+}
+
+static void __init s3c6400_clk_init(struct device_node *np)
+{
+ s3c64xx_clk_init(np, 0, 0, true, NULL);
+}
+CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
+
+static void __init s3c6410_clk_init(struct device_node *np)
+{
+ s3c64xx_clk_init(np, 0, 0, false, NULL);
+}
+CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com>
+ *
+ * Based on Exynos Audio Subsystem Clock Controller driver:
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
+*/
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/s5pv210-audss.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+#ifdef CONFIG_PM_SLEEP
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
+};
+
+static int s5pv210_audss_clk_suspend(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+ reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+ return 0;
+}
+
+static void s5pv210_audss_clk_resume(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+ writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops s5pv210_audss_clk_syscore_ops = {
+ .suspend = s5pv210_audss_clk_suspend,
+ .resume = s5pv210_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* register s5pv210_audss clocks */
+static int s5pv210_audss_clk_probe(struct platform_device *pdev)
+{
+ int i, ret = 0;
+ struct resource *res;
+ const char *mout_audss_p[2];
+ const char *mout_i2s_p[3];
+ const char *hclk_p;
+ struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg_base)) {
+ dev_err(&pdev->dev, "failed to map audss registers\n");
+ return PTR_ERR(reg_base);
+ }
+
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * AUDSS_MAX_CLKS,
+ GFP_KERNEL);
+ if (!clk_table)
+ return -ENOMEM;
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = AUDSS_MAX_CLKS;
+
+ hclk = devm_clk_get(&pdev->dev, "hclk");
+ if (IS_ERR(hclk)) {
+ dev_err(&pdev->dev, "failed to get hclk clock\n");
+ return PTR_ERR(hclk);
+ }
+
+ pll_in = devm_clk_get(&pdev->dev, "fout_epll");
+ if (IS_ERR(pll_in)) {
+ dev_err(&pdev->dev, "failed to get fout_epll clock\n");
+ return PTR_ERR(pll_in);
+ }
+
+ sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
+ if (IS_ERR(sclk_audio)) {
+ dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
+ return PTR_ERR(sclk_audio);
+ }
+
+ /* iiscdclk0 is an optional external I2S codec clock */
+ cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
+ pll_ref = devm_clk_get(&pdev->dev, "xxti");
+
+ if (!IS_ERR(pll_ref))
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ else
+ mout_audss_p[0] = "xxti";
+ mout_audss_p[1] = __clk_get_name(pll_in);
+ clk_table[CLK_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ mout_audss_p, ARRAY_SIZE(mout_audss_p),
+ CLK_SET_RATE_NO_REPARENT,
+ reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
+ mout_i2s_p[0] = "mout_audss";
+ if (!IS_ERR(cdclk))
+ mout_i2s_p[1] = __clk_get_name(cdclk);
+ else
+ mout_i2s_p[1] = "iiscdclk0";
+ mout_i2s_p[2] = __clk_get_name(sclk_audio);
+ clk_table[CLK_MOUT_I2S_A] = clk_register_mux(NULL, "mout_i2s_audss",
+ mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
+ CLK_SET_RATE_NO_REPARENT,
+ reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+
+ clk_table[CLK_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ "dout_aud_bus", "mout_audss", 0,
+ reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
+ clk_table[CLK_DOUT_I2S_A] = clk_register_divider(NULL, "dout_i2s_audss",
+ "mout_i2s_audss", 0, reg_base + ASS_CLK_DIV,
+ 4, 4, 0, &lock);
+
+ clk_table[CLK_I2S] = clk_register_gate(NULL, "i2s_audss",
+ "dout_i2s_audss", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 6, 0, &lock);
+
+ hclk_p = __clk_get_name(hclk);
+
+ clk_table[CLK_HCLK_I2S] = clk_register_gate(NULL, "hclk_i2s_audss",
+ hclk_p, CLK_IGNORE_UNUSED,
+ reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ clk_table[CLK_HCLK_UART] = clk_register_gate(NULL, "hclk_uart_audss",
+ hclk_p, CLK_IGNORE_UNUSED,
+ reg_base + ASS_CLK_GATE, 4, 0, &lock);
+ clk_table[CLK_HCLK_HWA] = clk_register_gate(NULL, "hclk_hwa_audss",
+ hclk_p, CLK_IGNORE_UNUSED,
+ reg_base + ASS_CLK_GATE, 3, 0, &lock);
+ clk_table[CLK_HCLK_DMA] = clk_register_gate(NULL, "hclk_dma_audss",
+ hclk_p, CLK_IGNORE_UNUSED,
+ reg_base + ASS_CLK_GATE, 2, 0, &lock);
+ clk_table[CLK_HCLK_BUF] = clk_register_gate(NULL, "hclk_buf_audss",
+ hclk_p, CLK_IGNORE_UNUSED,
+ reg_base + ASS_CLK_GATE, 1, 0, &lock);
+ clk_table[CLK_HCLK_RP] = clk_register_gate(NULL, "hclk_rp_audss",
+ hclk_p, CLK_IGNORE_UNUSED,
+ reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+ for (i = 0; i < clk_data.clk_num; i++) {
+ if (IS_ERR(clk_table[i])) {
+ dev_err(&pdev->dev, "failed to register clock %d\n", i);
+ ret = PTR_ERR(clk_table[i]);
+ goto unregister;
+ }
+ }
+
+ ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ &clk_data);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add clock provider\n");
+ goto unregister;
+ }
+
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&s5pv210_audss_clk_syscore_ops);
+#endif
+
+ return 0;
+
+unregister:
+ for (i = 0; i < clk_data.clk_num; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister(clk_table[i]);
+ }
+
+ return ret;
+}
+
+static const struct of_device_id s5pv210_audss_clk_of_match[] = {
+ { .compatible = "samsung,s5pv210-audss-clock", },
+ {},
+};
+
+static struct platform_driver s5pv210_audss_clk_driver = {
+ .driver = {
+ .name = "s5pv210-audss-clk",
+ .suppress_bind_attrs = true,
+ .of_match_table = s5pv210_audss_clk_of_match,
+ },
+ .probe = s5pv210_audss_clk_probe,
+};
+
+static int __init s5pv210_audss_clk_init(void)
+{
+ return platform_driver_register(&s5pv210_audss_clk_driver);
+}
+core_initcall(s5pv210_audss_clk_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ *
+ * Based on clock drivers for S3C64xx and Exynos4 SoCs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clock/s5pv210.h>
+
+/* S5PC110/S5PV210 clock controller register offsets */
+#define APLL_LOCK 0x0000
+#define MPLL_LOCK 0x0008
+#define EPLL_LOCK 0x0010
+#define VPLL_LOCK 0x0020
+#define APLL_CON0 0x0100
+#define APLL_CON1 0x0104
+#define MPLL_CON 0x0108
+#define EPLL_CON0 0x0110
+#define EPLL_CON1 0x0114
+#define VPLL_CON 0x0120
+#define CLK_SRC0 0x0200
+#define CLK_SRC1 0x0204
+#define CLK_SRC2 0x0208
+#define CLK_SRC3 0x020c
+#define CLK_SRC4 0x0210
+#define CLK_SRC5 0x0214
+#define CLK_SRC6 0x0218
+#define CLK_SRC_MASK0 0x0280
+#define CLK_SRC_MASK1 0x0284
+#define CLK_DIV0 0x0300
+#define CLK_DIV1 0x0304
+#define CLK_DIV2 0x0308
+#define CLK_DIV3 0x030c
+#define CLK_DIV4 0x0310
+#define CLK_DIV5 0x0314
+#define CLK_DIV6 0x0318
+#define CLK_DIV7 0x031c
+#define CLK_GATE_MAIN0 0x0400
+#define CLK_GATE_MAIN1 0x0404
+#define CLK_GATE_MAIN2 0x0408
+#define CLK_GATE_PERI0 0x0420
+#define CLK_GATE_PERI1 0x0424
+#define CLK_GATE_SCLK0 0x0440
+#define CLK_GATE_SCLK1 0x0444
+#define CLK_GATE_IP0 0x0460
+#define CLK_GATE_IP1 0x0464
+#define CLK_GATE_IP2 0x0468
+#define CLK_GATE_IP3 0x046c
+#define CLK_GATE_IP4 0x0470
+#define CLK_GATE_BLOCK 0x0480
+#define CLK_GATE_IP5 0x0484
+#define CLK_OUT 0x0500
+#define MISC 0xe000
+#define OM_STAT 0xe100
+
+/* IDs of PLLs available on S5PV210/S5P6442 SoCs */
+enum {
+ apll,
+ mpll,
+ epll,
+ vpll,
+};
+
+/* IDs of external clocks (used for legacy boards) */
+enum {
+ xxti,
+ xusbxti,
+};
+
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *s5pv210_clk_dump;
+
+/* List of registers that need to be preserved across suspend/resume. */
+static unsigned long s5pv210_clk_regs[] __initdata = {
+ CLK_SRC0,
+ CLK_SRC1,
+ CLK_SRC2,
+ CLK_SRC3,
+ CLK_SRC4,
+ CLK_SRC5,
+ CLK_SRC6,
+ CLK_SRC_MASK0,
+ CLK_SRC_MASK1,
+ CLK_DIV0,
+ CLK_DIV1,
+ CLK_DIV2,
+ CLK_DIV3,
+ CLK_DIV4,
+ CLK_DIV5,
+ CLK_DIV6,
+ CLK_DIV7,
+ CLK_GATE_MAIN0,
+ CLK_GATE_MAIN1,
+ CLK_GATE_MAIN2,
+ CLK_GATE_PERI0,
+ CLK_GATE_PERI1,
+ CLK_GATE_SCLK0,
+ CLK_GATE_SCLK1,
+ CLK_GATE_IP0,
+ CLK_GATE_IP1,
+ CLK_GATE_IP2,
+ CLK_GATE_IP3,
+ CLK_GATE_IP4,
+ CLK_GATE_IP5,
+ CLK_GATE_BLOCK,
+ APLL_LOCK,
+ MPLL_LOCK,
+ EPLL_LOCK,
+ VPLL_LOCK,
+ APLL_CON0,
+ APLL_CON1,
+ MPLL_CON,
+ EPLL_CON0,
+ EPLL_CON1,
+ VPLL_CON,
+ CLK_OUT,
+};
+
+static int s5pv210_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, s5pv210_clk_dump,
+ ARRAY_SIZE(s5pv210_clk_regs));
+ return 0;
+}
+
+static void s5pv210_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, s5pv210_clk_dump,
+ ARRAY_SIZE(s5pv210_clk_regs));
+}
+
+static struct syscore_ops s5pv210_clk_syscore_ops = {
+ .suspend = s5pv210_clk_suspend,
+ .resume = s5pv210_clk_resume,
+};
+
+static void s5pv210_clk_sleep_init(void)
+{
+ s5pv210_clk_dump =
+ samsung_clk_alloc_reg_dump(s5pv210_clk_regs,
+ ARRAY_SIZE(s5pv210_clk_regs));
+ if (!s5pv210_clk_dump) {
+ pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+ return;
+ }
+
+ register_syscore_ops(&s5pv210_clk_syscore_ops);
+}
+#else
+static inline void s5pv210_clk_sleep_init(void) { }
+#endif
+
+/* Mux parent lists. */
+static const char *const fin_pll_p[] __initconst = {
+ "xxti",
+ "xusbxti"
+};
+
+static const char *const mout_apll_p[] __initconst = {
+ "fin_pll",
+ "fout_apll"
+};
+
+static const char *const mout_mpll_p[] __initconst = {
+ "fin_pll",
+ "fout_mpll"
+};
+
+static const char *const mout_epll_p[] __initconst = {
+ "fin_pll",
+ "fout_epll"
+};
+
+static const char *const mout_vpllsrc_p[] __initconst = {
+ "fin_pll",
+ "sclk_hdmi27m"
+};
+
+static const char *const mout_vpll_p[] __initconst = {
+ "mout_vpllsrc",
+ "fout_vpll"
+};
+
+static const char *const mout_group1_p[] __initconst = {
+ "dout_a2m",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll"
+};
+
+static const char *const mout_group2_p[] __initconst = {
+ "xxti",
+ "xusbxti",
+ "sclk_hdmi27m",
+ "sclk_usbphy0",
+ "sclk_usbphy1",
+ "sclk_hdmiphy",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+};
+
+static const char *const mout_audio0_p[] __initconst = {
+ "xxti",
+ "pcmcdclk0",
+ "sclk_hdmi27m",
+ "sclk_usbphy0",
+ "sclk_usbphy1",
+ "sclk_hdmiphy",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+};
+
+static const char *const mout_audio1_p[] __initconst = {
+ "i2scdclk1",
+ "pcmcdclk1",
+ "sclk_hdmi27m",
+ "sclk_usbphy0",
+ "sclk_usbphy1",
+ "sclk_hdmiphy",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+};
+
+static const char *const mout_audio2_p[] __initconst = {
+ "i2scdclk2",
+ "pcmcdclk2",
+ "sclk_hdmi27m",
+ "sclk_usbphy0",
+ "sclk_usbphy1",
+ "sclk_hdmiphy",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+};
+
+static const char *const mout_spdif_p[] __initconst = {
+ "dout_audio0",
+ "dout_audio1",
+ "dout_audio3",
+};
+
+static const char *const mout_group3_p[] __initconst = {
+ "mout_apll",
+ "mout_mpll"
+};
+
+static const char *const mout_group4_p[] __initconst = {
+ "mout_mpll",
+ "dout_a2m"
+};
+
+static const char *const mout_flash_p[] __initconst = {
+ "dout_hclkd",
+ "dout_hclkp"
+};
+
+static const char *const mout_dac_p[] __initconst = {
+ "mout_vpll",
+ "sclk_hdmiphy"
+};
+
+static const char *const mout_hdmi_p[] __initconst = {
+ "sclk_hdmiphy",
+ "dout_tblk"
+};
+
+static const char *const mout_mixer_p[] __initconst = {
+ "mout_dac",
+ "mout_hdmi"
+};
+
+static const char *const mout_vpll_6442_p[] __initconst = {
+ "fin_pll",
+ "fout_vpll"
+};
+
+static const char *const mout_mixer_6442_p[] __initconst = {
+ "mout_vpll",
+ "dout_mixer"
+};
+
+static const char *const mout_d0sync_6442_p[] __initconst = {
+ "mout_dsys",
+ "div_apll"
+};
+
+static const char *const mout_d1sync_6442_p[] __initconst = {
+ "mout_psys",
+ "div_apll"
+};
+
+static const char *const mout_group2_6442_p[] __initconst = {
+ "fin_pll",
+ "none",
+ "none",
+ "sclk_usbphy0",
+ "none",
+ "none",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+};
+
+static const char *const mout_audio0_6442_p[] __initconst = {
+ "fin_pll",
+ "pcmcdclk0",
+ "none",
+ "sclk_usbphy0",
+ "none",
+ "none",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+};
+
+static const char *const mout_audio1_6442_p[] __initconst = {
+ "i2scdclk1",
+ "pcmcdclk1",
+ "none",
+ "sclk_usbphy0",
+ "none",
+ "none",
+ "mout_mpll",
+ "mout_epll",
+ "mout_vpll",
+ "fin_pll",
+};
+
+static const char *const mout_clksel_p[] __initconst = {
+ "fout_apll_clkout",
+ "fout_mpll_clkout",
+ "fout_epll",
+ "fout_vpll",
+ "sclk_usbphy0",
+ "sclk_usbphy1",
+ "sclk_hdmiphy",
+ "rtc",
+ "rtc_tick",
+ "dout_hclkm",
+ "dout_pclkm",
+ "dout_hclkd",
+ "dout_pclkd",
+ "dout_hclkp",
+ "dout_pclkp",
+ "dout_apll_clkout",
+ "dout_hpm",
+ "xxti",
+ "xusbxti",
+ "div_dclk"
+};
+
+static const char *const mout_clksel_6442_p[] __initconst = {
+ "fout_apll_clkout",
+ "fout_mpll_clkout",
+ "fout_epll",
+ "fout_vpll",
+ "sclk_usbphy0",
+ "none",
+ "none",
+ "rtc",
+ "rtc_tick",
+ "none",
+ "none",
+ "dout_hclkd",
+ "dout_pclkd",
+ "dout_hclkp",
+ "dout_pclkp",
+ "dout_apll_clkout",
+ "none",
+ "fin_pll",
+ "none",
+ "div_dclk"
+};
+
+static const char *const mout_clkout_p[] __initconst = {
+ "dout_clkout",
+ "none",
+ "xxti",
+ "xusbxti"
+};
+
+/* Common fixed factor clocks. */
+static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
+ FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
+ FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
+ FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
+};
+
+/* PLL input mux (fin_pll), which needs to be registered before PLLs. */
+static const struct samsung_mux_clock early_mux_clks[] __initconst = {
+ MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
+ CLK_MUX_READ_ONLY, 0),
+};
+
+/* Common clock muxes. */
+static const struct samsung_mux_clock mux_clks[] __initconst = {
+ MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
+ MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
+ MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
+ MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
+ MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
+ MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
+ MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
+
+ MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
+};
+
+/* S5PV210-specific clock muxes. */
+static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
+ MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
+
+ MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
+ MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
+ MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
+ MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
+ MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
+ MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
+ MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
+ MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
+
+ MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
+ MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
+ MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
+
+ MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
+ MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
+ MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
+
+ MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
+ MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
+ MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
+ MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
+ MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
+ MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
+ MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
+ MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
+
+ MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
+ MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
+ MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
+
+ MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
+ MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
+ MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
+ MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
+ MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
+ MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
+ MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
+
+ MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
+};
+
+/* S5P6442-specific clock muxes. */
+static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
+ MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
+
+ MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
+ MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
+ MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
+ MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
+
+ MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
+ MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
+
+ MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
+ MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
+ MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
+
+ MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
+ MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
+ MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
+ MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
+ MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
+ MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
+
+ MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
+ MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
+
+ MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
+ MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
+
+ MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
+};
+
+/* S5PV210-specific fixed rate clocks generated inside the SoC. */
+static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
+ FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000),
+ FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
+ FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000),
+ FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000),
+};
+
+/* S5P6442-specific fixed rate clocks generated inside the SoC. */
+static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
+ FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000),
+};
+
+/* Common clock dividers. */
+static const struct samsung_div_clock div_clks[] __initconst = {
+ DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
+ DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
+ DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
+ DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
+
+ DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
+ DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
+ DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
+
+ DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
+ DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
+ DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
+
+ DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
+ DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
+ DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
+ DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
+ DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
+ DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
+
+ DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
+ DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
+
+ DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
+ DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
+ DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
+
+ DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
+};
+
+/* S5PV210-specific clock dividers. */
+static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
+ DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
+ DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
+ DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
+ DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
+
+ DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
+ DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
+
+ DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
+ DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
+ DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
+
+ DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
+ DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
+
+ DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
+
+ DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
+ DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
+ DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
+ DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
+ DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
+
+ DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
+ DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
+};
+
+/* S5P6442-specific clock dividers. */
+static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
+ DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
+ DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
+
+ DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
+};
+
+/* Common clock gates. */
+static const struct samsung_gate_clock gate_clks[] __initconst = {
+ GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
+ GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
+ GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
+ GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
+ GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
+
+ GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
+ GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
+ GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
+ GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
+ GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
+ GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
+ GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
+
+ GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
+ GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
+ GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
+ GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
+ GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
+
+ GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
+ GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
+ GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
+ GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
+ GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
+ GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
+ GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
+ GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
+ GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
+ GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
+ GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
+ GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
+ GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
+ GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
+ GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
+ GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
+
+ GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
+ GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
+
+ GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
+ CLK_SET_RATE_PARENT, 0),
+
+ GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+/* S5PV210-specific clock gates. */
+static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
+ GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
+ GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
+ GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
+ GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
+ GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
+
+ GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
+ GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
+ GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
+ GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
+ GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
+
+ GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
+ GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
+ GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
+ GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
+ GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
+ GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
+ GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
+ GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
+ GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
+
+ GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
+ GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
+ GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
+ GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
+ CLK_GATE_IP3, 11, 0, 0),
+ GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
+ GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
+ GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
+ GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
+
+ GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
+ GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
+ GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
+ GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
+ GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
+ GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
+
+ GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
+
+ GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+/* S5P6442-specific clock gates. */
+static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
+ GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
+ GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
+ GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
+ GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
+ GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
+
+ GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
+ GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
+
+ GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
+
+ GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+/*
+ * Clock aliases for legacy clkdev look-up.
+ * NOTE: Needed only to support legacy board files.
+ */
+static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
+ ALIAS(DOUT_APLL, NULL, "armclk"),
+ ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
+ ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
+};
+
+/* S5PV210-specific PLLs. */
+static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
+ [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, NULL),
+ [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
+ MPLL_LOCK, MPLL_CON, NULL),
+ [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, NULL),
+ [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
+ VPLL_LOCK, VPLL_CON, NULL),
+};
+
+/* S5P6442-specific PLLs. */
+static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
+ [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
+ APLL_LOCK, APLL_CON0, NULL),
+ [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
+ MPLL_LOCK, MPLL_CON, NULL),
+ [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
+ EPLL_LOCK, EPLL_CON0, NULL),
+ [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
+ VPLL_LOCK, VPLL_CON, NULL),
+};
+
+static void __init __s5pv210_clk_init(struct device_node *np,
+ unsigned long xxti_f,
+ unsigned long xusbxti_f,
+ bool is_s5p6442)
+{
+ struct samsung_clk_provider *ctx;
+
+ ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+
+ samsung_clk_register_mux(ctx, early_mux_clks,
+ ARRAY_SIZE(early_mux_clks));
+
+ if (is_s5p6442) {
+ samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
+ ARRAY_SIZE(s5p6442_frate_clks));
+ samsung_clk_register_pll(ctx, s5p6442_pll_clks,
+ ARRAY_SIZE(s5p6442_pll_clks), reg_base);
+ samsung_clk_register_mux(ctx, s5p6442_mux_clks,
+ ARRAY_SIZE(s5p6442_mux_clks));
+ samsung_clk_register_div(ctx, s5p6442_div_clks,
+ ARRAY_SIZE(s5p6442_div_clks));
+ samsung_clk_register_gate(ctx, s5p6442_gate_clks,
+ ARRAY_SIZE(s5p6442_gate_clks));
+ } else {
+ samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
+ ARRAY_SIZE(s5pv210_frate_clks));
+ samsung_clk_register_pll(ctx, s5pv210_pll_clks,
+ ARRAY_SIZE(s5pv210_pll_clks), reg_base);
+ samsung_clk_register_mux(ctx, s5pv210_mux_clks,
+ ARRAY_SIZE(s5pv210_mux_clks));
+ samsung_clk_register_div(ctx, s5pv210_div_clks,
+ ARRAY_SIZE(s5pv210_div_clks));
+ samsung_clk_register_gate(ctx, s5pv210_gate_clks,
+ ARRAY_SIZE(s5pv210_gate_clks));
+ }
+
+ samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
+ samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
+ samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
+
+ samsung_clk_register_fixed_factor(ctx, ffactor_clks,
+ ARRAY_SIZE(ffactor_clks));
+
+ samsung_clk_register_alias(ctx, s5pv210_aliases,
+ ARRAY_SIZE(s5pv210_aliases));
+
+ s5pv210_clk_sleep_init();
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
+ "\tmout_epll = %ld, mout_vpll = %ld\n",
+ is_s5p6442 ? "S5P6442" : "S5PV210",
+ _get_rate("mout_apll"), _get_rate("mout_mpll"),
+ _get_rate("mout_epll"), _get_rate("mout_vpll"));
+}
+
+static void __init s5pv210_clk_dt_init(struct device_node *np)
+{
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ __s5pv210_clk_init(np, 0, 0, false);
+}
+CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
+
+static void __init s5p6442_clk_dt_init(struct device_node *np)
+{
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ __s5pv210_clk_init(np, 0, 0, true);
+}
+CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+*/
+
+#include <linux/slab.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include "clk.h"
+
+static LIST_HEAD(clock_reg_cache_list);
+
+void samsung_clk_save(void __iomem *base,
+ struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs)
+{
+ for (; num_regs > 0; --num_regs, ++rd)
+ rd->value = readl(base + rd->offset);
+}
+
+void samsung_clk_restore(void __iomem *base,
+ const struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs)
+{
+ for (; num_regs > 0; --num_regs, ++rd)
+ writel(rd->value, base + rd->offset);
+}
+
+struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
+ const unsigned long *rdump,
+ unsigned long nr_rdump)
+{
+ struct samsung_clk_reg_dump *rd;
+ unsigned int i;
+
+ rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
+ if (!rd)
+ return NULL;
+
+ for (i = 0; i < nr_rdump; ++i)
+ rd[i].offset = rdump[i];
+
+ return rd;
+}
+
+/* setup the essentials required to support clock lookup using ccf */
+struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks)
+{
+ struct samsung_clk_provider *ctx;
+ struct clk **clk_table;
+ int i;
+
+ ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
+ if (!ctx)
+ panic("could not allocate clock provider context.\n");
+
+ clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_table)
+ panic("could not allocate clock lookup table\n");
+
+ for (i = 0; i < nr_clks; ++i)
+ clk_table[i] = ERR_PTR(-ENOENT);
+
+ ctx->reg_base = base;
+ ctx->clk_data.clks = clk_table;
+ ctx->clk_data.clk_num = nr_clks;
+ spin_lock_init(&ctx->lock);
+
+ return ctx;
+}
+
+void __init samsung_clk_of_add_provider(struct device_node *np,
+ struct samsung_clk_provider *ctx)
+{
+ if (np) {
+ if (of_clk_add_provider(np, of_clk_src_onecell_get,
+ &ctx->clk_data))
+ panic("could not register clk provider\n");
+ }
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
+ unsigned int id)
+{
+ if (ctx->clk_data.clks && id)
+ ctx->clk_data.clks[id] = clk;
+}
+
+/* register a list of aliases */
+void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
+ const struct samsung_clock_alias *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ if (!ctx->clk_data.clks) {
+ pr_err("%s: clock table missing\n", __func__);
+ return;
+ }
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ if (!list->id) {
+ pr_err("%s: clock id missing for index %d\n", __func__,
+ idx);
+ continue;
+ }
+
+ clk = ctx->clk_data.clks[list->id];
+ if (!clk) {
+ pr_err("%s: failed to find clock %d\n", __func__,
+ list->id);
+ continue;
+ }
+
+ ret = clk_register_clkdev(clk, list->alias, list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+/* register a list of fixed clocks */
+void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
+ const struct samsung_fixed_rate_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_rate(NULL, list->name,
+ list->parent_name, list->flags, list->fixed_rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /*
+ * Unconditionally add a clock lookup for the fixed rate clocks.
+ * There are not many of these on any of Samsung platforms.
+ */
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/* register a list of fixed factor clocks */
+void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
+ const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_factor(NULL, list->name,
+ list->parent_name, list->flags, list->mult, list->div);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+ }
+}
+
+/* register a list of mux clocks */
+void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
+ const struct samsung_mux_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_mux(NULL, list->name, list->parent_names,
+ list->num_parents, list->flags,
+ ctx->reg_base + list->offset,
+ list->shift, list->width, list->mux_flags, &ctx->lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias,
+ list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+ }
+}
+
+/* register a list of div clocks */
+void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
+ const struct samsung_div_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ if (list->table)
+ clk = clk_register_divider_table(NULL, list->name,
+ list->parent_name, list->flags,
+ ctx->reg_base + list->offset,
+ list->shift, list->width, list->div_flags,
+ list->table, &ctx->lock);
+ else
+ clk = clk_register_divider(NULL, list->name,
+ list->parent_name, list->flags,
+ ctx->reg_base + list->offset, list->shift,
+ list->width, list->div_flags, &ctx->lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias,
+ list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+ }
+}
+
+/* register a list of gate clocks */
+void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
+ const struct samsung_gate_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_gate(NULL, list->name, list->parent_name,
+ list->flags, ctx->reg_base + list->offset,
+ list->bit_idx, list->gate_flags, &ctx->lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias,
+ list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+ }
+}
+
+/*
+ * obtain the clock speed of all external fixed clock sources from device
+ * tree and register it
+ */
+void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate_clock *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ const struct of_device_id *clk_matches)
+{
+ const struct of_device_id *match;
+ struct device_node *clk_np;
+ u32 freq;
+
+ for_each_matching_node_and_match(clk_np, clk_matches, &match) {
+ if (of_property_read_u32(clk_np, "clock-frequency", &freq))
+ continue;
+ fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
+ }
+ samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
+}
+
+/* utility function to get the rate of a specified clock */
+unsigned long _get_rate(const char *clk_name)
+{
+ struct clk *clk;
+
+ clk = __clk_lookup(clk_name);
+ if (!clk) {
+ pr_err("%s: could not find clock %s\n", __func__, clk_name);
+ return 0;
+ }
+
+ return clk_get_rate(clk);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int samsung_clk_suspend(void)
+{
+ struct samsung_clock_reg_cache *reg_cache;
+
+ list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+ samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
+ reg_cache->rd_num);
+ return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+ struct samsung_clock_reg_cache *reg_cache;
+
+ list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+ samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
+ reg_cache->rd_num);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+ .suspend = samsung_clk_suspend,
+ .resume = samsung_clk_resume,
+};
+
+void samsung_clk_sleep_init(void __iomem *reg_base,
+ const unsigned long *rdump,
+ unsigned long nr_rdump)
+{
+ struct samsung_clock_reg_cache *reg_cache;
+
+ reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
+ GFP_KERNEL);
+ if (!reg_cache)
+ panic("could not allocate register reg_cache.\n");
+ reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
+
+ if (!reg_cache->rdump)
+ panic("could not allocate register dump storage.\n");
+
+ if (list_empty(&clock_reg_cache_list))
+ register_syscore_ops(&samsung_clk_syscore_ops);
+
+ reg_cache->reg_base = reg_base;
+ reg_cache->rd_num = nr_rdump;
+ list_add_tail(®_cache->node, &clock_reg_cache_list);
+}
+
+#else
+void samsung_clk_sleep_init(void __iomem *reg_base,
+ const unsigned long *rdump,
+ unsigned long nr_rdump) {}
+#endif
+
+/*
+ * Common function which registers plls, muxes, dividers and gates
+ * for each CMU. It also add CMU register list to register cache.
+ */
+struct samsung_clk_provider * __init samsung_cmu_register_one(
+ struct device_node *np,
+ const struct samsung_cmu_info *cmu)
+{
+ void __iomem *reg_base;
+ struct samsung_clk_provider *ctx;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ panic("%s: failed to map registers\n", __func__);
+ return NULL;
+ }
+
+ ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
+ if (!ctx) {
+ panic("%s: unable to allocate ctx\n", __func__);
+ return ctx;
+ }
+
+ if (cmu->pll_clks)
+ samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
+ reg_base);
+ if (cmu->mux_clks)
+ samsung_clk_register_mux(ctx, cmu->mux_clks,
+ cmu->nr_mux_clks);
+ if (cmu->div_clks)
+ samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
+ if (cmu->gate_clks)
+ samsung_clk_register_gate(ctx, cmu->gate_clks,
+ cmu->nr_gate_clks);
+ if (cmu->fixed_clks)
+ samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
+ cmu->nr_fixed_clks);
+ if (cmu->fixed_factor_clks)
+ samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
+ cmu->nr_fixed_factor_clks);
+ if (cmu->clk_regs)
+ samsung_clk_sleep_init(reg_base, cmu->clk_regs,
+ cmu->nr_clk_regs);
+
+ samsung_clk_of_add_provider(np, ctx);
+
+ return ctx;
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_H
+#define __SAMSUNG_CLK_H
+
+#include <linux/clk-provider.h>
+#include "clk-pll.h"
+
+struct clk;
+
+/**
+ * struct samsung_clk_provider: information about clock provider
+ * @reg_base: virtual address for the register base.
+ * @clk_data: holds clock related data like clk* and number of clocks.
+ * @lock: maintains exclusion between callbacks for a given clock-provider.
+ */
+struct samsung_clk_provider {
+ void __iomem *reg_base;
+ struct clk_onecell_data clk_data;
+ spinlock_t lock;
+};
+
+/**
+ * struct samsung_clock_alias: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_clock_alias {
+ unsigned int id;
+ const char *dev_name;
+ const char *alias;
+};
+
+#define ALIAS(_id, dname, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .alias = a, \
+ }
+
+#define MHZ (1000 * 1000)
+
+/**
+ * struct samsung_fixed_rate_clock: information about fixed-rate clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-rate clock.
+ * @parent_name: optional parent clock name.
+ * @flags: optional fixed-rate clock flags.
+ * @fixed-rate: fixed clock rate of this clock.
+ */
+struct samsung_fixed_rate_clock {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long fixed_rate;
+};
+
+#define FRATE(_id, cname, pname, f, frate) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .fixed_rate = frate, \
+ }
+
+/*
+ * struct samsung_fixed_factor_clock: information about fixed-factor clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-factor clock.
+ * @parent_name: parent clock name.
+ * @mult: fixed multiplication factor.
+ * @div: fixed division factor.
+ * @flags: optional fixed-factor clock flags.
+ */
+struct samsung_fixed_factor_clock {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long mult;
+ unsigned long div;
+ unsigned long flags;
+};
+
+#define FFACTOR(_id, cname, pname, m, d, f) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .mult = m, \
+ .div = d, \
+ .flags = f, \
+ }
+
+/**
+ * struct samsung_mux_clock: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this mux clock.
+ * @parent_names: array of pointer to parent clock names.
+ * @num_parents: number of parents listed in @parent_names.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the mux.
+ * @shift: starting bit location of the mux control bit-field in @reg.
+ * @width: width of the mux control bit-field in @reg.
+ * @mux_flags: flags for mux-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_mux_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char *const *parent_names;
+ u8 num_parents;
+ unsigned long flags;
+ unsigned long offset;
+ u8 shift;
+ u8 width;
+ u8 mux_flags;
+ const char *alias;
+};
+
+#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = (f) | CLK_SET_RATE_NO_REPARENT, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+ .mux_flags = mf, \
+ .alias = a, \
+ }
+
+#define MUX(_id, cname, pnames, o, s, w) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
+
+#define MUX_A(_id, cname, pnames, o, s, w, a) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
+
+#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
+
+#define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
+
+/**
+ * @id: platform specific id of the clock.
+ * struct samsung_div_clock: information about div clock
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this div clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the div.
+ * @shift: starting bit location of the div control bit-field in @reg.
+ * @div_flags: flags for div-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_div_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long offset;
+ u8 shift;
+ u8 width;
+ u8 div_flags;
+ const char *alias;
+ struct clk_div_table *table;
+};
+
+#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+ .div_flags = df, \
+ .alias = a, \
+ .table = t, \
+ }
+
+#define DIV(_id, cname, pname, o, s, w) \
+ __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
+
+#define DIV_A(_id, cname, pname, o, s, w, a) \
+ __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
+
+#define DIV_F(_id, cname, pname, o, s, w, f, df) \
+ __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
+
+#define DIV_T(_id, cname, pname, o, s, w, t) \
+ __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
+
+/**
+ * struct samsung_gate_clock: information about gate clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this gate clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the gate.
+ * @bit_idx: bit index of the gate control bit-field in @reg.
+ * @gate_flags: flags for gate-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_gate_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long offset;
+ u8 bit_idx;
+ u8 gate_flags;
+ const char *alias;
+};
+
+#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .offset = o, \
+ .bit_idx = b, \
+ .gate_flags = gf, \
+ .alias = a, \
+ }
+
+#define GATE(_id, cname, pname, o, b, f, gf) \
+ __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
+ __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
+
+#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
+ __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
+ __GATE(_id, dname, cname, pname, o, b, f, gf, a)
+
+#define PNAME(x) static const char * const x[] __initconst
+
+/**
+ * struct samsung_clk_reg_dump: register dump of clock controller registers.
+ * @offset: clock register offset from the controller base address.
+ * @value: the value to be register at offset.
+ */
+struct samsung_clk_reg_dump {
+ u32 offset;
+ u32 value;
+};
+
+/**
+ * struct samsung_pll_clock: information about pll clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this pll clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @con_offset: offset of the register for configuring the PLL.
+ * @lock_offset: offset of the register for locking the PLL.
+ * @type: Type of PLL to be registered.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_pll_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ int con_offset;
+ int lock_offset;
+ enum samsung_pll_type type;
+ const struct samsung_pll_rate_table *rate_table;
+ const char *alias;
+};
+
+#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \
+ _rtable, _alias) \
+ { \
+ .id = _id, \
+ .type = _typ, \
+ .dev_name = _dname, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .flags = CLK_GET_RATE_NOCACHE, \
+ .con_offset = _con, \
+ .lock_offset = _lock, \
+ .rate_table = _rtable, \
+ .alias = _alias, \
+ }
+
+#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
+ __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
+ _lock, _con, _rtable, _name)
+
+#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
+ __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
+ _lock, _con, _rtable, _alias)
+
+struct samsung_clock_reg_cache {
+ struct list_head node;
+ void __iomem *reg_base;
+ struct samsung_clk_reg_dump *rdump;
+ unsigned int rd_num;
+};
+
+struct samsung_cmu_info {
+ /* list of pll clocks and respective count */
+ const struct samsung_pll_clock *pll_clks;
+ unsigned int nr_pll_clks;
+ /* list of mux clocks and respective count */
+ const struct samsung_mux_clock *mux_clks;
+ unsigned int nr_mux_clks;
+ /* list of div clocks and respective count */
+ const struct samsung_div_clock *div_clks;
+ unsigned int nr_div_clks;
+ /* list of gate clocks and respective count */
+ const struct samsung_gate_clock *gate_clks;
+ unsigned int nr_gate_clks;
+ /* list of fixed clocks and respective count */
+ const struct samsung_fixed_rate_clock *fixed_clks;
+ unsigned int nr_fixed_clks;
+ /* list of fixed factor clocks and respective count */
+ const struct samsung_fixed_factor_clock *fixed_factor_clks;
+ unsigned int nr_fixed_factor_clks;
+ /* total number of clocks with IDs assigned*/
+ unsigned int nr_clk_ids;
+
+ /* list and number of clocks registers */
+ const unsigned long *clk_regs;
+ unsigned int nr_clk_regs;
+};
+
+extern struct samsung_clk_provider *__init samsung_clk_init(
+ struct device_node *np, void __iomem *base,
+ unsigned long nr_clks);
+extern void __init samsung_clk_of_add_provider(struct device_node *np,
+ struct samsung_clk_provider *ctx);
+extern void __init samsung_clk_of_register_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate_clock *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ const struct of_device_id *clk_matches);
+
+extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
+ struct clk *clk, unsigned int id);
+
+extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
+ const struct samsung_clock_alias *list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_rate(
+ struct samsung_clk_provider *ctx,
+ const struct samsung_fixed_rate_clock *clk_list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_factor(
+ struct samsung_clk_provider *ctx,
+ const struct samsung_fixed_factor_clock *list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
+ const struct samsung_mux_clock *clk_list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
+ const struct samsung_div_clock *clk_list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
+ const struct samsung_gate_clock *clk_list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+ const struct samsung_pll_clock *pll_list,
+ unsigned int nr_clk, void __iomem *base);
+
+extern struct samsung_clk_provider __init *samsung_cmu_register_one(
+ struct device_node *,
+ const struct samsung_cmu_info *);
+
+extern unsigned long _get_rate(const char *clk_name);
+
+extern void samsung_clk_sleep_init(void __iomem *reg_base,
+ const unsigned long *rdump,
+ unsigned long nr_rdump);
+
+extern void samsung_clk_save(void __iomem *base,
+ struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs);
+extern void samsung_clk_restore(void __iomem *base,
+ const struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs);
+extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
+ const unsigned long *rdump,
+ unsigned long nr_rdump);
+
+#endif /* __SAMSUNG_CLK_H */
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions for composite clocks.
+ */
+
+#include <linux/syscore_ops.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <soc/samsung/cal-if.h>
+
+#include "composite.h"
+
+#define PLL_STAT_OSC (0x0)
+#define PLL_STAT_PLL (0x1)
+#define PLL_STAT_CHANGE (0x4)
+#define PLL_STAT_MASK (0x7)
+
+#define to_comp_pll(_hw) container_of(_hw, struct samsung_composite_pll, hw)
+#define to_comp_mux(_hw) container_of(_hw, struct samsung_composite_mux, hw)
+#define to_comp_divider(_hw) container_of(_hw, struct samsung_composite_divider, hw)
+#define to_usermux(_hw) container_of(_hw, struct clk_samsung_usermux, hw)
+#define to_vclk(_hw) container_of(_hw, struct samsung_vclk, hw)
+
+static DEFINE_SPINLOCK(lock);
+
+#ifdef CONFIG_PM_SLEEP
+void samsung_clk_save(void __iomem *base,
+ struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs)
+{
+ for (; num_regs > 0; --num_regs, ++rd)
+ rd->value = readl(base + rd->offset);
+}
+
+void samsung_clk_restore(void __iomem *base,
+ const struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs)
+{
+ for (; num_regs > 0; --num_regs, ++rd)
+ writel(rd->value, base + rd->offset);
+}
+
+struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
+ const unsigned long *rdump,
+ unsigned long nr_rdump)
+{
+ struct samsung_clk_reg_dump *rd;
+ unsigned int i;
+
+ rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
+ if (!rd)
+ return NULL;
+
+ for (i = 0; i < nr_rdump; ++i)
+ rd[i].offset = rdump[i];
+
+ return rd;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+/* setup the essentials required to support clock lookup using ccf */
+struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks)
+{
+ struct samsung_clk_provider *ctx = NULL;
+ struct clk **clk_table;
+ int i;
+
+ if (!np)
+ return ctx;
+
+ ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
+ if (!ctx)
+ panic("could not allocate clock provider context.\n");
+
+ clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_table)
+ panic("could not allocate clock lookup table\n");
+
+ for (i = 0; i < nr_clks; ++i)
+ clk_table[i] = ERR_PTR(-ENOENT);
+
+ ctx->reg_base = base;
+ ctx->clk_data.clks = clk_table;
+ ctx->clk_data.clk_num = nr_clks;
+ spin_lock_init(&ctx->lock);
+
+ return ctx;
+}
+
+void __init samsung_clk_of_add_provider(struct device_node *np,
+ struct samsung_clk_provider *ctx)
+{
+ if (np) {
+ if (of_clk_add_provider(np, of_clk_src_onecell_get,
+ &ctx->clk_data))
+ panic("could not register clk provider\n");
+ }
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+static void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
+ unsigned int id)
+{
+ if (ctx->clk_data.clks && id)
+ ctx->clk_data.clks[id] = clk;
+}
+
+/* register a list of fixed clocks */
+void __init samsung_register_fixed_rate(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_rate(NULL, list->name,
+ list->parent_name, list->flags, list->fixed_rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /*
+ * Unconditionally add a clock lookup for the fixed rate clocks.
+ * There are not many of these on any of Samsung platforms.
+ */
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/* register a list of fixed factor clocks */
+void __init samsung_register_fixed_factor(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_factor *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_factor(NULL, list->name,
+ list->parent_name, list->flags, list->mult, list->div);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/*
+ * obtain the clock speed of all external fixed clock sources from device
+ * tree and register it
+ */
+void __init samsung_register_of_fixed_ext(struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ struct of_device_id *clk_matches)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ u32 freq;
+
+ for_each_matching_node_and_match(np, clk_matches, &match) {
+ if (of_property_read_u32(np, "clock-frequency", &freq))
+ continue;
+ fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
+ }
+ samsung_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
+}
+
+/* operation functions for pll clocks */
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_composite_pll *pll, unsigned long rate)
+{
+ const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ for (i = 0; i < pll->rate_count; i++) {
+ if (rate == rate_table[i].rate)
+ return &rate_table[i];
+ }
+
+ return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ const struct samsung_pll_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ /* Assumming rate_table is in descending order */
+ for (i = 0; i < pll->rate_count; i++) {
+ if (drate >= rate_table[i].rate)
+ return rate_table[i].rate;
+ }
+
+ /* return minimum supported value */
+ return rate_table[i - 1].rate;
+}
+
+static int samsung_composite_pll_is_enabled(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ reg = readl(pll->enable_reg);
+
+ return (((reg >> pll->enable_bit) & 1) == set) ? 1 : 0;
+}
+
+static int samsung_composite_pll_enable(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* Setting Enable register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg |= (1 << pll->enable_bit);
+ else
+ reg &= ~(1 << pll->enable_bit);
+ writel(reg, pll->enable_reg);
+
+ /* setting CTRL mux register to 1 */
+ reg = readl(pll->sel_reg);
+ reg |= (1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) != PLL_STAT_PLL);
+
+ return 0;
+}
+
+static void samsung_composite_pll_disable(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* setting CTRL mux register to 0 */
+ reg = readl(pll->sel_reg);
+ reg &= ~(1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) != PLL_STAT_OSC);
+
+ /* Setting Register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg &= ~(1 << pll->enable_bit);
+ else
+ reg |= (1 << pll->enable_bit);
+
+ writel(reg, pll->enable_reg);
+}
+
+static unsigned long samsung_pll145xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl(pll->con_reg);
+ mdiv = (pll_con >> PLL145XX_MDIV_SHIFT) & PLL145XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL145XX_PDIV_SHIFT) & PLL145XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL145XX_SDIV_SHIFT) & PLL145XX_SDIV_MASK;
+ /* Do calculation */
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll145xx_mp_check(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ return ((mdiv != ((pll_con >> PLL145XX_MDIV_SHIFT) & PLL145XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con >> PLL145XX_PDIV_SHIFT) & PLL145XX_PDIV_MASK)));
+}
+
+static int samsung_pll145xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 pll_con;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con = readl(pll->con_reg);
+ if (!(samsung_pll145xx_mp_check(rate->mdiv, rate->pdiv, pll_con))) {
+ if ((rate->sdiv) == ((pll_con >> PLL145XX_SDIV_SHIFT) & PLL145XX_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con &= ~(PLL145XX_SDIV_MASK << PLL145XX_SDIV_SHIFT);
+ pll_con |= rate->sdiv << PLL145XX_SDIV_SHIFT;
+ writel(pll_con, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL145XX_LOCK_FACTOR, pll->lock_reg);
+ /* Change PLL PMS values */
+ pll_con &= ~((PLL145XX_MDIV_MASK << PLL145XX_MDIV_SHIFT) |
+ (PLL145XX_PDIV_MASK << PLL145XX_PDIV_SHIFT) |
+ (PLL145XX_SDIV_MASK << PLL145XX_SDIV_SHIFT));
+ pll_con |= (rate->mdiv << PLL145XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL145XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL145XX_SDIV_SHIFT);
+ /* To prevent instable PLL operation, preset ENABLE bit with 0 */
+ pll_con &= ~BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con |= BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ do {
+ cpu_relax();
+ pll_con = readl(pll->con_reg);
+ } while (!(pll_con & (PLL145XX_LOCKED_MASK << PLL145XX_LOCKED_SHIFT)));
+
+ return 0;
+}
+
+
+static unsigned long samsung_pll1460x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL1460X_MDIV_SHIFT) & PLL1460X_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL1460X_PDIV_SHIFT) & PLL1460X_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL1460X_SDIV_SHIFT) & PLL1460X_SDIV_MASK;
+ kdiv = (s16)((pll_con1 >> PLL1460X_KDIV_SHIFT) & PLL1460X_KDIV_MASK);
+ /* Do calculation */
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll1460x_mpk_check(u32 mdiv, u32 pdiv, u32 kdiv, u32 pll_con0, u32 pll_con1)
+{
+ return ((mdiv != ((pll_con0 >> PLL1460X_MDIV_SHIFT) & PLL1460X_MDIV_MASK)) ||
+ (pdiv != ((pll_con0 >> PLL1460X_PDIV_SHIFT) & PLL1460X_PDIV_MASK)) ||
+ (kdiv != ((pll_con1 >> PLL1460X_KDIV_SHIFT) & PLL1460X_KDIV_MASK)));
+}
+
+static int samsung_pll1460x_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ if (!(samsung_pll1460x_mpk_check(rate->mdiv, rate->pdiv, rate->kdiv, pll_con0, pll_con1))) {
+ if ((rate->sdiv) == ((pll_con0 >> PLL1460X_SDIV_SHIFT) & PLL1460X_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con0 &= ~(PLL1460X_SDIV_MASK << PLL1460X_SDIV_SHIFT);
+ pll_con0 |= (rate->sdiv << PLL1460X_SDIV_SHIFT);
+ writel(pll_con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL1460X_LOCK_FACTOR, pll->lock_reg);
+
+ pll_con1 &= ~(PLL1460X_KDIV_MASK << PLL1460X_KDIV_SHIFT);
+ pll_con1 |= (rate->kdiv << PLL1460X_KDIV_SHIFT);
+ writel(pll_con1, pll->con_reg + 4);
+
+ pll_con0 &= ~((PLL1460X_MDIV_MASK << PLL1460X_MDIV_SHIFT) |
+ (PLL1460X_PDIV_MASK << PLL1460X_PDIV_SHIFT) |
+ (PLL1460X_SDIV_MASK << PLL1460X_SDIV_SHIFT));
+ pll_con0 |= (rate->mdiv << PLL1460X_MDIV_SHIFT) |
+ (rate->pdiv << PLL1460X_PDIV_SHIFT) |
+ (rate->sdiv << PLL1460X_SDIV_SHIFT);
+ /* To prevent instable PLL operation, preset ENABLE bit with 0 */
+ pll_con0 &= ~BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con0 |= BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /* Wait lock time */
+ do {
+ cpu_relax();
+ pll_con0 = readl(pll->con_reg);
+ } while (!(pll_con0 & (PLL1460X_LOCKED_MASK << PLL1460X_LOCKED_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll145xx_clk_ops = {
+ .recalc_rate = samsung_pll145xx_recalc_rate,
+ .set_rate = samsung_pll145xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable,
+ .disable = samsung_composite_pll_disable,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+static const struct clk_ops samsung_pll1460x_clk_ops = {
+ .recalc_rate = samsung_pll1460x_recalc_rate,
+ .set_rate = samsung_pll1460x_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable,
+ .disable = samsung_composite_pll_disable,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+static int samsung_composite_pll_enable_onchange(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* Setting Enable register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg |= (1 << pll->enable_bit);
+ else
+ reg &= ~(1 << pll->enable_bit);
+ writel(reg, pll->enable_reg);
+
+ /* setting CTRL mux register to 1 */
+ reg = readl(pll->sel_reg);
+ reg |= (1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) == PLL_STAT_CHANGE);
+
+ return 0;
+}
+
+static void samsung_composite_pll_disable_onchange(struct clk_hw *hw)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ int set = pll->pll_flag & PLL_BYPASS ? 0 : 1;
+ unsigned int reg;
+
+ /* setting CTRL mux register to 0 */
+ reg = readl(pll->sel_reg);
+ reg &= ~(1 << pll->sel_bit);
+ writel(reg, pll->sel_reg);
+
+ /* check status for mux setting */
+ do {
+ cpu_relax();
+ reg = readl(pll->stat_reg);
+ } while (((reg >> pll->stat_bit) & PLL_STAT_MASK) == PLL_STAT_CHANGE);
+
+ /* Setting Register */
+ reg = readl(pll->enable_reg);
+ if (set)
+ reg &= ~(1 << pll->enable_bit);
+ else
+ reg |= (1 << pll->enable_bit);
+
+ writel(reg, pll->enable_reg);
+}
+
+static unsigned long samsung_pll255xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = readl(pll->con_reg);
+ mdiv = (pll_con >> PLL255XX_MDIV_SHIFT) & PLL255XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL255XX_PDIV_SHIFT) & PLL255XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL255XX_SDIV_SHIFT) & PLL255XX_SDIV_MASK;
+ /* Do calculation */
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll255xx_mp_check(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ return ((mdiv != ((pll_con >> PLL255XX_MDIV_SHIFT) & PLL255XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con >> PLL255XX_PDIV_SHIFT) & PLL255XX_PDIV_MASK)));
+}
+
+static int samsung_pll255xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 pll_con;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con = readl(pll->con_reg);
+ if (!(samsung_pll255xx_mp_check(rate->mdiv, rate->pdiv, pll_con))) {
+ if ((rate->sdiv) == ((pll_con >> PLL255XX_SDIV_SHIFT) & PLL255XX_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con &= ~(PLL255XX_SDIV_MASK << PLL255XX_SDIV_SHIFT);
+ pll_con |= rate->sdiv << PLL255XX_SDIV_SHIFT;
+ writel(pll_con, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL255XX_LOCK_FACTOR, pll->lock_reg);
+ /* Change PLL PMS values */
+ pll_con &= ~((PLL255XX_MDIV_MASK << PLL255XX_MDIV_SHIFT) |
+ (PLL255XX_PDIV_MASK << PLL255XX_PDIV_SHIFT) |
+ (PLL255XX_SDIV_MASK << PLL255XX_SDIV_SHIFT));
+ pll_con |= (rate->mdiv << PLL255XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL255XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL255XX_SDIV_SHIFT);
+
+ /* To prevent unstable PLL operation, preset enable bit with 0 */
+ pll_con &= ~BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con |= BIT(31);
+ writel(pll_con, pll->con_reg);
+
+ do {
+ cpu_relax();
+ pll_con = readl(pll->con_reg);
+ } while (!(pll_con & (PLL255XX_LOCKED_MASK << PLL255XX_LOCKED_SHIFT)));
+
+ return 0;
+}
+
+/* register function for pll clocks */
+static const struct clk_ops samsung_pll255xx_clk_ops = {
+ .recalc_rate = samsung_pll255xx_recalc_rate,
+ .set_rate = samsung_pll255xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable_onchange,
+ .disable = samsung_composite_pll_disable_onchange,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL2650X_MDIV_SHIFT) & PLL2650X_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650X_PDIV_SHIFT) & PLL2650X_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650X_SDIV_SHIFT) & PLL2650X_SDIV_MASK;
+ kdiv = (s16)((pll_con1 >> PLL2650X_KDIV_SHIFT) & PLL2650X_KDIV_MASK);
+ /* Do calculation */
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2650x_mpk_check(u32 mdiv, u32 pdiv, u32 kdiv, u32 pll_con0, u32 pll_con1)
+{
+ return ((mdiv != ((pll_con0 >> PLL2650X_MDIV_SHIFT) & PLL2650X_MDIV_MASK)) ||
+ (pdiv != ((pll_con0 >> PLL2650X_PDIV_SHIFT) & PLL2650X_PDIV_MASK)) ||
+ (kdiv != ((pll_con1 >> PLL2650X_KDIV_SHIFT) & PLL2650X_KDIV_MASK)));
+}
+
+static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_pll *pll = to_comp_pll(hw);
+ u32 pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = readl(pll->con_reg);
+ pll_con1 = readl(pll->con_reg + 4);
+ if (!(samsung_pll2650x_mpk_check(rate->mdiv, rate->pdiv, rate->kdiv, pll_con0, pll_con1))) {
+ if ((rate->sdiv) == ((pll_con0 >> PLL2650X_SDIV_SHIFT) & PLL2650X_SDIV_MASK))
+ return 0;
+ /* In the case of changing S value only */
+ pll_con0 &= ~(PLL2650X_SDIV_MASK << PLL2650X_SDIV_SHIFT);
+ pll_con0 |= (rate->sdiv << PLL2650X_SDIV_SHIFT);
+ writel(pll_con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time */
+ writel(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
+
+ pll_con1 &= ~(PLL2650X_KDIV_MASK << PLL2650X_KDIV_SHIFT);
+ pll_con1 |= (rate->kdiv << PLL2650X_KDIV_SHIFT);
+ writel(pll_con1, pll->con_reg + 4);
+
+ pll_con0 &= ~((PLL2650X_MDIV_MASK << PLL2650X_MDIV_SHIFT) |
+ (PLL2650X_PDIV_MASK << PLL2650X_PDIV_SHIFT) |
+ (PLL2650X_SDIV_MASK << PLL2650X_SDIV_SHIFT));
+ pll_con0 |= (rate->mdiv << PLL2650X_MDIV_SHIFT) |
+ (rate->pdiv << PLL2650X_PDIV_SHIFT) |
+ (rate->sdiv << PLL2650X_SDIV_SHIFT);
+
+ /* To prevent unstable PLL operation, preset enable bit with 0 */
+ pll_con0 &= ~BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /* Set enable bit */
+ pll_con0 |= BIT(31);
+ writel(pll_con0, pll->con_reg);
+
+ /*
+ * Wait lock time
+ * unit address translation : us to ms for mdelay
+ */
+ mdelay(rate->pdiv * PLL2650X_LOCK_FACTOR / 1000);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650x_clk_ops = {
+ .recalc_rate = samsung_pll2650x_recalc_rate,
+ .set_rate = samsung_pll2650x_set_rate,
+ .round_rate = samsung_pll_round_rate,
+ .enable = samsung_composite_pll_enable_onchange,
+ .disable = samsung_composite_pll_disable_onchange,
+ .is_enabled = samsung_composite_pll_is_enabled,
+};
+
+/* register function for pll clocks */
+static void _samsung_register_comp_pll(struct samsung_clk_provider *ctx,
+ struct samsung_composite_pll *list)
+{
+ struct clk *clk;
+ static const char *pname[1] = {"fin_pll"};
+ int len;
+ unsigned int ret = 0;
+
+ if (list->rate_table) {
+ /* find count of rates in rate_table */
+ for (len = 0; list->rate_table[len].rate != 0; )
+ len++;
+ list->rate_count = len; }
+ else
+ list->rate_count = 0;
+
+ if (list->type == pll_1450x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll145xx_clk_ops,
+ &list->hw, &samsung_pll145xx_clk_ops, list->flag);
+ else if (list->type == pll_1451x || list->type == pll_1452x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll145xx_clk_ops,
+ &list->hw, &samsung_pll145xx_clk_ops, list->flag);
+ else if (list->type == pll_1460x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll1460x_clk_ops,
+ &list->hw, &samsung_pll1460x_clk_ops, list->flag);
+ else if (list->type == pll_2551x || list->type == pll_2555x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll255xx_clk_ops,
+ &list->hw, &samsung_pll255xx_clk_ops, list->flag);
+ else if (list->type == pll_2650x)
+ clk = clk_register_composite(NULL, list->name, pname, 1,
+ NULL, NULL,
+ &list->hw, &samsung_pll2650x_clk_ops,
+ &list->hw, &samsung_pll2650x_clk_ops, list->flag);
+ else {
+ pr_err("%s: invalid pll type %d\n", __func__, list->type);
+ return;
+ }
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n",
+ __func__, list->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+void samsung_register_comp_pll(struct samsung_clk_provider *ctx,
+ struct samsung_composite_pll *list, unsigned int nr_pll)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_pll; cnt++)
+ _samsung_register_comp_pll(ctx, &list[cnt]);
+}
+
+/* operation functions for mux clocks */
+static u8 samsung_mux_get_parent(struct clk_hw *hw)
+{
+ struct samsung_composite_mux *mux = to_comp_mux(hw);
+ u32 val;
+
+ val = readl(mux->sel_reg) >> mux->sel_bit;
+ val &= (BIT(mux->sel_width) - 1);
+
+ return (u8)val;
+}
+
+static int samsung_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct samsung_composite_mux *mux = to_comp_mux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+
+ val = readl(mux->sel_reg);
+ val &= ~((BIT(mux->sel_width) - 1) << mux->sel_bit);
+ val |= index << mux->sel_bit;
+ writel(val, mux->sel_reg);
+
+ if (mux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to set parent %s.\n",
+ __func__, clk_hw_get_name(hw));
+ pr_err("MUX_REG: %08x, MUX_STAT_REG: %08x\n",
+ readl(mux->sel_reg), readl(mux->stat_reg));
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(mux->stat_reg);
+ val &= ((BIT(mux->stat_width) - 1) << mux->stat_bit);
+ } while (val != (index << mux->stat_bit));
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_composite_mux_ops = {
+ .get_parent = samsung_mux_get_parent,
+ .set_parent = samsung_mux_set_parent,
+};
+
+/* operation functions for mux clocks checking status with "on changing" */
+
+static int samsung_mux_set_parent_onchange(struct clk_hw *hw, u8 index)
+{
+ struct samsung_composite_mux *mux = to_comp_mux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+
+ val = readl(mux->sel_reg);
+ val &= ~((BIT(mux->sel_width) - 1) << mux->sel_bit);
+ val |= index << mux->sel_bit;
+ writel(val, mux->sel_reg);
+
+ if (mux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to set parent %s.\n",
+ __func__, clk_hw_get_name(hw));
+ pr_err("MUX_REG: %08x, MUX_STAT_REG: %08x\n",
+ readl(mux->sel_reg), readl(mux->stat_reg));
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(mux->stat_reg);
+ val &= ((BIT(mux->stat_width) - 1) << mux->stat_bit);
+ } while (val == PLL_STAT_CHANGE);
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+
+ return 0;
+}
+static const struct clk_ops samsung_composite_mux_ops_onchange = {
+ .get_parent = samsung_mux_get_parent,
+ .set_parent = samsung_mux_set_parent_onchange,
+};
+
+/* register function for mux clock */
+static void _samsung_register_comp_mux(struct samsung_clk_provider *ctx,
+ struct samsung_composite_mux *list)
+{
+ struct clk *clk;
+ unsigned int ret = 0;
+
+ list->lock = &lock;
+
+ if (!(list->flag & CLK_ON_CHANGING))
+ clk = clk_register_composite(NULL, list->name, list->parents, list->num_parents,
+ &list->hw, &samsung_composite_mux_ops,
+ NULL, NULL,
+ NULL, NULL, list->flag);
+ else
+ clk = clk_register_composite(NULL, list->name, list->parents, list->num_parents,
+ &list->hw, &samsung_composite_mux_ops_onchange,
+ NULL, NULL,
+ NULL, NULL, list->flag);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register mux clock %s\n",
+ __func__, list->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+void samsung_register_comp_mux(struct samsung_clk_provider *ctx,
+ struct samsung_composite_mux *list, unsigned int nr_mux)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_mux; cnt++)
+ _samsung_register_comp_mux(ctx, &list[cnt]);
+}
+
+/* operation functions for divider clocks */
+static unsigned long samsung_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_divider *divider = to_comp_divider(hw);
+ unsigned int val;
+
+ val = readl(divider->rate_reg) >> divider->rate_bit;
+ val &= (1 << divider->rate_width) - 1;
+ val += 1;
+ if (!val)
+ return parent_rate;
+
+ return parent_rate / val;
+}
+
+static int samsung_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate)
+{
+ struct samsung_composite_divider *divider = to_comp_divider(hw);
+ int i, bestdiv = 0;
+ unsigned long parent_rate, maxdiv, now, best = 0;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ maxdiv = ((unsigned long)(1UL << (divider->rate_width)) - 1UL) + 1UL;
+
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestdiv = (parent_rate + rate - 1) / rate;
+ bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+ return bestdiv;
+ }
+
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (i = 1; i <= maxdiv; i++) {
+ if (rate * i == parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = clk_round_rate(clk_get_parent(hw->clk),
+ ((rate * i) + i - 1));
+ now = parent_rate / i;
+ if (now <= rate && now > best) {
+ bestdiv = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestdiv) {
+ bestdiv = ((1 << (divider->rate_width)) - 1) + 1;
+ *best_parent_rate = clk_round_rate(clk_get_parent(hw->clk), 1);
+ }
+
+ return bestdiv;
+}
+
+static long samsung_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ int div = 1;
+
+ div = samsung_divider_bestdiv(hw, rate, prate);
+ if (div == 0) {
+ pr_err("%s: divider value should not be %d\n", __func__, div);
+ div = 1;
+ }
+
+ return *prate / div;
+}
+
+static int samsung_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct samsung_composite_divider *divider = to_comp_divider(hw);
+ unsigned int div;
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ div = (parent_rate / rate) - 1;
+
+ if (div > ((1 << divider->rate_width) - 1))
+ div = (1 << divider->rate_width) - 1;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+
+ val = readl(divider->rate_reg);
+ val &= ~(((1 << divider->rate_width) - 1) << divider->rate_bit);
+ val |= div << divider->rate_bit;
+ writel(val, divider->rate_reg);
+
+ if (divider->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: faild to set rate %s.\n",
+ __func__, clk_hw_get_name(hw));
+ pr_err("DIV_REG: %08x, MUX_STAT_REG: %08x\n",
+ readl(divider->rate_reg), readl(divider->stat_reg));
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(divider->stat_reg);
+ val &= BIT(divider->stat_width - 1) << divider->stat_bit;
+ } while (val);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_composite_divider_ops = {
+ .recalc_rate = samsung_divider_recalc_rate,
+ .round_rate = samsung_divider_round_rate,
+ .set_rate = samsung_divider_set_rate,
+};
+
+/* register function for divider clocks */
+static void _samsung_register_comp_divider(struct samsung_clk_provider *ctx,
+ struct samsung_composite_divider *list)
+{
+ struct clk *clk;
+ unsigned int ret = 0;
+
+ list->lock = &lock;
+
+ clk = clk_register_composite(NULL, list->name, &list->parent_name, 1,
+ NULL, NULL,
+ &list->hw, &samsung_composite_divider_ops,
+ NULL, NULL, list->flag);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register mux clock %s\n",
+ __func__, list->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
+void samsung_register_comp_divider(struct samsung_clk_provider *ctx,
+ struct samsung_composite_divider *list, unsigned int nr_div)
+{
+ int cnt;
+
+ for (cnt = 0; cnt < nr_div; cnt++)
+ _samsung_register_comp_divider(ctx, &list[cnt]);
+}
+
+struct dummy_gate_clk {
+ unsigned long offset;
+ u8 bit_idx;
+ struct clk *clk;
+};
+
+static struct dummy_gate_clk **gate_clk_list;
+static unsigned int gate_clk_nr;
+
+int samsung_add_clk_gate_list(struct clk *clk, unsigned long offset, u8 bit_idx, const char *name)
+{
+ struct dummy_gate_clk *tmp_clk;
+
+ if (!clk || !offset)
+ return -EINVAL;
+
+ tmp_clk = kzalloc(sizeof(struct dummy_gate_clk), GFP_KERNEL);
+ if (!tmp_clk) {
+ pr_err("%s: fail to alloc for gate_clk\n", __func__);
+ return -ENOMEM;
+ }
+
+ tmp_clk->offset = offset;
+ tmp_clk->bit_idx = bit_idx;
+ tmp_clk->clk = clk;
+
+ gate_clk_list[gate_clk_nr] = tmp_clk;
+
+ gate_clk_nr++;
+
+ return 0;
+}
+
+struct clk *samsung_clk_get_by_reg(unsigned long offset, u8 bit_idx)
+{
+ unsigned int i;
+
+ for (i = 0; i < gate_clk_nr; i++) {
+ if (gate_clk_list[i]->offset == offset) {
+ if (gate_clk_list[i]->bit_idx == bit_idx)
+ return gate_clk_list[i]->clk;
+ }
+ }
+
+ pr_err("%s: Fail to get clk by register offset\n", __func__);
+
+ return 0;
+}
+
+/* existing register function for gate clocks */
+static struct clk * __init _samsung_register_gate(
+ struct samsung_clk_provider *ctx, struct samsung_gate *list)
+{
+ struct clk *clk;
+ unsigned int ret = 0;
+
+ clk = clk_register_gate(NULL, list->name, list->parent_name,
+ list->flag, list->reg, list->bit,
+ list->flag, &lock);
+
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ return 0;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, list->id);
+
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+
+ return clk;
+}
+
+void __init samsung_register_gate(struct samsung_clk_provider *ctx,
+ struct samsung_gate *list, unsigned int nr_gate)
+{
+ int cnt;
+ struct clk *clk;
+ bool gate_list_fail = false;
+ unsigned int gate_enable_nr = 0;
+ struct clk **gate_enable_list;
+
+ gate_clk_list = kzalloc(sizeof(struct dummy_gate_clk *) * nr_gate, GFP_KERNEL);
+ if (!gate_clk_list) {
+ pr_err("%s: can not alloc for gate clock list\n", __func__);
+ gate_list_fail = true;
+ }
+
+ gate_enable_list = kzalloc(sizeof(struct clk *) * nr_gate, GFP_KERNEL);
+
+ if (!gate_enable_list) {
+ pr_err("%s: can not alloc for enable gate clock list\n", __func__);
+ return ;
+ }
+
+ for (cnt = 0; cnt < nr_gate; cnt++) {
+ clk = _samsung_register_gate(ctx, &list[cnt]);
+
+ if (((&list[cnt])->flag & CLK_GATE_ENABLE) && gate_enable_list) {
+ gate_enable_list[gate_enable_nr] = clk;
+ gate_enable_nr++;
+ }
+
+ /* Make list for gate clk to used by samsung_clk_get_by_reg */
+ if (!gate_list_fail)
+ samsung_add_clk_gate_list(clk, (unsigned long)(list[cnt].reg), list[cnt].bit, list[cnt].name);
+ }
+
+ /*
+ * Enable for not controlling gate clocks
+ */
+ for (cnt = 0; cnt < gate_enable_nr; cnt++)
+ clk_prepare_enable(gate_enable_list[cnt]);
+
+ if (gate_enable_list)
+ kfree(gate_enable_list);
+}
+
+/* operation functions for usermux clocks */
+static int samsung_usermux_is_enabled(struct clk_hw *hw)
+{
+ struct clk_samsung_usermux *usermux = to_usermux(hw);
+ u32 val;
+
+ val = readl(usermux->sel_reg);
+ val &= BIT(usermux->sel_bit);
+
+ return val ? 1 : 0;
+}
+
+static int samsung_usermux_enable(struct clk_hw *hw)
+{
+ struct clk_samsung_usermux *usermux = to_usermux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (usermux->lock)
+ spin_lock_irqsave(usermux->lock, flags);
+
+ val = readl(usermux->sel_reg);
+ val &= ~(1 << usermux->sel_bit);
+ val |= (1 << usermux->sel_bit);
+ writel(val, usermux->sel_reg);
+
+ if (usermux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to enable clock %s.\n",
+ __func__, clk_hw_get_name(hw));
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+ return -ETIMEDOUT;
+ }
+ val = readl(usermux->stat_reg);
+ val &= BIT(2) << usermux->stat_bit;
+ } while (val);
+
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+
+ return 0;
+}
+
+static void samsung_usermux_disable(struct clk_hw *hw)
+{
+ struct clk_samsung_usermux *usermux = to_usermux(hw);
+ u32 val;
+ unsigned long flags = 0;
+ unsigned int timeout = 1000;
+
+ if (usermux->lock)
+ spin_lock_irqsave(usermux->lock, flags);
+
+ val = readl(usermux->sel_reg);
+ val &= ~(1 << usermux->sel_bit);
+ writel(val, usermux->sel_reg);
+
+ if (usermux->stat_reg)
+ do {
+ --timeout;
+ if (!timeout) {
+ pr_err("%s: failed to disable clock %s.\n",
+ __func__, clk_hw_get_name(hw));
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+ return;
+ }
+ val = readl(usermux->stat_reg);
+ val &= BIT(2) << usermux->stat_bit;
+ } while (val);
+
+ if (usermux->lock)
+ spin_unlock_irqrestore(usermux->lock, flags);
+}
+
+static const struct clk_ops samsung_usermux_ops = {
+ .enable = samsung_usermux_enable,
+ .disable = samsung_usermux_disable,
+ .is_enabled = samsung_usermux_is_enabled,
+};
+
+/* register function for usermux clocks */
+static struct clk * __init _samsung_register_comp_usermux(struct samsung_usermux *list)
+{
+ struct clk_samsung_usermux *usermux;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ usermux = kzalloc(sizeof(struct clk_samsung_usermux), GFP_KERNEL);
+ if (!usermux) {
+ pr_err("%s: could not allocate usermux clk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = list->name;
+ init.ops = &samsung_usermux_ops;
+ init.flags = list->flag | CLK_IS_BASIC;
+ init.parent_names = (list->parent_name ? &list->parent_name : NULL);
+ init.num_parents = (list->parent_name ? 1 : 0);
+
+ usermux->sel_reg = list->sel_reg;
+ usermux->sel_bit = list->sel_bit;
+ usermux->stat_reg = list->stat_reg;
+ usermux->stat_bit = list->stat_bit;
+ usermux->flag = 0;
+ usermux->lock = &lock;
+ usermux->hw.init = &init;
+
+ clk = clk_register(NULL, &usermux->hw);
+
+ if (IS_ERR(clk))
+ kfree(usermux);
+
+ return clk;
+}
+
+void __init samsung_register_usermux(struct samsung_clk_provider *ctx,
+ struct samsung_usermux *list, unsigned int nr_usermux)
+{
+ struct clk *clk;
+ int cnt;
+ unsigned int ret = 0;
+
+ for (cnt = 0; cnt < nr_usermux; cnt++) {
+ clk = _samsung_register_comp_usermux(&list[cnt]);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ (&list[cnt])->name);
+ return;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, (&list[cnt])->id);
+
+ if ((&list[cnt])->alias) {
+ ret = clk_register_clkdev(clk, (&list[cnt])->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, (&list[cnt])->alias);
+ }
+ }
+}
+
+/**
+ * Operations for virtual clock used in cal
+ * When cal is used to set clocks, following operations will be executed.
+ */
+int cal_vclk_enable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if ((vclk->flags & VCLK_GATE) && !(vclk->flags & VCLK_QCH_DIS))
+ return 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_IN);
+ /* Call cal api to enable virtual clock */
+ ret = cal_clk_enable(vclk->id);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %d.\n", __func__, vclk->id, ret);
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return 0;
+}
+
+void cal_vclk_disable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if ((vclk->flags & VCLK_GATE) && !(vclk->flags & VCLK_QCH_DIS))
+ return ;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+ /* Call cal api to disable virtual clock */
+ ret = cal_clk_disable(vclk->id);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %d.\n", __func__, vclk->id, ret);
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return;
+ }
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+}
+
+int cal_vclk_is_enabled(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ int ret = 0;
+
+ /*
+ * Call cal api to check whether clock is enabled or not
+ * Spinlock is not needed because only read operation will
+ * be executed
+ */
+ ret = cal_clk_is_enabled(vclk->id);
+
+ return ret;
+}
+
+unsigned long cal_vclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long ret = 0;
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+ /* Call cal api to recalculate rate */
+ ret = cal_clk_getrate(vclk->id);
+ exynos_ss_clk(hw, __func__, ret, ESS_FLAG_OUT);
+
+ return ret;
+}
+
+unsigned long cal_vclk_gate_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk;
+ struct clk_hw *parent;
+ unsigned long ret = 0;
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+ parent = clk_hw_get_parent(hw);
+ if (parent) {
+ vclk = to_vclk(parent);
+ /* call cal api to recalculate rate */
+ ret = cal_clk_getrate(vclk->id);
+ }
+ exynos_ss_clk(hw, __func__, ret, ESS_FLAG_OUT);
+
+ return ret;
+}
+
+long cal_vclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ /* round_rate ops is not needed when using cal */
+ return (long)rate;
+}
+
+int cal_vclk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_IN);
+ /* Call cal api to set rate of clock */
+ ret = cal_clk_setrate(vclk->id, rate);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %lu %d.\n", __func__,
+ vclk->id, rate, ret);
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return ret;
+}
+
+unsigned long cal_vclk_dfs_sw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long ret = 0;
+
+ /* Call cal api to recalculate rate */
+ ret = cal_dfs_cached_get_rate(vclk->id);
+
+ return ret;
+}
+unsigned long cal_vclk_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long ret = 0;
+
+ /* Call cal api to recalculate rate */
+ ret = cal_dfs_get_rate(vclk->id);
+
+ return ret;
+}
+
+int cal_vclk_dfs_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_IN);
+ /* Call cal api to set rate of clock */
+ ret = cal_dfs_set_rate(vclk->id, rate);
+ if (ret) {
+ pr_err("[CAL]%s failed %d %lu %d.\n", __func__,
+ vclk->id, rate, ret);
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_ON);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+ exynos_ss_clk(hw, __func__, rate, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return ret;
+}
+
+int cal_vclk_dfs_set_rate_switch(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ int ret = 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ /* Call cal api to set rate of clock */
+ ret = cal_dfs_set_rate_switch(vclk->id, rate);
+ if (ret) {
+ pr_err("[CAL]%s failed.\n", __func__);
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+ return -EAGAIN;
+ }
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return ret;
+}
+
+static int cal_vclk_qch_init(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ int ret = 0;
+
+ if (vclk->flags & VCLK_QCH_EN)
+ ret = cal_qch_init(vclk->id, 1);
+ else if (vclk->flags & VCLK_QCH_DIS)
+ ret = cal_qch_init(vclk->id, 0);
+
+ return ret;
+}
+
+int cal_vclk_qactive_enable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ unsigned int reg;
+
+ if (!(vclk->flags & VCLK_QACTIVE))
+ return 0;
+
+ if (!vclk->addr)
+ return 0;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_IN);
+
+ reg = readl(vclk->addr);
+ reg &= ~(vclk->mask);
+ reg |= vclk->val;
+ writel(reg, vclk->addr);
+
+ exynos_ss_clk(hw, __func__, 1, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+
+ return 0;
+}
+
+void cal_vclk_qactive_disable(struct clk_hw *hw)
+{
+ struct samsung_vclk *vclk = to_vclk(hw);
+ unsigned long flags = 0;
+ unsigned int reg;
+
+ if (!(vclk->flags & VCLK_QACTIVE))
+ return ;
+
+ if (!vclk->addr)
+ return ;;
+
+ if (vclk->lock)
+ spin_lock_irqsave(vclk->lock, flags);
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_IN);
+
+ reg = readl(vclk->addr);
+ reg &= ~(vclk->mask);
+ writel(reg, vclk->addr);
+
+ exynos_ss_clk(hw, __func__, 0, ESS_FLAG_OUT);
+
+ if (vclk->lock)
+ spin_unlock_irqrestore(vclk->lock, flags);
+}
+
+static const struct clk_ops samsung_vclk_ops = {
+ .enable = cal_vclk_enable,
+ .disable = cal_vclk_disable,
+ .is_enabled = cal_vclk_is_enabled,
+ .recalc_rate = cal_vclk_recalc_rate,
+ .round_rate = cal_vclk_round_rate,
+ .set_rate = cal_vclk_set_rate,
+};
+
+static const struct clk_ops samsung_vclk_dfs_ops = {
+ .recalc_rate = cal_vclk_dfs_recalc_rate,
+ .round_rate = cal_vclk_round_rate,
+ .set_rate = cal_vclk_dfs_set_rate,
+};
+
+static const struct clk_ops samsung_vclk_dfs_sw_ops = {
+ .recalc_rate = cal_vclk_dfs_sw_recalc_rate,
+ .round_rate = cal_vclk_round_rate,
+ .set_rate = cal_vclk_dfs_set_rate_switch,
+};
+
+static const struct clk_ops samsung_vclk_gate_ops = {
+ .enable = cal_vclk_enable,
+ .disable = cal_vclk_disable,
+ .is_enabled = cal_vclk_is_enabled,
+ .recalc_rate = cal_vclk_gate_recalc_rate,
+};
+
+static const struct clk_ops samsung_vclk_qactive_ops = {
+ .enable = cal_vclk_qactive_enable,
+ .disable = cal_vclk_qactive_disable,
+};
+
+static struct clk * __init _samsung_register_vclk(struct init_vclk *list)
+{
+ struct samsung_vclk *vclk;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ vclk = kzalloc(sizeof(struct samsung_vclk), GFP_KERNEL);
+ if (!vclk) {
+ pr_err("%s: could not allocate struct vclk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = list->name;
+ if (list->vclk_flags & VCLK_DFS)
+ init.ops = &samsung_vclk_dfs_ops;
+ else if (list->vclk_flags & VCLK_DFS_SWITCH)
+ init.ops = &samsung_vclk_dfs_sw_ops;
+ else if (list->vclk_flags & VCLK_GATE)
+ init.ops = &samsung_vclk_gate_ops;
+ else if (list->vclk_flags & VCLK_QACTIVE) {
+ init.ops = &samsung_vclk_qactive_ops;
+ vclk->addr = ioremap(list->addr, 4);
+ vclk->mask = list->mask;
+ vclk->val = list->val;
+ } else
+ init.ops = &samsung_vclk_ops;
+ init.flags = list->flags | (CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
+ init.parent_names = (list->parent ? &list->parent : NULL);
+ init.num_parents = (list->parent ? 1 : 0);
+ vclk->id = list->calid;
+ /* Flags for vclk are not defined yet */
+ vclk->flags = list->vclk_flags;
+ vclk->lock = &lock;
+ vclk->hw.init = &init;
+ clk = clk_register(NULL, &vclk->hw);
+
+ if (IS_ERR(clk))
+ kfree(vclk);
+
+ return clk;
+}
+
+void __init samsung_register_vclk(struct samsung_clk_provider *ctx,
+ struct init_vclk *list, unsigned int nr_vclk)
+{
+ struct clk *clk;
+ int cnt;
+ unsigned int ret = 0;
+
+ for (cnt = 0; cnt < nr_vclk; cnt++) {
+ clk = _samsung_register_vclk(&list[cnt]);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register virtual clock %s\n",
+ __func__, (&list[cnt])->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(ctx, clk, (&list[cnt])->id);
+
+ /* Additional array of clocks for finding struct clk */
+ if ((&list[cnt])->alias) {
+ ret = clk_register_clkdev(clk, (&list[cnt])->alias, NULL);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, (&list[cnt])->alias);
+ }
+
+ cal_vclk_qch_init(__clk_get_hw(clk));
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions for composite clocks.
+ */
+
+#ifndef __SAMSUNG_CLK_COMPOSITE_H
+#define __SAMSUNG_CLK_COMPOSITE_H
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+
+/*
+ * struct samsung_clk_provider: information about clock provider
+ * @reg_base: virtual address for the register base.
+ * @clk_data: holds clock related data like clk* and number of clocks.
+ * @lock: maintains exclusion bwtween callbacks for a given clock-provider.
+ */
+struct samsung_clk_provider {
+ void __iomem *reg_base;
+ struct clk_onecell_data clk_data;
+ spinlock_t lock;
+};
+
+/*
+ * struct samsung_clk_reg_dump: register dump of clock controller registers.
+ * @offset: clock register offset from the controller base address.
+ * @value: the value to be register at offset.
+ */
+struct samsung_clk_reg_dump {
+ unsigned long offset;
+ u32 value;
+};
+
+/*
+ * struct samsung_fixed_rate_clock: information about fixed-rate clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-rate clock.
+ * @parent_name: optional parent clock name.
+ * @flags: optional fixed-rate clock flags.
+ * @fixed-rate: fixed clock rate of this clock.
+ */
+struct samsung_fixed_rate {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long fixed_rate;
+};
+
+#define FRATE(_id, cname, pname, f, frate) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .fixed_rate = frate, \
+ }
+
+extern void __init samsung_register_fixed_rate(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *list,
+ unsigned int nr_clk);
+/*
+ * struct samsung_fixed_factor_clock: information about fixed-factor clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-factor clock.
+ * @parent_name: parent clock name.
+ * @mult: fixed multiplication factor.
+ * @div: fixed division factor.
+ * @flags: optional fixed-factor clock flags.
+ */
+struct samsung_fixed_factor {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long mult;
+ unsigned long div;
+ unsigned long flags;
+};
+
+#define FFACTOR(_id, cname, pname, m, d, f) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .mult = m, \
+ .div = d, \
+ .flags = f, \
+ }
+
+extern void __init samsung_register_fixed_factor(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_factor *list,
+ unsigned int nr_clk);
+
+/*
+ * PLL145xx Clock Type: PLL1450x, PLL1451x, PLL1452x
+ * Maximum lock time can be 150 * Pdiv cycles
+ */
+#define PLL145XX_LOCK_FACTOR (150)
+#define PLL145XX_MDIV_MASK (0x3FF)
+#define PLL145XX_PDIV_MASK (0x03F)
+#define PLL145XX_SDIV_MASK (0x007)
+#define PLL145XX_LOCKED_MASK (0x1)
+#define PLL145XX_MDIV_SHIFT (16)
+#define PLL145XX_PDIV_SHIFT (8)
+#define PLL145XX_SDIV_SHIFT (0)
+#define PLL145XX_LOCKED_SHIFT (29)
+
+/*
+ * PLL1460X Clock Type
+ * Maximum lock time can be 3000 * Pdiv cycles
+ */
+#define PLL1460X_LOCK_FACTOR (3000)
+#define PLL1460X_MDIV_MASK (0x03FF)
+#define PLL1460X_PDIV_MASK (0x003F)
+#define PLL1460X_SDIV_MASK (0x0007)
+#define PLL1460X_KDIV_MASK (0xFFFF)
+#define PLL1460X_LOCKED_MASK (0x1)
+#define PLL1460X_MDIV_SHIFT (16)
+#define PLL1460X_PDIV_SHIFT (8)
+#define PLL1460X_SDIV_SHIFT (0)
+#define PLL1460X_KDIV_SHIFT (0)
+#define PLL1460X_LOCKED_SHIFT (29)
+
+/*
+ * PLL255xx Clock Type : PLL2551x, PLL2555x
+ * Maximum lock time can be 200 * Pdiv cycles
+ */
+#define PLL255XX_LOCK_FACTOR (200)
+#define PLL255XX_MDIV_MASK (0x3FF)
+#define PLL255XX_PDIV_MASK (0x3F)
+#define PLL255XX_SDIV_MASK (0x7)
+#define PLL255XX_LOCKED_MASK (0x1)
+#define PLL255XX_MDIV_SHIFT (12)
+#define PLL255XX_PDIV_SHIFT (4)
+#define PLL255XX_SDIV_SHIFT (0)
+#define PLL255XX_LOCKED_SHIFT (29)
+
+/*
+ * PLL2650X Clock Type
+ * Maximum lock time can be 3000 * Pdiv cycles
+ */
+#define PLL2650X_LOCK_FACTOR (3000)
+#define PLL2650X_MDIV_MASK (0x01FF)
+#define PLL2650X_PDIV_MASK (0x003F)
+#define PLL2650X_SDIV_MASK (0x0007)
+#define PLL2650X_KDIV_MASK (0xFFFF)
+#define PLL2650X_LOCKED_MASK (0x1)
+#define PLL2650X_MDIV_SHIFT (12)
+#define PLL2650X_PDIV_SHIFT (4)
+#define PLL2650X_SDIV_SHIFT (0)
+#define PLL2650X_KDIV_SHIFT (0)
+#define PLL2650X_LOCKED_SHIFT (29)
+
+enum pll_type {
+ pll_1450x = 0,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
+ pll_2551x,
+ pll_2555x,
+ pll_2650x,
+};
+
+struct samsung_pll_rate_table {
+ long rate;
+ unsigned int pdiv;
+ unsigned int mdiv;
+ unsigned int sdiv;
+ unsigned int kdiv;
+};
+
+#define PLL_BYPASS BIT(0)
+#define CHK_ON_CHANGING BIT(7)
+/*
+ * struct samsung_composite_pll: information about composite-pll clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this pll clock.
+ * @type: type of this pll clock.
+ * @lock_reg: register for locking pll.
+ * @con_reg: configuration register for pll.
+ * @enable_reg: it can be different whether pll can be gated or only bypassed.
+ * @enable_bit: bit index for en/disable pll.
+ * @sel_reg: composite-pll has ctrl-mux. when disabled, it is set by 0.
+ * @sel_bit: bit index for ctrl-mux.
+ * @stat_reg: when sel_reg is set, status register must be checked.
+ * @stat_bit: bit index for status register.
+ * @rate_table: available pll output ratio table.
+ * @alias: support alias for this clock.
+ */
+struct samsung_composite_pll {
+ struct clk_hw hw;
+ unsigned int id;
+ const char *name;
+ enum pll_type type;
+ void __iomem *lock_reg;
+ void __iomem *con_reg;
+ void __iomem *enable_reg;
+ unsigned int enable_bit;
+ void __iomem *sel_reg;
+ unsigned int sel_bit;
+ void __iomem *stat_reg;
+ unsigned int stat_bit;
+ const struct samsung_pll_rate_table *rate_table;
+ unsigned int rate_count;
+ unsigned int pll_flag;
+ u8 flag;
+ const char *alias;
+};
+
+#define PLL(_id, cname, _type, lock, con, en, enbit, sel, selbit, stat, statbit, rtable, pf, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .type = _type, \
+ .lock_reg = lock, \
+ .con_reg = con, \
+ .enable_reg = en, \
+ .enable_bit = enbit, \
+ .sel_reg = sel, \
+ .sel_bit = selbit, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .rate_table = rtable, \
+ .rate_count = 0, \
+ .pll_flag = pf, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void samsung_register_comp_pll(
+ struct samsung_clk_provider *ctx,
+ struct samsung_composite_pll *pll_list,
+ unsigned int nr_pll);
+
+#define PNAME(x) static const char *x[]
+/*
+ * struct samsung_composite_mux: information about composite-mux clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this mux clock.
+ * @parents: array of parent clocks.
+ * @num_parents: number of parent clocks.
+ * @sel_reg: register for mux selection.
+ * @sel_bit: bit index for sel_reg.
+ * @sel_width: different by number of parent clocks.
+ * @stat_reg: status must be checked when changing parent.
+ * @stat_bit: bit index for status register.
+ * @stat_width: different by number of parent clocks.
+ * @flag: optional flag for clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct samsung_composite_mux {
+ struct clk_hw hw;
+ unsigned int id;
+ const char *name;
+ const char **parents;
+ unsigned int num_parents;
+ void __iomem *sel_reg;
+ unsigned int sel_bit;
+ unsigned int sel_width;
+ void __iomem *stat_reg;
+ unsigned int stat_bit;
+ unsigned int stat_width;
+ unsigned int flag;
+ const char *alias;
+ spinlock_t *lock;
+};
+
+#define MUX(_id, cname, pnames, sel, selbit, selwid, stat, statbit, statwid, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parents = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .sel_reg = sel, \
+ .sel_bit = selbit, \
+ .sel_width = selwid, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .stat_width = statwid, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void samsung_register_comp_mux(
+ struct samsung_clk_provider *ctx,
+ struct samsung_composite_mux *mux_list,
+ unsigned int nr_mux);
+
+/*
+ * struct samsung_composite_divider: information about composite-divider clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this divider clock.
+ * @parent_name: name of parent clock.
+ * @rate_reg: register for ratio selection.
+ * @rate_bit: bit index for rate_reg.
+ * @rate_width: can be different by bit index.
+ * @stat_reg: status must be checked when changing ratio.
+ * @stat_bit: bit index for status register.
+ * @stat_width: can be different by bit index.
+ * @flag: flag for clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct samsung_composite_divider {
+ struct clk_hw hw;
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ void __iomem *rate_reg;
+ unsigned int rate_bit;
+ unsigned int rate_width;
+ void __iomem *stat_reg;
+ unsigned int stat_bit;
+ unsigned int stat_width;
+ unsigned int flag;
+ const char *alias;
+ spinlock_t *lock;
+};
+
+#define DIV(_id, cname, pname, rate, ratebit, ratewid, stat, statbit, statwid, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .rate_reg = rate, \
+ .rate_bit = ratebit, \
+ .rate_width = ratewid, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .stat_width = statwid, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void samsung_register_comp_divider(struct samsung_clk_provider *ctx,
+ struct samsung_composite_divider *div_list, unsigned int nr_div);
+
+#define CLK_GATE_ENABLE BIT(20)
+#define CLK_ON_CHANGING BIT(7)
+/*
+ * struct samsung_gate: information about gate clocks
+ * @id: id of the clock for binding with device tree.
+ * @name:
+ * @parent_name:
+ * @reg:
+ * @bit:
+ * @flag:
+ * @alias:
+ */
+struct samsung_gate {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ void __iomem *reg;
+ u8 bit;
+ unsigned int flag;
+ const char *alias;
+};
+
+#define GATE(_id, cname, pname, r, b, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .reg = r, \
+ .bit = b, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void __init samsung_register_gate(
+ struct samsung_clk_provider *ctx,
+ struct samsung_gate *gate_list,
+ unsigned int nr_gate);
+
+struct clk_samsung_usermux {
+ struct clk_hw hw;
+ void __iomem *sel_reg;
+ u8 sel_bit;
+ void __iomem *stat_reg;
+ u8 stat_bit;
+ u8 flag;
+ spinlock_t *lock;
+};
+
+/*
+ * struct samsung_composite_usermux: information about usermux clocks
+ * @id: id of the clock for binding with device tree.
+ * @name: name of this usermux clock.
+ * @parent_name: name of parent clock.
+ * @sel_reg: register for usermux selection.
+ * @sel_bit: bit index for sel_reg.
+ * @stat_reg: status must be checked when changing parent.
+ * @stat_bit: bit index for status register.
+ * @flag: optional flag for clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct samsung_usermux {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ void __iomem *sel_reg;
+ u8 sel_bit;
+ void __iomem *stat_reg;
+ u8 stat_bit;
+ u8 flag;
+ const char *alias;
+};
+
+#define USERMUX(_id, cname, pname, sel, selbit, stat, statbit, f, a) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .sel_reg = sel, \
+ .sel_bit = selbit, \
+ .stat_reg = stat, \
+ .stat_bit = statbit, \
+ .flag = f, \
+ .alias = a, \
+ }
+
+extern void __init samsung_register_usermux(
+ struct samsung_clk_provider *ctx,
+ struct samsung_usermux *list,
+ unsigned int nr_usermux);
+
+#define VCLK_DFS BIT(1)
+#define VCLK_DFS_SWITCH BIT(2)
+#define VCLK_GATE BIT(3)
+#define VCLK_QCH_EN BIT(4)
+#define VCLK_QCH_DIS BIT(5)
+#define VCLK_QACTIVE BIT(6)
+
+/*
+ * struct init_vclk: initial information for virtual clocks
+ * @id: id of the clock for binding with device tree.
+ * @calid: id of the clock for calling cal.
+ * @name: name of this virtual clock.
+ * @flags: optional flag for clock.
+ * @vclk_flags: optional flag for only virtual clock.
+ * @alias: optional name. recommend no more than 15 characters.
+ */
+struct init_vclk{
+ unsigned int id;
+ unsigned int calid;
+ const char *name;
+ const char *parent;
+ u8 flags;
+ u8 vclk_flags;
+ const char *alias;
+ u32 addr;
+ u32 mask;
+ u32 val;
+};
+
+struct samsung_vclk {
+ struct clk_hw hw;
+ unsigned int id;
+ u8 flags;
+ spinlock_t *lock;
+ void __iomem *addr;
+ u32 mask;
+ u32 val;
+};
+
+#define VCLK(_id, _calid, _name, f, vf, a) \
+ { \
+ .id = _id, \
+ .calid = _calid, \
+ .name = _name, \
+ .flags = f, \
+ .vclk_flags = vf, \
+ .alias = a, \
+ }
+
+#define HWACG_VCLK(_id, _calid, _name, _parent, f, vf, a) \
+ { \
+ .id = _id, \
+ .calid = _calid, \
+ .name = _name, \
+ .parent = _parent, \
+ .flags = f, \
+ .vclk_flags = vf, \
+ .alias = a, \
+ }
+
+#define HWACG_VCLK_QACTIVE(_id, _name, _parent, f, vf, a, _addr, _mask, _val) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent = _parent, \
+ .flags = f, \
+ .vclk_flags = vf, \
+ .alias = a, \
+ .addr = _addr, \
+ .mask = _mask, \
+ .val = _val, \
+ }
+
+extern void __init samsung_register_vclk(struct samsung_clk_provider *ctx,
+ struct init_vclk *list, unsigned int nr_vclk);
+
+extern struct samsung_clk_provider *__init samsung_clk_init(
+ struct device_node *np, void __iomem *base,
+ unsigned long nr_clks);
+
+extern void __init samsung_clk_of_add_provider(struct device_node *np,
+ struct samsung_clk_provider *ctx);
+
+extern void __init samsung_register_of_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ struct of_device_id *clk_matches);
+
+extern void samsung_clk_save(void __iomem *base,
+ struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs);
+extern void samsung_clk_restore(void __iomem *base,
+ const struct samsung_clk_reg_dump *rd,
+ unsigned int num_regs);
+extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
+ const unsigned long *rdump,
+ unsigned long nr_rdump);
+
+#endif /* __SAMSUNG_CLK_COMPOSITE_H */
#define DOUT_CLK_AUD_UAIF1 (CLK_DISPAUD_BASE + 19)
#define DOUT_CLK_AUD_UAIF2 (CLK_DISPAUD_BASE + 20)
#define PLL_OUT_AUD (CLK_DISPAUD_BASE + 21)
+#define DOUT_CLK_AUD_FM (CLK_DISPAUD_BASE + 22)
/* NUMBER FOR FSYS DRIVER STARTS FROM 300 */
#define CLK_FSYS_BASE (300)
#define SPI2 (CLK_PERI_BASE + 27)
#define USI_I2C (CLK_PERI_BASE + 28)
#define USI_USI (CLK_PERI_BASE + 29)
+#define UMUX_CLKCMU_PERI_BUS (CLK_PERI_BASE + 30)
/* NUMBER FOR SHUB DRIVER STARTS FROM 600 */
#define CLK_SHUB_BASE (600)
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff