drm/i915: add timeout to FBC disable waits

FBC disable on 965 can take long enough to trigger latency checks in the
kernel so be sure to timeout after a reasonable period.

Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15015.

Tested-by: James Ettle <theholyettlz@googlemail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b867f3c78408259a47db246e7a209315561037c9..36afe94099640fe56abce08b6cb38c7bfa457fab 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1029,19 +1029,28 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 void i8xx_disable_fbc(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+       unsigned long timeout = jiffies + msecs_to_jiffies(1);
        u32 fbc_ctl;
 
        if (!I915_HAS_FBC(dev))
                return;
 
+       if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
+               return; /* Already off, just return */
+
        /* Disable compression */
        fbc_ctl = I915_READ(FBC_CONTROL);
        fbc_ctl &= ~FBC_CTL_EN;
        I915_WRITE(FBC_CONTROL, fbc_ctl);
 
        /* Wait for compressing bit to clear */
-       while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
-               ; /* nothing */
+       while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
+               if (time_after(jiffies, timeout)) {
+                       DRM_DEBUG_DRIVER("FBC idle timed out\n");
+                       break;
+               }
+               ; /* do nothing */
+       }
 
        intel_wait_for_vblank(dev);