ARM: dts: fix omap3 dss clock handle names
authorTomi Valkeinen <tomi.valkeinen@ti.com>
Wed, 12 Feb 2014 13:45:57 +0000 (15:45 +0200)
committerTomi Valkeinen <tomi.valkeinen@ti.com>
Wed, 19 Mar 2014 07:31:47 +0000 (09:31 +0200)
The DSS fclk and iclk handles are named differently on OMAP3430 ES1 than
on later OMAP revisions. The ES1 has handles 'dss1_alwon_fck_3430es1'
and 'dss_ick_3430es1', whereas later revisions have similar names but
ending with 'es2'.

This means we don't have one clock handle to which we could refer to
when defining the DSS clocks.

However, as the namespaces are separate for ES1 and ES2+ OMAPs, we can
just rename the handles to 'dss1_alwon_fck' and 'dss_ick' for both ES1
and ES2+, removing the issue.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Christoph Fritz <chf.fritz@googlemail.com>
Tested-by: Marek Belisko <marek@goldelico.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/omap3430es1-clocks.dtsi
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi

index 6f31954636a1ea0454690316feac8c6abfb9b4ba..4c22f3a7f813a727058ebd4c283d62f1cfc04e0c 100644 (file)
                clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
        };
 
-       dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
+       dss1_alwon_fck: dss1_alwon_fck_3430es1 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll4_m4x2_ck>;
                ti,set-rate-parent;
        };
 
-       dss_ick_3430es1: dss_ick_3430es1 {
+       dss_ick: dss_ick_3430es1 {
                #clock-cells = <0>;
                compatible = "ti,omap3-no-wait-interface-clock";
                clocks = <&l4_ick>;
        dss_clkdm: dss_clkdm {
                compatible = "ti,clockdomain";
                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
-                        <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
+                        <&dss1_alwon_fck>, <&dss_ick>;
        };
 
        d2d_clkdm: d2d_clkdm {
index af9ae5346bf2e9f2cda58bcb2aa3604ebaba3e58..080fb3f4e429bdd4e1463527bbfba42e47478593 100644 (file)
                ti,bit-shift = <30>;
        };
 
-       dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
+       dss1_alwon_fck: dss1_alwon_fck_3430es2 {
                #clock-cells = <0>;
                compatible = "ti,dss-gate-clock";
                clocks = <&dpll4_m4x2_ck>;
                ti,set-rate-parent;
        };
 
-       dss_ick_3430es2: dss_ick_3430es2 {
+       dss_ick: dss_ick_3430es2 {
                #clock-cells = <0>;
                compatible = "ti,omap3-dss-interface-clock";
                clocks = <&l4_ick>;
        dss_clkdm: dss_clkdm {
                compatible = "ti,clockdomain";
                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
-                        <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+                        <&dss1_alwon_fck>, <&dss_ick>;
        };
 
        core_l4_clkdm: core_l4_clkdm {