*/
static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
{
- u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
+ u32 gsintmsk = readl(hsotg->regs + GINTMSK);
u32 new_gsintmsk;
new_gsintmsk = gsintmsk | ints;
if (new_gsintmsk != gsintmsk) {
dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
- writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
+ writel(new_gsintmsk, hsotg->regs + GINTMSK);
}
}
*/
static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
{
- u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
+ u32 gsintmsk = readl(hsotg->regs + GINTMSK);
u32 new_gsintmsk;
new_gsintmsk = gsintmsk & ~ints;
if (new_gsintmsk != gsintmsk)
- writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
+ writel(new_gsintmsk, hsotg->regs + GINTMSK);
}
/**
bit <<= 16;
local_irq_save(flags);
- daint = readl(hsotg->regs + S3C_DAINTMSK);
+ daint = readl(hsotg->regs + DAINTMSK);
if (en)
daint |= bit;
else
daint &= ~bit;
- writel(daint, hsotg->regs + S3C_DAINTMSK);
+ writel(daint, hsotg->regs + DAINTMSK);
local_irq_restore(flags);
}
/* set FIFO sizes to 2048/1024 */
- writel(2048, hsotg->regs + S3C_GRXFSIZ);
- writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
- S3C_GNPTXFSIZ_NPTxFDep(1024),
- hsotg->regs + S3C_GNPTXFSIZ);
+ writel(2048, hsotg->regs + GRXFSIZ);
+ writel(GNPTXFSIZ_NPTxFStAddr(2048) |
+ GNPTXFSIZ_NPTxFDep(1024),
+ hsotg->regs + GNPTXFSIZ);
/*
* arange all the rest of the TX FIFOs, as some versions of this
for (ep = 1; ep <= 15; ep++) {
val = addr;
- val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
+ val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
addr += size;
- writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
+ writel(val, hsotg->regs + DPTXFSIZn(ep));
}
/*
* all fifos are flushed before continuing
*/
- writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
- S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
+ writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
+ GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
/* wait until the fifos are both flushed */
timeout = 100;
while (1) {
- val = readl(hsotg->regs + S3C_GRSTCTL);
+ val = readl(hsotg->regs + GRSTCTL);
- if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
+ if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
break;
if (--timeout == 0) {
struct s3c_hsotg_req *hs_req)
{
bool periodic = is_ep_periodic(hs_ep);
- u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
+ u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
int buf_pos = hs_req->req.actual;
int to_write = hs_ep->size_loaded;
void *data;
return 0;
if (periodic && !hsotg->dedicated_fifos) {
- u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
+ u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
int size_left;
int size_done;
* how much data is left in the fifo.
*/
- size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+ size_left = DxEPTSIZ_XferSize_GET(epsize);
/*
* if shared fifo, we cannot write anything until the
* previous data has been completely sent.
*/
if (hs_ep->fifo_load != 0) {
- s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+ s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
return -ENOSPC;
}
__func__, can_write);
if (can_write <= 0) {
- s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+ s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
return -ENOSPC;
}
} else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
- can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
+ can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
can_write &= 0xffff;
can_write *= 4;
} else {
- if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
+ if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
dev_dbg(hsotg->dev,
"%s: no queue slots available (0x%08x)\n",
__func__, gnptxsts);
- s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
+ s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
return -ENOSPC;
}
- can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
+ can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
can_write *= 4; /* fifo size is in 32bit quantities. */
}
to_write = hs_ep->ep.maxpacket;
s3c_hsotg_en_gsint(hsotg,
- periodic ? S3C_GINTSTS_PTxFEmp :
- S3C_GINTSTS_NPTxFEmp);
+ periodic ? GINTSTS_PTxFEmp :
+ GINTSTS_NPTxFEmp);
}
/* see if we can write data */
*/
s3c_hsotg_en_gsint(hsotg,
- periodic ? S3C_GINTSTS_PTxFEmp :
- S3C_GINTSTS_NPTxFEmp);
+ periodic ? GINTSTS_PTxFEmp :
+ GINTSTS_NPTxFEmp);
}
dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
to_write = DIV_ROUND_UP(to_write, 4);
data = hs_req->req.buf + buf_pos;
- writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
+ writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
return (to_write >= can_write) ? -ENOSPC : 0;
}
unsigned maxpkt;
if (index != 0) {
- maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
- maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
+ maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
+ maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
} else {
maxsize = 64+64;
if (hs_ep->dir_in)
- maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
+ maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
else
maxpkt = 2;
}
}
}
- epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
- epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
+ epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
+ epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
__func__, readl(hsotg->regs + epctrl_reg), index,
/* If endpoint is stalled, we will restart request later */
ctrl = readl(hsotg->regs + epctrl_reg);
- if (ctrl & S3C_DxEPCTL_Stall) {
+ if (ctrl & DxEPCTL_Stall) {
dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
return;
}
packets = 1; /* send one packet if length is zero. */
if (dir_in && index != 0)
- epsize = S3C_DxEPTSIZ_MC(1);
+ epsize = DxEPTSIZ_MC(1);
else
epsize = 0;
packets++;
}
- epsize |= S3C_DxEPTSIZ_PktCnt(packets);
- epsize |= S3C_DxEPTSIZ_XferSize(length);
+ epsize |= DxEPTSIZ_PktCnt(packets);
+ epsize |= DxEPTSIZ_XferSize(length);
dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
__func__, packets, length, ureq->length, epsize, epsize_reg);
* synced by s3c_hsotg_ep_queue().
*/
- dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
+ dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
writel(ureq->dma, hsotg->regs + dma_reg);
dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
__func__, ureq->dma, dma_reg);
}
- ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
- ctrl |= S3C_DxEPCTL_USBActEp;
+ ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
+ ctrl |= DxEPCTL_USBActEp;
dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
if (hsotg->setup && index == 0)
hsotg->setup = 0;
else
- ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
+ ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
* to debugging to see what is going on.
*/
if (dir_in)
- writel(S3C_DIEPMSK_INTknTXFEmpMsk,
- hsotg->regs + S3C_DIEPINT(index));
+ writel(DIEPMSK_INTknTXFEmpMsk,
+ hsotg->regs + DIEPINT(index));
/*
* Note, trying to clear the NAK here causes problems with transmit
*/
/* check ep is enabled */
- if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
+ if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
dev_warn(hsotg->dev,
"ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
index, readl(hsotg->regs + epctrl_reg));
if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
switch (ctrl->bRequest) {
case USB_REQ_SET_ADDRESS:
- dcfg = readl(hsotg->regs + S3C_DCFG);
- dcfg &= ~S3C_DCFG_DevAddr_MASK;
- dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
- writel(dcfg, hsotg->regs + S3C_DCFG);
+ dcfg = readl(hsotg->regs + DCFG);
+ dcfg &= ~DCFG_DevAddr_MASK;
+ dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
+ writel(dcfg, hsotg->regs + DCFG);
dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
u32 ctrl;
dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
- reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
+ reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
/*
- * S3C_DxEPCTL_Stall will be cleared by EP once it has
+ * DxEPCTL_Stall will be cleared by EP once it has
* taken effect, so no need to clear later.
*/
ctrl = readl(hsotg->regs + reg);
- ctrl |= S3C_DxEPCTL_Stall;
- ctrl |= S3C_DxEPCTL_CNAK;
+ ctrl |= DxEPCTL_Stall;
+ ctrl |= DxEPCTL_CNAK;
writel(ctrl, hsotg->regs + reg);
dev_dbg(hsotg->dev,
{
struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
struct s3c_hsotg_req *hs_req = hs_ep->req;
- void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
+ void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
int to_read;
int max_req;
int read_ptr;
if (!hs_req) {
- u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
+ u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
int ptr;
dev_warn(hsotg->dev,
dev_dbg(hsotg->dev, "sending zero-length packet\n");
/* issue a zero-sized packet to terminate this */
- writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
- S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
+ writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
+ DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
- ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
- ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
- ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
- ctrl |= S3C_DxEPCTL_USBActEp;
- writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
+ ctrl = readl(hsotg->regs + DIEPCTL0);
+ ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
+ ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
+ ctrl |= DxEPCTL_USBActEp;
+ writel(ctrl, hsotg->regs + DIEPCTL0);
}
/**
static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
int epnum, bool was_setup)
{
- u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
+ u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
struct s3c_hsotg_req *hs_req = hs_ep->req;
struct usb_request *req = &hs_req->req;
- unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+ unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
int result = 0;
if (!hs_req) {
{
u32 dsts;
- dsts = readl(hsotg->regs + S3C_DSTS);
- dsts &= S3C_DSTS_SOFFN_MASK;
- dsts >>= S3C_DSTS_SOFFN_SHIFT;
+ dsts = readl(hsotg->regs + DSTS);
+ dsts &= DSTS_SOFFN_MASK;
+ dsts >>= DSTS_SOFFN_SHIFT;
return dsts;
}
*/
static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
{
- u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
+ u32 grxstsr = readl(hsotg->regs + GRXSTSP);
u32 epnum, status, size;
WARN_ON(using_dma(hsotg));
- epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
- status = grxstsr & S3C_GRXSTS_PktSts_MASK;
+ epnum = grxstsr & GRXSTS_EPNum_MASK;
+ status = grxstsr & GRXSTS_PktSts_MASK;
- size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
- size >>= S3C_GRXSTS_ByteCnt_SHIFT;
+ size = grxstsr & GRXSTS_ByteCnt_MASK;
+ size >>= GRXSTS_ByteCnt_SHIFT;
if (1)
dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
__func__, grxstsr, size, epnum);
-#define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
+#define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
- switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
- case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
+ switch (status >> GRXSTS_PktSts_SHIFT) {
+ case __status(GRXSTS_PktSts_GlobalOutNAK):
dev_dbg(hsotg->dev, "GlobalOutNAK\n");
break;
- case __status(S3C_GRXSTS_PktSts_OutDone):
+ case __status(GRXSTS_PktSts_OutDone):
dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
s3c_hsotg_read_frameno(hsotg));
s3c_hsotg_handle_outdone(hsotg, epnum, false);
break;
- case __status(S3C_GRXSTS_PktSts_SetupDone):
+ case __status(GRXSTS_PktSts_SetupDone):
dev_dbg(hsotg->dev,
"SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
s3c_hsotg_read_frameno(hsotg),
- readl(hsotg->regs + S3C_DOEPCTL(0)));
+ readl(hsotg->regs + DOEPCTL(0)));
s3c_hsotg_handle_outdone(hsotg, epnum, true);
break;
- case __status(S3C_GRXSTS_PktSts_OutRX):
+ case __status(GRXSTS_PktSts_OutRX):
s3c_hsotg_rx_data(hsotg, epnum, size);
break;
- case __status(S3C_GRXSTS_PktSts_SetupRX):
+ case __status(GRXSTS_PktSts_SetupRX):
dev_dbg(hsotg->dev,
"SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
s3c_hsotg_read_frameno(hsotg),
- readl(hsotg->regs + S3C_DOEPCTL(0)));
+ readl(hsotg->regs + DOEPCTL(0)));
s3c_hsotg_rx_data(hsotg, epnum, size);
break;
{
switch (mps) {
case 64:
- return S3C_D0EPCTL_MPS_64;
+ return D0EPCTL_MPS_64;
case 32:
- return S3C_D0EPCTL_MPS_32;
+ return D0EPCTL_MPS_32;
case 16:
- return S3C_D0EPCTL_MPS_16;
+ return D0EPCTL_MPS_16;
case 8:
- return S3C_D0EPCTL_MPS_8;
+ return D0EPCTL_MPS_8;
}
/* bad max packet size, warn and return invalid result */
if (mpsval > 3)
goto bad_mps;
} else {
- if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
+ if (mps >= DxEPCTL_MPS_LIMIT+1)
goto bad_mps;
mpsval = mps;
* if one of the directions may not be in use.
*/
- reg = readl(regs + S3C_DIEPCTL(ep));
- reg &= ~S3C_DxEPCTL_MPS_MASK;
+ reg = readl(regs + DIEPCTL(ep));
+ reg &= ~DxEPCTL_MPS_MASK;
reg |= mpsval;
- writel(reg, regs + S3C_DIEPCTL(ep));
+ writel(reg, regs + DIEPCTL(ep));
if (ep) {
- reg = readl(regs + S3C_DOEPCTL(ep));
- reg &= ~S3C_DxEPCTL_MPS_MASK;
+ reg = readl(regs + DOEPCTL(ep));
+ reg &= ~DxEPCTL_MPS_MASK;
reg |= mpsval;
- writel(reg, regs + S3C_DOEPCTL(ep));
+ writel(reg, regs + DOEPCTL(ep));
}
return;
int timeout;
int val;
- writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh,
- hsotg->regs + S3C_GRSTCTL);
+ writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
+ hsotg->regs + GRSTCTL);
/* wait until the fifo is flushed */
timeout = 100;
while (1) {
- val = readl(hsotg->regs + S3C_GRSTCTL);
+ val = readl(hsotg->regs + GRSTCTL);
- if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0)
+ if ((val & (GRSTCTL_TxFFlsh)) == 0)
break;
if (--timeout == 0) {
struct s3c_hsotg_ep *hs_ep)
{
struct s3c_hsotg_req *hs_req = hs_ep->req;
- u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
+ u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
int size_left, size_done;
if (!hs_req) {
* aligned).
*/
- size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+ size_left = DxEPTSIZ_XferSize_GET(epsize);
size_done = hs_ep->size_loaded - size_left;
size_done += hs_ep->last_load;
int dir_in)
{
struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
- u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
- u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
- u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
+ u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
+ u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
+ u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
u32 ints;
ints = readl(hsotg->regs + epint_reg);
dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
__func__, idx, dir_in ? "in" : "out", ints);
- if (ints & S3C_DxEPINT_XferCompl) {
+ if (ints & DxEPINT_XferCompl) {
dev_dbg(hsotg->dev,
"%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
__func__, readl(hsotg->regs + epctl_reg),
}
}
- if (ints & S3C_DxEPINT_EPDisbld) {
+ if (ints & DxEPINT_EPDisbld) {
dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
if (dir_in) {
s3c_hsotg_txfifo_flush(hsotg, idx);
- if ((epctl & S3C_DxEPCTL_Stall) &&
- (epctl & S3C_DxEPCTL_EPType_Bulk)) {
- int dctl = readl(hsotg->regs + S3C_DCTL);
+ if ((epctl & DxEPCTL_Stall) &&
+ (epctl & DxEPCTL_EPType_Bulk)) {
+ int dctl = readl(hsotg->regs + DCTL);
- dctl |= S3C_DCTL_CGNPInNAK;
- writel(dctl, hsotg->regs + S3C_DCTL);
+ dctl |= DCTL_CGNPInNAK;
+ writel(dctl, hsotg->regs + DCTL);
}
}
}
- if (ints & S3C_DxEPINT_AHBErr)
+ if (ints & DxEPINT_AHBErr)
dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
- if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
+ if (ints & DxEPINT_Setup) { /* Setup or Timeout */
dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
if (using_dma(hsotg) && idx == 0) {
}
}
- if (ints & S3C_DxEPINT_Back2BackSetup)
+ if (ints & DxEPINT_Back2BackSetup)
dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
if (dir_in) {
/* not sure if this is important, but we'll clear it anyway */
- if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
+ if (ints & DIEPMSK_INTknTXFEmpMsk) {
dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
__func__, idx);
}
/* this probably means something bad is happening */
- if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
+ if (ints & DIEPMSK_INTknEPMisMsk) {
dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
__func__, idx);
}
/* FIFO has space or is empty (see GAHBCFG) */
if (hsotg->dedicated_fifos &&
- ints & S3C_DIEPMSK_TxFIFOEmpty) {
+ ints & DIEPMSK_TxFIFOEmpty) {
dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
__func__, idx);
if (!using_dma(hsotg))
*/
static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
{
- u32 dsts = readl(hsotg->regs + S3C_DSTS);
+ u32 dsts = readl(hsotg->regs + DSTS);
int ep0_mps = 0, ep_mps;
/*
*/
/* catch both EnumSpd_FS and EnumSpd_FS48 */
- switch (dsts & S3C_DSTS_EnumSpd_MASK) {
- case S3C_DSTS_EnumSpd_FS:
- case S3C_DSTS_EnumSpd_FS48:
+ switch (dsts & DSTS_EnumSpd_MASK) {
+ case DSTS_EnumSpd_FS:
+ case DSTS_EnumSpd_FS48:
hsotg->gadget.speed = USB_SPEED_FULL;
ep0_mps = EP0_MPS_LIMIT;
ep_mps = 64;
break;
- case S3C_DSTS_EnumSpd_HS:
+ case DSTS_EnumSpd_HS:
hsotg->gadget.speed = USB_SPEED_HIGH;
ep0_mps = EP0_MPS_LIMIT;
ep_mps = 512;
break;
- case S3C_DSTS_EnumSpd_LS:
+ case DSTS_EnumSpd_LS:
hsotg->gadget.speed = USB_SPEED_LOW;
/*
* note, we don't actually support LS in this driver at the
s3c_hsotg_enqueue_setup(hsotg);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
- readl(hsotg->regs + S3C_DIEPCTL0),
- readl(hsotg->regs + S3C_DOEPCTL0));
+ readl(hsotg->regs + DIEPCTL0),
+ readl(hsotg->regs + DOEPCTL0));
}
/**
}
/* IRQ flags which will trigger a retry around the IRQ loop */
-#define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
- S3C_GINTSTS_PTxFEmp | \
- S3C_GINTSTS_RxFLvl)
+#define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
+ GINTSTS_PTxFEmp | \
+ GINTSTS_RxFLvl)
/**
* s3c_hsotg_corereset - issue softreset to the core
dev_dbg(hsotg->dev, "resetting core\n");
/* issue soft reset */
- writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
+ writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
timeout = 1000;
do {
- grstctl = readl(hsotg->regs + S3C_GRSTCTL);
- } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
+ grstctl = readl(hsotg->regs + GRSTCTL);
+ } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
- if (grstctl & S3C_GRSTCTL_CSftRst) {
+ if (grstctl & GRSTCTL_CSftRst) {
dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
return -EINVAL;
}
timeout = 1000;
while (1) {
- u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
+ u32 grstctl = readl(hsotg->regs + GRSTCTL);
if (timeout-- < 0) {
dev_info(hsotg->dev,
return -ETIMEDOUT;
}
- if (!(grstctl & S3C_GRSTCTL_AHBIdle))
+ if (!(grstctl & GRSTCTL_AHBIdle))
continue;
break; /* reset done */
*/
/* set the PLL on, remove the HNP/SRP and set the PHY */
- writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
- (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
+ writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
+ (0x5 << 10), hsotg->regs + GUSBCFG);
s3c_hsotg_init_fifo(hsotg);
- __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+ __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
- writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
+ writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
/* Clear any pending OTG interrupts */
- writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
+ writel(0xffffffff, hsotg->regs + GOTGINT);
/* Clear any pending interrupts */
- writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
+ writel(0xffffffff, hsotg->regs + GINTSTS);
- writel(S3C_GINTSTS_ErlySusp | S3C_GINTSTS_SessReqInt |
- S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
- S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
- S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
- S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt,
- hsotg->regs + S3C_GINTMSK);
+ writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
+ GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
+ GINTSTS_ConIDStsChng | GINTSTS_USBRst |
+ GINTSTS_EnumDone | GINTSTS_OTGInt |
+ GINTSTS_USBSusp | GINTSTS_WkUpInt,
+ hsotg->regs + GINTMSK);
if (using_dma(hsotg))
- writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
- S3C_GAHBCFG_HBstLen_Incr4,
- hsotg->regs + S3C_GAHBCFG);
+ writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
+ GAHBCFG_HBstLen_Incr4,
+ hsotg->regs + GAHBCFG);
else
- writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
+ writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG);
/*
* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
* endpoint to try and read data.
*/
- writel(((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0) |
- S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
- S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
- S3C_DIEPMSK_INTknEPMisMsk,
- hsotg->regs + S3C_DIEPMSK);
+ writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) |
+ DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
+ DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
+ DIEPMSK_INTknEPMisMsk,
+ hsotg->regs + DIEPMSK);
/*
* don't need XferCompl, we get that from RXFIFO in slave mode. In
* DMA mode we may need this.
*/
- writel((using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
- S3C_DIEPMSK_TimeOUTMsk) : 0) |
- S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_AHBErrMsk |
- S3C_DOEPMSK_SetupMsk,
- hsotg->regs + S3C_DOEPMSK);
+ writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
+ DIEPMSK_TimeOUTMsk) : 0) |
+ DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
+ DOEPMSK_SetupMsk,
+ hsotg->regs + DOEPMSK);
- writel(0, hsotg->regs + S3C_DAINTMSK);
+ writel(0, hsotg->regs + DAINTMSK);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
- readl(hsotg->regs + S3C_DIEPCTL0),
- readl(hsotg->regs + S3C_DOEPCTL0));
+ readl(hsotg->regs + DIEPCTL0),
+ readl(hsotg->regs + DOEPCTL0));
/* enable in and out endpoint interrupts */
- s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
+ s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
/*
* Enable the RXFIFO when in slave mode, as this is how we collect
* things we cannot process, so do not use it.
*/
if (!using_dma(hsotg))
- s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
+ s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
/* Enable interrupts for EP0 in and out */
s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
- __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
+ __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
udelay(10); /* see openiboot */
- __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
+ __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
- dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
+ dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
/*
- * S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
+ * DxEPCTL_USBActEp says RO in manual, but seems to be set by
* writing to the EPCTL register..
*/
/* set to read 1 8byte packet */
- writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
- S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
+ writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
+ DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
- S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
- S3C_DxEPCTL_USBActEp,
- hsotg->regs + S3C_DOEPCTL0);
+ DxEPCTL_CNAK | DxEPCTL_EPEna |
+ DxEPCTL_USBActEp,
+ hsotg->regs + DOEPCTL0);
/* enable, but don't activate EP0in */
writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
- S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
+ DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
s3c_hsotg_enqueue_setup(hsotg);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
- readl(hsotg->regs + S3C_DIEPCTL0),
- readl(hsotg->regs + S3C_DOEPCTL0));
+ readl(hsotg->regs + DIEPCTL0),
+ readl(hsotg->regs + DOEPCTL0));
/* clear global NAKs */
- writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
- hsotg->regs + S3C_DCTL);
+ writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
+ hsotg->regs + DCTL);
/* must be at-least 3ms to allow bus to see disconnect */
mdelay(3);
/* remove the soft-disconnect and let's go */
- __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+ __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
}
/**
u32 gintmsk;
irq_retry:
- gintsts = readl(hsotg->regs + S3C_GINTSTS);
- gintmsk = readl(hsotg->regs + S3C_GINTMSK);
+ gintsts = readl(hsotg->regs + GINTSTS);
+ gintmsk = readl(hsotg->regs + GINTMSK);
dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
__func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
gintsts &= gintmsk;
- if (gintsts & S3C_GINTSTS_OTGInt) {
- u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
+ if (gintsts & GINTSTS_OTGInt) {
+ u32 otgint = readl(hsotg->regs + GOTGINT);
dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
- writel(otgint, hsotg->regs + S3C_GOTGINT);
+ writel(otgint, hsotg->regs + GOTGINT);
}
- if (gintsts & S3C_GINTSTS_SessReqInt) {
+ if (gintsts & GINTSTS_SessReqInt) {
dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
- writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
+ writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
}
- if (gintsts & S3C_GINTSTS_EnumDone) {
- writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
+ if (gintsts & GINTSTS_EnumDone) {
+ writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
s3c_hsotg_irq_enumdone(hsotg);
}
- if (gintsts & S3C_GINTSTS_ConIDStsChng) {
+ if (gintsts & GINTSTS_ConIDStsChng) {
dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
- readl(hsotg->regs + S3C_DSTS),
- readl(hsotg->regs + S3C_GOTGCTL));
+ readl(hsotg->regs + DSTS),
+ readl(hsotg->regs + GOTGCTL));
- writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
+ writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
}
- if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
- u32 daint = readl(hsotg->regs + S3C_DAINT);
- u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
- u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
+ if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
+ u32 daint = readl(hsotg->regs + DAINT);
+ u32 daint_out = daint >> DAINT_OutEP_SHIFT;
+ u32 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
int ep;
dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
}
}
- if (gintsts & S3C_GINTSTS_USBRst) {
+ if (gintsts & GINTSTS_USBRst) {
- u32 usb_status = readl(hsotg->regs + S3C_GOTGCTL);
+ u32 usb_status = readl(hsotg->regs + GOTGCTL);
dev_info(hsotg->dev, "%s: USBRst\n", __func__);
dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
- readl(hsotg->regs + S3C_GNPTXSTS));
+ readl(hsotg->regs + GNPTXSTS));
- writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
+ writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
- if (usb_status & S3C_GOTGCTL_BSESVLD) {
+ if (usb_status & GOTGCTL_BSESVLD) {
if (time_after(jiffies, hsotg->last_rst +
msecs_to_jiffies(200))) {
/* check both FIFOs */
- if (gintsts & S3C_GINTSTS_NPTxFEmp) {
+ if (gintsts & GINTSTS_NPTxFEmp) {
dev_dbg(hsotg->dev, "NPTxFEmp\n");
/*
* it needs re-enabling
*/
- s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
+ s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
s3c_hsotg_irq_fifoempty(hsotg, false);
}
- if (gintsts & S3C_GINTSTS_PTxFEmp) {
+ if (gintsts & GINTSTS_PTxFEmp) {
dev_dbg(hsotg->dev, "PTxFEmp\n");
- /* See note in S3C_GINTSTS_NPTxFEmp */
+ /* See note in GINTSTS_NPTxFEmp */
- s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+ s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
s3c_hsotg_irq_fifoempty(hsotg, true);
}
- if (gintsts & S3C_GINTSTS_RxFLvl) {
+ if (gintsts & GINTSTS_RxFLvl) {
/*
* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
* we need to retry s3c_hsotg_handle_rx if this is still
s3c_hsotg_handle_rx(hsotg);
}
- if (gintsts & S3C_GINTSTS_ModeMis) {
+ if (gintsts & GINTSTS_ModeMis) {
dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
- writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
+ writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
}
- if (gintsts & S3C_GINTSTS_USBSusp) {
- dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
- writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
+ if (gintsts & GINTSTS_USBSusp) {
+ dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
+ writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
call_gadget(hsotg, suspend);
s3c_hsotg_disconnect(hsotg);
}
- if (gintsts & S3C_GINTSTS_WkUpInt) {
- dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
- writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
+ if (gintsts & GINTSTS_WkUpInt) {
+ dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
+ writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
call_gadget(hsotg, resume);
}
- if (gintsts & S3C_GINTSTS_ErlySusp) {
- dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
- writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
+ if (gintsts & GINTSTS_ErlySusp) {
+ dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
+ writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
s3c_hsotg_disconnect(hsotg);
}
* the occurrence.
*/
- if (gintsts & S3C_GINTSTS_GOUTNakEff) {
+ if (gintsts & GINTSTS_GOUTNakEff) {
dev_info(hsotg->dev, "GOUTNakEff triggered\n");
- writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
+ writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
s3c_hsotg_dump(hsotg);
}
- if (gintsts & S3C_GINTSTS_GINNakEff) {
+ if (gintsts & GINTSTS_GINNakEff) {
dev_info(hsotg->dev, "GINNakEff triggered\n");
- writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
+ writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
s3c_hsotg_dump(hsotg);
}
/* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
- epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+ epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
epctrl = readl(hsotg->regs + epctrl_reg);
dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
spin_lock_irqsave(&hs_ep->lock, flags);
- epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
- epctrl |= S3C_DxEPCTL_MPS(mps);
+ epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
+ epctrl |= DxEPCTL_MPS(mps);
/*
* mark the endpoint as active, otherwise the core may ignore
* transactions entirely for this endpoint
*/
- epctrl |= S3C_DxEPCTL_USBActEp;
+ epctrl |= DxEPCTL_USBActEp;
/*
* set the NAK status on the endpoint, otherwise we might try and
* size register hasn't been set.
*/
- epctrl |= S3C_DxEPCTL_SNAK;
+ epctrl |= DxEPCTL_SNAK;
/* update the endpoint state */
hs_ep->ep.maxpacket = mps;
goto out;
case USB_ENDPOINT_XFER_BULK:
- epctrl |= S3C_DxEPCTL_EPType_Bulk;
+ epctrl |= DxEPCTL_EPType_Bulk;
break;
case USB_ENDPOINT_XFER_INT:
*/
hs_ep->periodic = 1;
- epctrl |= S3C_DxEPCTL_TxFNum(index);
+ epctrl |= DxEPCTL_TxFNum(index);
}
- epctrl |= S3C_DxEPCTL_EPType_Intterupt;
+ epctrl |= DxEPCTL_EPType_Intterupt;
break;
case USB_ENDPOINT_XFER_CONTROL:
- epctrl |= S3C_DxEPCTL_EPType_Control;
+ epctrl |= DxEPCTL_EPType_Control;
break;
}
* a unique tx-fifo even if it is non-periodic.
*/
if (dir_in && hsotg->dedicated_fifos)
- epctrl |= S3C_DxEPCTL_TxFNum(index);
+ epctrl |= DxEPCTL_TxFNum(index);
/* for non control endpoints, set PID to D0 */
if (index)
- epctrl |= S3C_DxEPCTL_SetD0PID;
+ epctrl |= DxEPCTL_SetD0PID;
dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
__func__, epctrl);
return -EINVAL;
}
- epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+ epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
/* terminate all requests with shutdown */
kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
spin_lock_irqsave(&hs_ep->lock, flags);
ctrl = readl(hsotg->regs + epctrl_reg);
- ctrl &= ~S3C_DxEPCTL_EPEna;
- ctrl &= ~S3C_DxEPCTL_USBActEp;
- ctrl |= S3C_DxEPCTL_SNAK;
+ ctrl &= ~DxEPCTL_EPEna;
+ ctrl &= ~DxEPCTL_USBActEp;
+ ctrl |= DxEPCTL_SNAK;
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
writel(ctrl, hsotg->regs + epctrl_reg);
/* write both IN and OUT control registers */
- epreg = S3C_DIEPCTL(index);
+ epreg = DIEPCTL(index);
epctl = readl(hs->regs + epreg);
if (value) {
- epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK;
- if (epctl & S3C_DxEPCTL_EPEna)
- epctl |= S3C_DxEPCTL_EPDis;
+ epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
+ if (epctl & DxEPCTL_EPEna)
+ epctl |= DxEPCTL_EPDis;
} else {
- epctl &= ~S3C_DxEPCTL_Stall;
- xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
- if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
- xfertype == S3C_DxEPCTL_EPType_Intterupt)
- epctl |= S3C_DxEPCTL_SetD0PID;
+ epctl &= ~DxEPCTL_Stall;
+ xfertype = epctl & DxEPCTL_EPType_MASK;
+ if (xfertype == DxEPCTL_EPType_Bulk ||
+ xfertype == DxEPCTL_EPType_Intterupt)
+ epctl |= DxEPCTL_SetD0PID;
}
writel(epctl, hs->regs + epreg);
- epreg = S3C_DOEPCTL(index);
+ epreg = DOEPCTL(index);
epctl = readl(hs->regs + epreg);
if (value)
- epctl |= S3C_DxEPCTL_Stall;
+ epctl |= DxEPCTL_Stall;
else {
- epctl &= ~S3C_DxEPCTL_Stall;
- xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
- if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
- xfertype == S3C_DxEPCTL_EPType_Intterupt)
- epctl |= S3C_DxEPCTL_SetD0PID;
+ epctl &= ~DxEPCTL_Stall;
+ xfertype = epctl & DxEPCTL_EPType_MASK;
+ if (xfertype == DxEPCTL_EPType_Bulk ||
+ xfertype == DxEPCTL_EPType_Intterupt)
+ epctl |= DxEPCTL_SetD0PID;
}
writel(epctl, hs->regs + epreg);
{
/* unmask subset of endpoint interrupts */
- writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
- S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
- hsotg->regs + S3C_DIEPMSK);
+ writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
+ DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
+ hsotg->regs + DIEPMSK);
- writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
- S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
- hsotg->regs + S3C_DOEPMSK);
+ writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
+ DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
+ hsotg->regs + DOEPMSK);
- writel(0, hsotg->regs + S3C_DAINTMSK);
+ writel(0, hsotg->regs + DAINTMSK);
/* Be in disconnected state until gadget is registered */
- __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+ __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
if (0) {
/* post global nak until we're ready */
- writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
- hsotg->regs + S3C_DCTL);
+ writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
+ hsotg->regs + DCTL);
}
/* setup fifos */
dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
- readl(hsotg->regs + S3C_GRXFSIZ),
- readl(hsotg->regs + S3C_GNPTXFSIZ));
+ readl(hsotg->regs + GRXFSIZ),
+ readl(hsotg->regs + GNPTXFSIZ));
s3c_hsotg_init_fifo(hsotg);
/* set the PLL on, remove the HNP/SRP and set the PHY */
- writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
- hsotg->regs + S3C_GUSBCFG);
+ writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
+ hsotg->regs + GUSBCFG);
- writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
- hsotg->regs + S3C_GAHBCFG);
+ writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
+ hsotg->regs + GAHBCFG);
}
/**
* code is changed to make each endpoint's direction changeable.
*/
- ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
- hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
+ ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
+ hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
/*
* if we're using dma, we need to set the next-endpoint pointer
*/
if (using_dma(hsotg)) {
- u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
- writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
- writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
+ u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
+ writel(next, hsotg->regs + DIEPCTL(epnum));
+ writel(next, hsotg->regs + DOEPCTL(epnum));
}
}
int idx;
dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
- readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
- readl(regs + S3C_DIEPMSK));
+ readl(regs + DCFG), readl(regs + DCTL),
+ readl(regs + DIEPMSK));
dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
- readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
+ readl(regs + GAHBCFG), readl(regs + 0x44));
dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
- readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
+ readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
/* show periodic fifo settings */
for (idx = 1; idx <= 15; idx++) {
- val = readl(regs + S3C_DPTXFSIZn(idx));
+ val = readl(regs + DPTXFSIZn(idx));
dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
- val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
- val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
+ val >> DPTXFSIZn_DPTxFSize_SHIFT,
+ val & DPTXFSIZn_DPTxFStAddr_MASK);
}
for (idx = 0; idx < 15; idx++) {
dev_info(dev,
"ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
- readl(regs + S3C_DIEPCTL(idx)),
- readl(regs + S3C_DIEPTSIZ(idx)),
- readl(regs + S3C_DIEPDMA(idx)));
+ readl(regs + DIEPCTL(idx)),
+ readl(regs + DIEPTSIZ(idx)),
+ readl(regs + DIEPDMA(idx)));
- val = readl(regs + S3C_DOEPCTL(idx));
+ val = readl(regs + DOEPCTL(idx));
dev_info(dev,
"ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
- idx, readl(regs + S3C_DOEPCTL(idx)),
- readl(regs + S3C_DOEPTSIZ(idx)),
- readl(regs + S3C_DOEPDMA(idx)));
+ idx, readl(regs + DOEPCTL(idx)),
+ readl(regs + DOEPTSIZ(idx)),
+ readl(regs + DOEPDMA(idx)));
}
dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
- readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
+ readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
#endif
}
int idx;
seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
- readl(regs + S3C_DCFG),
- readl(regs + S3C_DCTL),
- readl(regs + S3C_DSTS));
+ readl(regs + DCFG),
+ readl(regs + DCTL),
+ readl(regs + DSTS));
seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
- readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
+ readl(regs + DIEPMSK), readl(regs + DOEPMSK));
seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
- readl(regs + S3C_GINTMSK),
- readl(regs + S3C_GINTSTS));
+ readl(regs + GINTMSK),
+ readl(regs + GINTSTS));
seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
- readl(regs + S3C_DAINTMSK),
- readl(regs + S3C_DAINT));
+ readl(regs + DAINTMSK),
+ readl(regs + DAINT));
seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
- readl(regs + S3C_GNPTXSTS),
- readl(regs + S3C_GRXSTSR));
+ readl(regs + GNPTXSTS),
+ readl(regs + GRXSTSR));
seq_printf(seq, "\nEndpoint status:\n");
for (idx = 0; idx < 15; idx++) {
u32 in, out;
- in = readl(regs + S3C_DIEPCTL(idx));
- out = readl(regs + S3C_DOEPCTL(idx));
+ in = readl(regs + DIEPCTL(idx));
+ out = readl(regs + DOEPCTL(idx));
seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
idx, in, out);
- in = readl(regs + S3C_DIEPTSIZ(idx));
- out = readl(regs + S3C_DOEPTSIZ(idx));
+ in = readl(regs + DIEPTSIZ(idx));
+ out = readl(regs + DOEPTSIZ(idx));
seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
in, out);
int idx;
seq_printf(seq, "Non-periodic FIFOs:\n");
- seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
+ seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
- val = readl(regs + S3C_GNPTXFSIZ);
+ val = readl(regs + GNPTXFSIZ);
seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
- val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
- val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
+ val >> GNPTXFSIZ_NPTxFDep_SHIFT,
+ val & GNPTXFSIZ_NPTxFStAddr_MASK);
seq_printf(seq, "\nPeriodic TXFIFOs:\n");
for (idx = 1; idx <= 15; idx++) {
- val = readl(regs + S3C_DPTXFSIZn(idx));
+ val = readl(regs + DPTXFSIZn(idx));
seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
- val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
- val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
+ val >> DPTXFSIZn_DPTxFSize_SHIFT,
+ val & DPTXFSIZn_DPTxFStAddr_MASK);
}
return 0;
/* first show the register state */
seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
- readl(regs + S3C_DIEPCTL(index)),
- readl(regs + S3C_DOEPCTL(index)));
+ readl(regs + DIEPCTL(index)),
+ readl(regs + DOEPCTL(index)));
seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
- readl(regs + S3C_DIEPDMA(index)),
- readl(regs + S3C_DOEPDMA(index)));
+ readl(regs + DIEPDMA(index)),
+ readl(regs + DOEPDMA(index)));
seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
- readl(regs + S3C_DIEPINT(index)),
- readl(regs + S3C_DOEPINT(index)));
+ readl(regs + DIEPINT(index)),
+ readl(regs + DOEPINT(index)));
seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
- readl(regs + S3C_DIEPTSIZ(index)),
- readl(regs + S3C_DOEPTSIZ(index)));
+ readl(regs + DIEPTSIZ(index)),
+ readl(regs + DOEPTSIZ(index)));
seq_printf(seq, "\n");
seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
-/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
+/* drivers/usb/gadget/s3c-hsotg.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
- * S3C - USB2.0 Highspeed/OtG device block registers
+ * USB2.0 Highspeed/OtG Synopsis DWC2 device block registers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
-#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
-
-#define S3C_HSOTG_REG(x) (x)
-
-#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
-#define S3C_GOTGCTL_BSESVLD (1 << 19)
-#define S3C_GOTGCTL_ASESVLD (1 << 18)
-#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
-#define S3C_GOTGCTL_CONID_B (1 << 16)
-#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
-#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
-#define S3C_GOTGCTL_HNPREQ (1 << 9)
-#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
-#define S3C_GOTGCTL_SESREQ (1 << 1)
-#define S3C_GOTGCTL_SESREQSCS (1 << 0)
-
-#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
-#define S3C_GOTGINT_DbnceDone (1 << 19)
-#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
-#define S3C_GOTGINT_HstNegDet (1 << 17)
-#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
-#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
-#define S3C_GOTGINT_SesEndDet (1 << 2)
-
-#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
-#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
-#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
-#define S3C_GAHBCFG_DMAEn (1 << 5)
-#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
-#define S3C_GAHBCFG_HBstLen_SHIFT (1)
-#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
-#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
-
-#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
-#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
-#define S3C_GUSBCFG_HNPCap (1 << 9)
-#define S3C_GUSBCFG_SRPCap (1 << 8)
-#define S3C_GUSBCFG_PHYIf16 (1 << 3)
-#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
-#define S3C_GUSBCFG_TOutCal_SHIFT (0)
-#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
-#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
-
-#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
-
-#define S3C_GRSTCTL_AHBIdle (1 << 31)
-#define S3C_GRSTCTL_DMAReq (1 << 30)
-#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
-#define S3C_GRSTCTL_TxFNum_SHIFT (6)
-#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
-#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
-#define S3C_GRSTCTL_TxFFlsh (1 << 5)
-#define S3C_GRSTCTL_RxFFlsh (1 << 4)
-#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
-#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
-#define S3C_GRSTCTL_HSftRst (1 << 1)
-#define S3C_GRSTCTL_CSftRst (1 << 0)
-
-#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
-#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
-
-#define S3C_GINTSTS_WkUpInt (1 << 31)
-#define S3C_GINTSTS_SessReqInt (1 << 30)
-#define S3C_GINTSTS_DisconnInt (1 << 29)
-#define S3C_GINTSTS_ConIDStsChng (1 << 28)
-#define S3C_GINTSTS_PTxFEmp (1 << 26)
-#define S3C_GINTSTS_HChInt (1 << 25)
-#define S3C_GINTSTS_PrtInt (1 << 24)
-#define S3C_GINTSTS_FetSusp (1 << 22)
-#define S3C_GINTSTS_incompIP (1 << 21)
-#define S3C_GINTSTS_IncomplSOIN (1 << 20)
-#define S3C_GINTSTS_OEPInt (1 << 19)
-#define S3C_GINTSTS_IEPInt (1 << 18)
-#define S3C_GINTSTS_EPMis (1 << 17)
-#define S3C_GINTSTS_EOPF (1 << 15)
-#define S3C_GINTSTS_ISOutDrop (1 << 14)
-#define S3C_GINTSTS_EnumDone (1 << 13)
-#define S3C_GINTSTS_USBRst (1 << 12)
-#define S3C_GINTSTS_USBSusp (1 << 11)
-#define S3C_GINTSTS_ErlySusp (1 << 10)
-#define S3C_GINTSTS_GOUTNakEff (1 << 7)
-#define S3C_GINTSTS_GINNakEff (1 << 6)
-#define S3C_GINTSTS_NPTxFEmp (1 << 5)
-#define S3C_GINTSTS_RxFLvl (1 << 4)
-#define S3C_GINTSTS_SOF (1 << 3)
-#define S3C_GINTSTS_OTGInt (1 << 2)
-#define S3C_GINTSTS_ModeMis (1 << 1)
-#define S3C_GINTSTS_CurMod_Host (1 << 0)
-
-#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
-#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
-
-#define S3C_GRXSTS_FN_MASK (0x7f << 25)
-#define S3C_GRXSTS_FN_SHIFT (25)
-
-#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
-#define S3C_GRXSTS_PktSts_SHIFT (17)
-#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
-#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
-#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
-#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
-#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
-
-#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
-#define S3C_GRXSTS_DPID_SHIFT (15)
-#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
-#define S3C_GRXSTS_ByteCnt_SHIFT (4)
-#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
-#define S3C_GRXSTS_EPNum_SHIFT (0)
-
-#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
-
-#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
-
-#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
-#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
-#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
-#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
-#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
-#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
-#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
-#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
-
-#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
-
-#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
-#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
-
-#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
-#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
-#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
-
-#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
-#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
-#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
-
-
-#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
-
-#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
-
-#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
-#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
-#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
-#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
-#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
-
-#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
-#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
+#ifndef __REGS_USB_HSOTG_H
+#define __REGS_USB_HSOTG_H __FILE__
+
+#define HSOTG_REG(x) (x)
+
+#define GOTGCTL HSOTG_REG(0x000)
+#define GOTGCTL_BSESVLD (1 << 19)
+#define GOTGCTL_ASESVLD (1 << 18)
+#define GOTGCTL_DBNC_SHORT (1 << 17)
+#define GOTGCTL_CONID_B (1 << 16)
+#define GOTGCTL_DEVHNPEN (1 << 11)
+#define GOTGCTL_HSSETHNPEN (1 << 10)
+#define GOTGCTL_HNPREQ (1 << 9)
+#define GOTGCTL_HSTNEGSCS (1 << 8)
+#define GOTGCTL_SESREQ (1 << 1)
+#define GOTGCTL_SESREQSCS (1 << 0)
+
+#define GOTGINT HSOTG_REG(0x004)
+#define GOTGINT_DbnceDone (1 << 19)
+#define GOTGINT_ADevTOUTChg (1 << 18)
+#define GOTGINT_HstNegDet (1 << 17)
+#define GOTGINT_HstnegSucStsChng (1 << 9)
+#define GOTGINT_SesReqSucStsChng (1 << 8)
+#define GOTGINT_SesEndDet (1 << 2)
+
+#define GAHBCFG HSOTG_REG(0x008)
+#define GAHBCFG_PTxFEmpLvl (1 << 8)
+#define GAHBCFG_NPTxFEmpLvl (1 << 7)
+#define GAHBCFG_DMAEn (1 << 5)
+#define GAHBCFG_HBstLen_MASK (0xf << 1)
+#define GAHBCFG_HBstLen_SHIFT (1)
+#define GAHBCFG_HBstLen_Single (0x0 << 1)
+#define GAHBCFG_HBstLen_Incr (0x1 << 1)
+#define GAHBCFG_HBstLen_Incr4 (0x3 << 1)
+#define GAHBCFG_HBstLen_Incr8 (0x5 << 1)
+#define GAHBCFG_HBstLen_Incr16 (0x7 << 1)
+#define GAHBCFG_GlblIntrEn (1 << 0)
+
+#define GUSBCFG HSOTG_REG(0x00C)
+#define GUSBCFG_PHYLPClkSel (1 << 15)
+#define GUSBCFG_HNPCap (1 << 9)
+#define GUSBCFG_SRPCap (1 << 8)
+#define GUSBCFG_PHYIf16 (1 << 3)
+#define GUSBCFG_TOutCal_MASK (0x7 << 0)
+#define GUSBCFG_TOutCal_SHIFT (0)
+#define GUSBCFG_TOutCal_LIMIT (0x7)
+#define GUSBCFG_TOutCal(_x) ((_x) << 0)
+
+#define GRSTCTL HSOTG_REG(0x010)
+
+#define GRSTCTL_AHBIdle (1 << 31)
+#define GRSTCTL_DMAReq (1 << 30)
+#define GRSTCTL_TxFNum_MASK (0x1f << 6)
+#define GRSTCTL_TxFNum_SHIFT (6)
+#define GRSTCTL_TxFNum_LIMIT (0x1f)
+#define GRSTCTL_TxFNum(_x) ((_x) << 6)
+#define GRSTCTL_TxFFlsh (1 << 5)
+#define GRSTCTL_RxFFlsh (1 << 4)
+#define GRSTCTL_INTknQFlsh (1 << 3)
+#define GRSTCTL_FrmCntrRst (1 << 2)
+#define GRSTCTL_HSftRst (1 << 1)
+#define GRSTCTL_CSftRst (1 << 0)
+
+#define GINTSTS HSOTG_REG(0x014)
+#define GINTMSK HSOTG_REG(0x018)
+
+#define GINTSTS_WkUpInt (1 << 31)
+#define GINTSTS_SessReqInt (1 << 30)
+#define GINTSTS_DisconnInt (1 << 29)
+#define GINTSTS_ConIDStsChng (1 << 28)
+#define GINTSTS_PTxFEmp (1 << 26)
+#define GINTSTS_HChInt (1 << 25)
+#define GINTSTS_PrtInt (1 << 24)
+#define GINTSTS_FetSusp (1 << 22)
+#define GINTSTS_incompIP (1 << 21)
+#define GINTSTS_IncomplSOIN (1 << 20)
+#define GINTSTS_OEPInt (1 << 19)
+#define GINTSTS_IEPInt (1 << 18)
+#define GINTSTS_EPMis (1 << 17)
+#define GINTSTS_EOPF (1 << 15)
+#define GINTSTS_ISOutDrop (1 << 14)
+#define GINTSTS_EnumDone (1 << 13)
+#define GINTSTS_USBRst (1 << 12)
+#define GINTSTS_USBSusp (1 << 11)
+#define GINTSTS_ErlySusp (1 << 10)
+#define GINTSTS_GOUTNakEff (1 << 7)
+#define GINTSTS_GINNakEff (1 << 6)
+#define GINTSTS_NPTxFEmp (1 << 5)
+#define GINTSTS_RxFLvl (1 << 4)
+#define GINTSTS_SOF (1 << 3)
+#define GINTSTS_OTGInt (1 << 2)
+#define GINTSTS_ModeMis (1 << 1)
+#define GINTSTS_CurMod_Host (1 << 0)
+
+#define GRXSTSR HSOTG_REG(0x01C)
+#define GRXSTSP HSOTG_REG(0x020)
+
+#define GRXSTS_FN_MASK (0x7f << 25)
+#define GRXSTS_FN_SHIFT (25)
+
+#define GRXSTS_PktSts_MASK (0xf << 17)
+#define GRXSTS_PktSts_SHIFT (17)
+#define GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
+#define GRXSTS_PktSts_OutRX (0x2 << 17)
+#define GRXSTS_PktSts_OutDone (0x3 << 17)
+#define GRXSTS_PktSts_SetupDone (0x4 << 17)
+#define GRXSTS_PktSts_SetupRX (0x6 << 17)
+
+#define GRXSTS_DPID_MASK (0x3 << 15)
+#define GRXSTS_DPID_SHIFT (15)
+#define GRXSTS_ByteCnt_MASK (0x7ff << 4)
+#define GRXSTS_ByteCnt_SHIFT (4)
+#define GRXSTS_EPNum_MASK (0xf << 0)
+#define GRXSTS_EPNum_SHIFT (0)
+
+#define GRXFSIZ HSOTG_REG(0x024)
+
+#define GNPTXFSIZ HSOTG_REG(0x028)
+
+#define GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
+#define GNPTXFSIZ_NPTxFDep_SHIFT (16)
+#define GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
+#define GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
+#define GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
+#define GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
+#define GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
+#define GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
+
+#define GNPTXSTS HSOTG_REG(0x02C)
+
+#define GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
+#define GNPTXSTS_NPtxQTop_SHIFT (24)
+
+#define GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
+#define GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
+#define GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
+
+#define GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
+#define GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
+#define GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
+
+
+#define HPTXFSIZ HSOTG_REG(0x100)
+
+#define DPTXFSIZn(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
+
+#define DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
+#define DPTXFSIZn_DPTxFSize_SHIFT (16)
+#define DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
+#define DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
+#define DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
+
+#define DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
+#define DPTXFSIZn_DPTxFStAddr_SHIFT (0)
/* Device mode registers */
-#define S3C_DCFG S3C_HSOTG_REG(0x800)
-
-#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
-#define S3C_DCFG_EPMisCnt_SHIFT (18)
-#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
-#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
-
-#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
-#define S3C_DCFG_PerFrInt_SHIFT (11)
-#define S3C_DCFG_PerFrInt_LIMIT (0x3)
-#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
-
-#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
-#define S3C_DCFG_DevAddr_SHIFT (4)
-#define S3C_DCFG_DevAddr_LIMIT (0x7f)
-#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
-
-#define S3C_DCFG_NZStsOUTHShk (1 << 2)
-
-#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
-#define S3C_DCFG_DevSpd_SHIFT (0)
-#define S3C_DCFG_DevSpd_HS (0x0 << 0)
-#define S3C_DCFG_DevSpd_FS (0x1 << 0)
-#define S3C_DCFG_DevSpd_LS (0x2 << 0)
-#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
-
-#define S3C_DCTL S3C_HSOTG_REG(0x804)
-
-#define S3C_DCTL_PWROnPrgDone (1 << 11)
-#define S3C_DCTL_CGOUTNak (1 << 10)
-#define S3C_DCTL_SGOUTNak (1 << 9)
-#define S3C_DCTL_CGNPInNAK (1 << 8)
-#define S3C_DCTL_SGNPInNAK (1 << 7)
-#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
-#define S3C_DCTL_TstCtl_SHIFT (4)
-#define S3C_DCTL_GOUTNakSts (1 << 3)
-#define S3C_DCTL_GNPINNakSts (1 << 2)
-#define S3C_DCTL_SftDiscon (1 << 1)
-#define S3C_DCTL_RmtWkUpSig (1 << 0)
-
-#define S3C_DSTS S3C_HSOTG_REG(0x808)
-
-#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
-#define S3C_DSTS_SOFFN_SHIFT (8)
-#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
-#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
-#define S3C_DSTS_ErraticErr (1 << 3)
-#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
-#define S3C_DSTS_EnumSpd_SHIFT (1)
-#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
-#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
-#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
-#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
-
-#define S3C_DSTS_SuspSts (1 << 0)
-
-#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
-
-#define S3C_DIEPMSK_TxFIFOEmpty (1 << 7)
-#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
-#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
-#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
-#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
-#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
-#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
-#define S3C_DIEPMSK_XferComplMsk (1 << 0)
-
-#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
-
-#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
-#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
-#define S3C_DOEPMSK_SetupMsk (1 << 3)
-#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
-#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
-#define S3C_DOEPMSK_XferComplMsk (1 << 0)
-
-#define S3C_DAINT S3C_HSOTG_REG(0x818)
-#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
-
-#define S3C_DAINT_OutEP_SHIFT (16)
-#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
-#define S3C_DAINT_InEP(x) (1 << (x))
-
-#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
-#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
-#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
-#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
-
-#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
-#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
-
-#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
-#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
-#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
-#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
+#define DCFG HSOTG_REG(0x800)
+
+#define DCFG_EPMisCnt_MASK (0x1f << 18)
+#define DCFG_EPMisCnt_SHIFT (18)
+#define DCFG_EPMisCnt_LIMIT (0x1f)
+#define DCFG_EPMisCnt(_x) ((_x) << 18)
+
+#define DCFG_PerFrInt_MASK (0x3 << 11)
+#define DCFG_PerFrInt_SHIFT (11)
+#define DCFG_PerFrInt_LIMIT (0x3)
+#define DCFG_PerFrInt(_x) ((_x) << 11)
+
+#define DCFG_DevAddr_MASK (0x7f << 4)
+#define DCFG_DevAddr_SHIFT (4)
+#define DCFG_DevAddr_LIMIT (0x7f)
+#define DCFG_DevAddr(_x) ((_x) << 4)
+
+#define DCFG_NZStsOUTHShk (1 << 2)
+
+#define DCFG_DevSpd_MASK (0x3 << 0)
+#define DCFG_DevSpd_SHIFT (0)
+#define DCFG_DevSpd_HS (0x0 << 0)
+#define DCFG_DevSpd_FS (0x1 << 0)
+#define DCFG_DevSpd_LS (0x2 << 0)
+#define DCFG_DevSpd_FS48 (0x3 << 0)
+
+#define DCTL HSOTG_REG(0x804)
+
+#define DCTL_PWROnPrgDone (1 << 11)
+#define DCTL_CGOUTNak (1 << 10)
+#define DCTL_SGOUTNak (1 << 9)
+#define DCTL_CGNPInNAK (1 << 8)
+#define DCTL_SGNPInNAK (1 << 7)
+#define DCTL_TstCtl_MASK (0x7 << 4)
+#define DCTL_TstCtl_SHIFT (4)
+#define DCTL_GOUTNakSts (1 << 3)
+#define DCTL_GNPINNakSts (1 << 2)
+#define DCTL_SftDiscon (1 << 1)
+#define DCTL_RmtWkUpSig (1 << 0)
+
+#define DSTS HSOTG_REG(0x808)
+
+#define DSTS_SOFFN_MASK (0x3fff << 8)
+#define DSTS_SOFFN_SHIFT (8)
+#define DSTS_SOFFN_LIMIT (0x3fff)
+#define DSTS_SOFFN(_x) ((_x) << 8)
+#define DSTS_ErraticErr (1 << 3)
+#define DSTS_EnumSpd_MASK (0x3 << 1)
+#define DSTS_EnumSpd_SHIFT (1)
+#define DSTS_EnumSpd_HS (0x0 << 1)
+#define DSTS_EnumSpd_FS (0x1 << 1)
+#define DSTS_EnumSpd_LS (0x2 << 1)
+#define DSTS_EnumSpd_FS48 (0x3 << 1)
+
+#define DSTS_SuspSts (1 << 0)
+
+#define DIEPMSK HSOTG_REG(0x810)
+
+#define DIEPMSK_TxFIFOEmpty (1 << 7)
+#define DIEPMSK_INEPNakEffMsk (1 << 6)
+#define DIEPMSK_INTknEPMisMsk (1 << 5)
+#define DIEPMSK_INTknTXFEmpMsk (1 << 4)
+#define DIEPMSK_TimeOUTMsk (1 << 3)
+#define DIEPMSK_AHBErrMsk (1 << 2)
+#define DIEPMSK_EPDisbldMsk (1 << 1)
+#define DIEPMSK_XferComplMsk (1 << 0)
+
+#define DOEPMSK HSOTG_REG(0x814)
+
+#define DOEPMSK_Back2BackSetup (1 << 6)
+#define DOEPMSK_OUTTknEPdisMsk (1 << 4)
+#define DOEPMSK_SetupMsk (1 << 3)
+#define DOEPMSK_AHBErrMsk (1 << 2)
+#define DOEPMSK_EPDisbldMsk (1 << 1)
+#define DOEPMSK_XferComplMsk (1 << 0)
+
+#define DAINT HSOTG_REG(0x818)
+#define DAINTMSK HSOTG_REG(0x81C)
+
+#define DAINT_OutEP_SHIFT (16)
+#define DAINT_OutEP(x) (1 << ((x) + 16))
+#define DAINT_InEP(x) (1 << (x))
+
+#define DTKNQR1 HSOTG_REG(0x820)
+#define DTKNQR2 HSOTG_REG(0x824)
+#define DTKNQR3 HSOTG_REG(0x830)
+#define DTKNQR4 HSOTG_REG(0x834)
+
+#define DVBUSDIS HSOTG_REG(0x828)
+#define DVBUSPULSE HSOTG_REG(0x82C)
+
+#define DIEPCTL0 HSOTG_REG(0x900)
+#define DOEPCTL0 HSOTG_REG(0xB00)
+#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
+#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
/* EP0 specialness:
* bits[29..28] - reserved (no SetD0PID, SetD1PID)
* bits[25..22] - should always be zero, this isn't a periodic endpoint
* bits[10..0] - MPS setting differenct for EP0
-*/
-#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
-#define S3C_D0EPCTL_MPS_SHIFT (0)
-#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
-#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
-#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
-#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
-
-#define S3C_DxEPCTL_EPEna (1 << 31)
-#define S3C_DxEPCTL_EPDis (1 << 30)
-#define S3C_DxEPCTL_SetD1PID (1 << 29)
-#define S3C_DxEPCTL_SetOddFr (1 << 29)
-#define S3C_DxEPCTL_SetD0PID (1 << 28)
-#define S3C_DxEPCTL_SetEvenFr (1 << 28)
-#define S3C_DxEPCTL_SNAK (1 << 27)
-#define S3C_DxEPCTL_CNAK (1 << 26)
-#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
-#define S3C_DxEPCTL_TxFNum_SHIFT (22)
-#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
-#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
-
-#define S3C_DxEPCTL_Stall (1 << 21)
-#define S3C_DxEPCTL_Snp (1 << 20)
-#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
-#define S3C_DxEPCTL_EPType_SHIFT (18)
-#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
-#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
-#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
-#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
-
-#define S3C_DxEPCTL_NAKsts (1 << 17)
-#define S3C_DxEPCTL_DPID (1 << 16)
-#define S3C_DxEPCTL_EOFrNum (1 << 16)
-#define S3C_DxEPCTL_USBActEp (1 << 15)
-#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
-#define S3C_DxEPCTL_NextEp_SHIFT (11)
-#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
-#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
-
-#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
-#define S3C_DxEPCTL_MPS_SHIFT (0)
-#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
-#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
-
-#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
-#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
-
-#define S3C_DxEPINT_INEPNakEff (1 << 6)
-#define S3C_DxEPINT_Back2BackSetup (1 << 6)
-#define S3C_DxEPINT_INTknEPMis (1 << 5)
-#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
-#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
-#define S3C_DxEPINT_Timeout (1 << 3)
-#define S3C_DxEPINT_Setup (1 << 3)
-#define S3C_DxEPINT_AHBErr (1 << 2)
-#define S3C_DxEPINT_EPDisbld (1 << 1)
-#define S3C_DxEPINT_XferCompl (1 << 0)
-
-#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
-
-#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
-#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
-#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
-#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
-
-#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
-#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
-#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
-#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
-
-
-#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
-#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
-#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
-#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
-#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
-
-#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
-#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
-#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
-
-#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
-#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
-
-#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
-#define S3C_DxEPTSIZ_MC_SHIFT (29)
-#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
-#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
-
-#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
-#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
-#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
-#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
-#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
-
-#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
-#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
-#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
-#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
-#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
-
-
-#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
-#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
-#define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20))
-
-#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
-
-#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
+ */
+#define D0EPCTL_MPS_MASK (0x3 << 0)
+#define D0EPCTL_MPS_SHIFT (0)
+#define D0EPCTL_MPS_64 (0x0 << 0)
+#define D0EPCTL_MPS_32 (0x1 << 0)
+#define D0EPCTL_MPS_16 (0x2 << 0)
+#define D0EPCTL_MPS_8 (0x3 << 0)
+
+#define DxEPCTL_EPEna (1 << 31)
+#define DxEPCTL_EPDis (1 << 30)
+#define DxEPCTL_SetD1PID (1 << 29)
+#define DxEPCTL_SetOddFr (1 << 29)
+#define DxEPCTL_SetD0PID (1 << 28)
+#define DxEPCTL_SetEvenFr (1 << 28)
+#define DxEPCTL_SNAK (1 << 27)
+#define DxEPCTL_CNAK (1 << 26)
+#define DxEPCTL_TxFNum_MASK (0xf << 22)
+#define DxEPCTL_TxFNum_SHIFT (22)
+#define DxEPCTL_TxFNum_LIMIT (0xf)
+#define DxEPCTL_TxFNum(_x) ((_x) << 22)
+
+#define DxEPCTL_Stall (1 << 21)
+#define DxEPCTL_Snp (1 << 20)
+#define DxEPCTL_EPType_MASK (0x3 << 18)
+#define DxEPCTL_EPType_SHIFT (18)
+#define DxEPCTL_EPType_Control (0x0 << 18)
+#define DxEPCTL_EPType_Iso (0x1 << 18)
+#define DxEPCTL_EPType_Bulk (0x2 << 18)
+#define DxEPCTL_EPType_Intterupt (0x3 << 18)
+
+#define DxEPCTL_NAKsts (1 << 17)
+#define DxEPCTL_DPID (1 << 16)
+#define DxEPCTL_EOFrNum (1 << 16)
+#define DxEPCTL_USBActEp (1 << 15)
+#define DxEPCTL_NextEp_MASK (0xf << 11)
+#define DxEPCTL_NextEp_SHIFT (11)
+#define DxEPCTL_NextEp_LIMIT (0xf)
+#define DxEPCTL_NextEp(_x) ((_x) << 11)
+
+#define DxEPCTL_MPS_MASK (0x7ff << 0)
+#define DxEPCTL_MPS_SHIFT (0)
+#define DxEPCTL_MPS_LIMIT (0x7ff)
+#define DxEPCTL_MPS(_x) ((_x) << 0)
+
+#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
+#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
+
+#define DxEPINT_INEPNakEff (1 << 6)
+#define DxEPINT_Back2BackSetup (1 << 6)
+#define DxEPINT_INTknEPMis (1 << 5)
+#define DxEPINT_INTknTXFEmp (1 << 4)
+#define DxEPINT_OUTTknEPdis (1 << 4)
+#define DxEPINT_Timeout (1 << 3)
+#define DxEPINT_Setup (1 << 3)
+#define DxEPINT_AHBErr (1 << 2)
+#define DxEPINT_EPDisbld (1 << 1)
+#define DxEPINT_XferCompl (1 << 0)
+
+#define DIEPTSIZ0 HSOTG_REG(0x910)
+
+#define DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
+#define DIEPTSIZ0_PktCnt_SHIFT (19)
+#define DIEPTSIZ0_PktCnt_LIMIT (0x3)
+#define DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
+
+#define DIEPTSIZ0_XferSize_MASK (0x7f << 0)
+#define DIEPTSIZ0_XferSize_SHIFT (0)
+#define DIEPTSIZ0_XferSize_LIMIT (0x7f)
+#define DIEPTSIZ0_XferSize(_x) ((_x) << 0)
+
+#define DOEPTSIZ0 HSOTG_REG(0xB10)
+#define DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
+#define DOEPTSIZ0_SUPCnt_SHIFT (29)
+#define DOEPTSIZ0_SUPCnt_LIMIT (0x3)
+#define DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
+
+#define DOEPTSIZ0_PktCnt (1 << 19)
+#define DOEPTSIZ0_XferSize_MASK (0x7f << 0)
+#define DOEPTSIZ0_XferSize_SHIFT (0)
+
+#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
+#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
+
+#define DxEPTSIZ_MC_MASK (0x3 << 29)
+#define DxEPTSIZ_MC_SHIFT (29)
+#define DxEPTSIZ_MC_LIMIT (0x3)
+#define DxEPTSIZ_MC(_x) ((_x) << 29)
+
+#define DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
+#define DxEPTSIZ_PktCnt_SHIFT (19)
+#define DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
+#define DxEPTSIZ_PktCnt_LIMIT (0x3ff)
+#define DxEPTSIZ_PktCnt(_x) ((_x) << 19)
+
+#define DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
+#define DxEPTSIZ_XferSize_SHIFT (0)
+#define DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
+#define DxEPTSIZ_XferSize_LIMIT (0x7ffff)
+#define DxEPTSIZ_XferSize(_x) ((_x) << 0)
+
+#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
+#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
+#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
+
+#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
+
+#endif /* __REGS_USB_HSOTG_H */
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff