intel drivers: repair missing flush operations
authorJesse Brandeburg <jesse.brandeburg@intel.com>
Wed, 20 Jul 2011 00:56:21 +0000 (00:56 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Thu, 4 Aug 2011 11:59:07 +0000 (04:59 -0700)
after review of all intel drivers, found several instances where
drivers had the incorrect pattern of:
memory mapped write();
delay();

which should always be:
memory mapped write();
write flush(); /* aka memory mapped read */
delay();

explanation:
The reason for including the flush is that writes can be held
(posted) in PCI/PCIe bridges, but the read always has to complete
synchronously and therefore has to flush all pending writes to a
device.  If a write is held and followed by a delay, the delay
means nothing because the write may not have reached hardware
(maybe even not until the next read)

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
18 files changed:
drivers/net/e1000/e1000_ethtool.c
drivers/net/e1000/e1000_hw.c
drivers/net/e1000e/es2lan.c
drivers/net/e1000e/ethtool.c
drivers/net/e1000e/ich8lan.c
drivers/net/e1000e/lib.c
drivers/net/e1000e/phy.c
drivers/net/igb/e1000_nvm.c
drivers/net/igb/igb_ethtool.c
drivers/net/igb/igb_main.c
drivers/net/igbvf/netdev.c
drivers/net/ixgb/ixgb_ee.c
drivers/net/ixgb/ixgb_hw.c
drivers/net/ixgbe/ixgbe_common.c
drivers/net/ixgbe/ixgbe_ethtool.c
drivers/net/ixgbe/ixgbe_main.c
drivers/net/ixgbe/ixgbe_phy.c
drivers/net/ixgbe/ixgbe_x540.c

index c5f0f04219f3a3040d04d6a34f8e311b1ad22d29..5548d464261a6173fc1be5588960d858b33e8592 100644 (file)
@@ -838,6 +838,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       E1000_WRITE_FLUSH();
        msleep(10);
 
        /* Test each interrupt */
@@ -856,6 +857,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                        adapter->test_icr = 0;
                        ew32(IMC, mask);
                        ew32(ICS, mask);
+                       E1000_WRITE_FLUSH();
                        msleep(10);
 
                        if (adapter->test_icr & mask) {
@@ -873,6 +875,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                adapter->test_icr = 0;
                ew32(IMS, mask);
                ew32(ICS, mask);
+               E1000_WRITE_FLUSH();
                msleep(10);
 
                if (!(adapter->test_icr & mask)) {
@@ -890,6 +893,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                        adapter->test_icr = 0;
                        ew32(IMC, ~mask & 0x00007FFF);
                        ew32(ICS, ~mask & 0x00007FFF);
+                       E1000_WRITE_FLUSH();
                        msleep(10);
 
                        if (adapter->test_icr) {
@@ -901,6 +905,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       E1000_WRITE_FLUSH();
        msleep(10);
 
        /* Unhook test interrupt handler */
@@ -1394,6 +1399,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
                        if (unlikely(++k == txdr->count)) k = 0;
                }
                ew32(TDT, k);
+               E1000_WRITE_FLUSH();
                msleep(200);
                time = jiffies; /* set the start time for the receive */
                good_cnt = 0;
index 1698622af434495d08fb07888e26bad4d6d41064..8545c7aa93eb674639b6d68dff2e77cb9a7e7d75 100644 (file)
@@ -446,6 +446,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
        /* Must reset the PHY before resetting the MAC */
        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
                ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
+               E1000_WRITE_FLUSH();
                msleep(5);
        }
 
@@ -3752,6 +3753,7 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
                udelay(1);
        }
 
@@ -3824,6 +3826,7 @@ static void e1000_release_eeprom(struct e1000_hw *hw)
                eecd &= ~E1000_EECD_SK; /* Lower SCK */
 
                ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
 
                udelay(hw->eeprom.delay_usec);
        } else if (hw->eeprom.type == e1000_eeprom_microwire) {
index c0ecb2d9fdb7abc1a47a240af1c5698f4e1b3edc..e4f42257c24c9743c5d6b135694930284f7b1f62 100644 (file)
@@ -1313,6 +1313,7 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
@@ -1347,6 +1348,7 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | data;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
index cb1a3623253e8704f6d724a53b8ab8ad896eaa6a..72756e4e644863044767f70a67a28f607197ad09 100644 (file)
@@ -964,6 +964,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       e1e_flush();
        usleep_range(10000, 20000);
 
        /* Test each interrupt */
@@ -996,6 +997,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                        adapter->test_icr = 0;
                        ew32(IMC, mask);
                        ew32(ICS, mask);
+                       e1e_flush();
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr & mask) {
@@ -1014,6 +1016,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                adapter->test_icr = 0;
                ew32(IMS, mask);
                ew32(ICS, mask);
+               e1e_flush();
                usleep_range(10000, 20000);
 
                if (!(adapter->test_icr & mask)) {
@@ -1032,6 +1035,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                        adapter->test_icr = 0;
                        ew32(IMC, ~mask & 0x00007FFF);
                        ew32(ICS, ~mask & 0x00007FFF);
+                       e1e_flush();
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr) {
@@ -1043,6 +1047,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       e1e_flush();
        usleep_range(10000, 20000);
 
        /* Unhook test interrupt handler */
@@ -1276,6 +1281,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
                             E1000_CTRL_FD);     /* Force Duplex to FULL */
 
                ew32(CTRL, ctrl_reg);
+               e1e_flush();
                udelay(500);
 
                return 0;
@@ -1418,6 +1424,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
         */
 #define E1000_SERDES_LB_ON 0x410
        ew32(SCTL, E1000_SERDES_LB_ON);
+       e1e_flush();
        usleep_range(10000, 20000);
 
        return 0;
@@ -1513,6 +1520,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
                    hw->phy.media_type == e1000_media_type_internal_serdes) {
 #define E1000_SERDES_LB_OFF 0x400
                        ew32(SCTL, E1000_SERDES_LB_OFF);
+                       e1e_flush();
                        usleep_range(10000, 20000);
                        break;
                }
@@ -1592,6 +1600,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
                                k = 0;
                }
                ew32(TDT, k);
+               e1e_flush();
                msleep(200);
                time = jiffies; /* set the start time for the receive */
                good_cnt = 0;
index c1752124f3cdf2572e89b48db537a26783c4b33d..f7a75c1531ad21d175aa49b2381ad990008b97df 100644 (file)
@@ -283,6 +283,7 @@ static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
        ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
        ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
        ew32(CTRL, ctrl);
+       e1e_flush();
        udelay(10);
        ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
        ew32(CTRL, ctrl);
@@ -1230,9 +1231,11 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
        ew32(CTRL, reg);
 
        ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+       e1e_flush();
        udelay(20);
        ew32(CTRL, ctrl_reg);
        ew32(CTRL_EXT, ctrl_ext);
+       e1e_flush();
        udelay(20);
 
 out:
@@ -3090,6 +3093,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        ret_val = e1000_acquire_swflag_ich8lan(hw);
        e_dbg("Issuing a global reset to ich8lan\n");
        ew32(CTRL, (ctrl | E1000_CTRL_RST));
+       /* cannot issue a flush here because it hangs the hardware */
        msleep(20);
 
        if (!ret_val)
index 65580b40594207a2aac7a663da5bc0c105a67cb2..7898a67d6505478036e19e790ebeb1a1f2295445 100644 (file)
@@ -1986,6 +1986,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                ew32(EECD, eecd);
+               e1e_flush();
                udelay(1);
 
                /*
index 2a6ee13285b19bf49e53485d03da830e1ef0cbe7..8666476cb9be4d723a3dc07f5feb66230aa86fb5 100644 (file)
@@ -537,6 +537,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
@@ -609,6 +610,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | data;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
index 7dcd65cede562d4cf47d83d4f4c2d742cb5ae241..40407124e7222090c364aa960cfc303115a9571f 100644 (file)
@@ -285,6 +285,7 @@ static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                wr32(E1000_EECD, eecd);
+               wrfl();
                udelay(1);
                timeout = NVM_MAX_RETRY_SPI;
 
index ff244ce803ceb51d95d033bcdbdbe85b47d4a499..414b0225be897fcaa51f19d9f417dd4a5140f956 100644 (file)
@@ -1225,6 +1225,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        wr32(E1000_IMC, ~0);
+       wrfl();
        msleep(10);
 
        /* Define all writable bits for ICS */
@@ -1268,6 +1269,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
 
                        wr32(E1000_IMC, mask);
                        wr32(E1000_ICS, mask);
+                       wrfl();
                        msleep(10);
 
                        if (adapter->test_icr & mask) {
@@ -1289,6 +1291,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
 
                wr32(E1000_IMS, mask);
                wr32(E1000_ICS, mask);
+               wrfl();
                msleep(10);
 
                if (!(adapter->test_icr & mask)) {
@@ -1310,6 +1313,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
 
                        wr32(E1000_IMC, ~mask);
                        wr32(E1000_ICS, ~mask);
+                       wrfl();
                        msleep(10);
 
                        if (adapter->test_icr & mask) {
@@ -1321,6 +1325,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        wr32(E1000_IMC, ~0);
+       wrfl();
        msleep(10);
 
        /* Unhook test interrupt handler */
index dc599059512aa6ff9fb249225108130f988898e0..ae3937e8cdeff9a17594d9a5a7ca7f37d62ae1c8 100644 (file)
@@ -1052,6 +1052,7 @@ msi_only:
                kfree(adapter->vf_data);
                adapter->vf_data = NULL;
                wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
+               wrfl();
                msleep(100);
                dev_info(&adapter->pdev->dev, "IOV Disabled\n");
        }
@@ -2198,6 +2199,7 @@ static void __devexit igb_remove(struct pci_dev *pdev)
                kfree(adapter->vf_data);
                adapter->vf_data = NULL;
                wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
+               wrfl();
                msleep(100);
                dev_info(&pdev->dev, "IOV Disabled\n");
        }
index 1330c8e932da3683fa1e3680e1979d0ae146ba11..40ed066e3ef48177cca4725405c53b78cd6af786 100644 (file)
@@ -1226,6 +1226,7 @@ static void igbvf_configure_tx(struct igbvf_adapter *adapter)
        /* disable transmits */
        txdctl = er32(TXDCTL(0));
        ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
+       e1e_flush();
        msleep(10);
 
        /* Setup the HW Tx Head and Tail descriptor pointers */
@@ -1306,6 +1307,7 @@ static void igbvf_configure_rx(struct igbvf_adapter *adapter)
        /* disable receives */
        rxdctl = er32(RXDCTL(0));
        ew32(RXDCTL(0), rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
+       e1e_flush();
        msleep(10);
 
        rdlen = rx_ring->count * sizeof(union e1000_adv_rx_desc);
index c982ab9f9005179b1910a75f45404442dfb9fec5..38b362b678572e45f8b316b7cc47e978f9091189 100644 (file)
@@ -57,6 +57,7 @@ ixgb_raise_clock(struct ixgb_hw *hw,
         */
        *eecd_reg = *eecd_reg | IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
@@ -75,6 +76,7 @@ ixgb_lower_clock(struct ixgb_hw *hw,
         */
        *eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
@@ -112,6 +114,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
                        eecd_reg |= IXGB_EECD_DI;
 
                IXGB_WRITE_REG(hw, EECD, eecd_reg);
+               IXGB_WRITE_FLUSH(hw);
 
                udelay(50);
 
@@ -206,21 +209,25 @@ ixgb_standby_eeprom(struct ixgb_hw *hw)
        /*  Deselect EEPROM  */
        eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Clock high  */
        eecd_reg |= IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Select EEPROM  */
        eecd_reg |= IXGB_EECD_CS;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Clock low  */
        eecd_reg &= ~IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
@@ -239,11 +246,13 @@ ixgb_clock_eeprom(struct ixgb_hw *hw)
        /*  Rising edge of clock  */
        eecd_reg |= IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Falling edge of clock  */
        eecd_reg &= ~IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
index 6cb2e42ff4c135d2bf171b2b5e2e6ec57da8f271..3d61a9e4faf761e619d61001bc3ce83f21211800 100644 (file)
@@ -149,6 +149,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
         */
        IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
        IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
+       IXGB_WRITE_FLUSH(hw);
        msleep(IXGB_DELAY_BEFORE_RESET);
 
        /* Issue a global reset to the MAC.  This will reset the chip's
@@ -1220,6 +1221,7 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw)
        ctrl &= ~IXGB_CTRL0_SDP2;
        ctrl |= IXGB_CTRL0_SDP3;
        IXGB_WRITE_REG(hw, CTRL0, ctrl);
+       IXGB_WRITE_FLUSH(hw);
 
        /* SerDes needs extra delay */
        msleep(IXGB_SUN_PHY_RESET_DELAY);
index 777051f54e532eb5f97dea9c22d2a26b7c66b13f..fc1375f26fe56a5991f434ab70a1069fb01d01a8 100644 (file)
@@ -2632,6 +2632,7 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
                autoc_reg |= IXGBE_AUTOC_AN_RESTART;
                autoc_reg |= IXGBE_AUTOC_FLU;
                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
+               IXGBE_WRITE_FLUSH(hw);
                usleep_range(10000, 20000);
        }
 
index dc649553a0a65a837e4053e57c0ab42b66af6f32..82d4244c6e1050a416dfe2a939ca7c15d095a125 100644 (file)
@@ -1378,6 +1378,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+       IXGBE_WRITE_FLUSH(&adapter->hw);
        usleep_range(10000, 20000);
 
        /* Test each interrupt */
@@ -1398,6 +1399,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
                                        ~mask & 0x00007FFF);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                        ~mask & 0x00007FFF);
+                       IXGBE_WRITE_FLUSH(&adapter->hw);
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr & mask) {
@@ -1415,6 +1417,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
                adapter->test_icr = 0;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
+               IXGBE_WRITE_FLUSH(&adapter->hw);
                usleep_range(10000, 20000);
 
                if (!(adapter->test_icr &mask)) {
@@ -1435,6 +1438,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
                                        ~mask & 0x00007FFF);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                        ~mask & 0x00007FFF);
+                       IXGBE_WRITE_FLUSH(&adapter->hw);
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr) {
@@ -1446,6 +1450,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
 
        /* Disable all the interrupts */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+       IXGBE_WRITE_FLUSH(&adapter->hw);
        usleep_range(10000, 20000);
 
        /* Unhook test interrupt handler */
index 1be617545dc9bdbbfb9a39b0be78c9a9c967337c..26b132bca43eae2ee50df30e5579b65e6911710e 100644 (file)
@@ -184,6 +184,7 @@ static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
        vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
        vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
        IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* take a breather then clean up driver data */
        msleep(100);
index 735f686c3b36605eff5abc5573a05ef87dbe17d5..f7ca3511b9fede0657bc69141b84b02d000c72c6 100644 (file)
@@ -1585,6 +1585,7 @@ static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
        *i2cctl |= IXGBE_I2C_CLK_OUT;
 
        IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* SCL rise time (1000ns) */
        udelay(IXGBE_I2C_T_RISE);
@@ -1605,6 +1606,7 @@ static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
        *i2cctl &= ~IXGBE_I2C_CLK_OUT;
 
        IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* SCL fall time (300ns) */
        udelay(IXGBE_I2C_T_FALL);
@@ -1628,6 +1630,7 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
                *i2cctl &= ~IXGBE_I2C_DATA_OUT;
 
        IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
        udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
index bec30ed91adc9a1059305b9bcea4445bd919601f..2696c78e9f46c65a4971caadbfc0ace41cb65571 100644 (file)
@@ -162,6 +162,7 @@ mac_reset_top:
        ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
        ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
        IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
+       IXGBE_WRITE_FLUSH(hw);
 
        msleep(50);