# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
+obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
-static struct clk osc_ck;
+DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
-static const struct clk_ops osc_ck_ops = {
- .recalc_rate = &omap2_osc_clk_recalc,
-};
+DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
-static struct clk_hw_omap osc_ck_hw = {
- .hw = {
- .clk = &osc_ck,
- },
-};
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0);
-static struct clk osc_ck = {
- .name = "osc_ck",
- .ops = &osc_ck_ops,
- .hw = &osc_ck_hw.hw,
- .flags = CLK_IS_ROOT,
+/* 26M ck is a dummy, added to fill the hole in the aplls_clkin parent list */
+static const char *aplls_clkin_ck_parent_names[] = {
+ "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck",
};
+DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT,
+ OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL);
+
DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-static struct clk sys_ck;
+DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck,
+ 0x0, 2, 1);
-static const char *sys_ck_parent_names[] = {
- "osc_ck",
+static const char *osc_ck_parent_names[] = {
+ "aplls_clkin_ck", "aplls_clkin_x2_ck",
};
-static const struct clk_ops sys_ck_ops = {
- .init = &omap2_init_clk_clkdm,
- .recalc_rate = &omap2xxx_sys_clk_recalc,
-};
+DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0,
+ OMAP2420_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
+ OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
-DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2420_PRCM_CLKSRC_CTRL,
+ OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
static struct dpll_data dpll_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck),
+ CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck),
+ CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "alt_ck", &alt_ck),
int __init omap2420_clk_init(void)
{
- prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_242X;
rate_table = omap2420_rate_table;
DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
-static struct clk osc_ck;
+DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
-static const struct clk_ops osc_ck_ops = {
- .enable = &omap2_enable_osc_ck,
- .disable = omap2_disable_osc_ck,
- .recalc_rate = &omap2_osc_clk_recalc,
-};
+DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
-static struct clk_hw_omap osc_ck_hw = {
- .hw = {
- .clk = &osc_ck,
- },
-};
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-static struct clk osc_ck = {
- .name = "osc_ck",
- .ops = &osc_ck_ops,
- .hw = &osc_ck_hw.hw,
- .flags = CLK_IS_ROOT,
+DEFINE_CLK_FIXED_RATE(virt_26m_ck, CLK_IS_ROOT, 26000000, 0x0);
+
+/* 26M ck is a dummy, added to filla hole in the aplls_clkin parent list */
+static const char *aplls_clkin_ck_parent_names[] = {
+ "virt_19200000_ck", "virt_26m_ck", "virt_13m_ck", "virt_12m_ck",
};
+DEFINE_CLK_MUX(aplls_clkin_ck, aplls_clkin_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP24XX_APLLS_CLKIN_SHIFT,
+ OMAP24XX_APLLS_CLKIN_WIDTH, 0x0, NULL);
+
DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-static struct clk sys_ck;
+DEFINE_CLK_FIXED_FACTOR(aplls_clkin_x2_ck, "aplls_clkin_ck", &aplls_clkin_ck,
+ 0x0, 2, 1);
-static const char *sys_ck_parent_names[] = {
- "osc_ck",
+static const char *osc_ck_parent_names[] = {
+ "aplls_clkin_ck", "aplls_clkin_x2_ck",
};
-static const struct clk_ops sys_ck_ops = {
- .init = &omap2_init_clk_clkdm,
- .recalc_rate = &omap2xxx_sys_clk_recalc,
-};
+DEFINE_CLK_MUX(osc_ck, osc_ck_parent_names, NULL, 0x0,
+ OMAP2430_PRCM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
+ OMAP_SYSCLKDIV_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
-DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+DEFINE_CLK_DIVIDER(sys_ck, "osc_ck", &osc_ck, 0x0, OMAP2430_PRCM_CLKSRC_CTRL,
+ OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
static struct dpll_data dpll_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clkdm_name = "mdm_clkdm",
};
-DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
+static const char *mdm_osc_ck_parent_names[] = {
+ "osc_ck",
+};
+
+DEFINE_STRUCT_CLK(mdm_osc_ck, mdm_osc_ck_parent_names, aes_ick_ops);
static struct clk mmchs1_fck;
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck),
+ CLK(NULL, "aplls_clkin_ck", &aplls_clkin_ck),
+ CLK(NULL, "aplls_clkin_x2_ck", &aplls_clkin_x2_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK("twl", "fck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
int __init omap2430_clk_init(void)
{
- prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_243X;
rate_table = omap2430_rate_table;
+++ /dev/null
-/*
- * OMAP2xxx osc_clk-specific clock code
- *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "clock2xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * XXX This does not actually enable the osc_ck, since the osc_ck must
- * be running for this function to be called. Instead, this function
- * is used to disable an autoidle mode on the osc_ck. The existing
- * clk_enable/clk_disable()-based usecounting for osc_ck should be
- * replaced with autoidle-based usecounting.
- */
-int omap2_enable_osc_ck(struct clk_hw *clk)
-{
- u32 pcc;
-
- pcc = readl_relaxed(prcm_clksrc_ctrl);
-
- writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-
- return 0;
-}
-
-/*
- * XXX This does not actually disable the osc_ck, since doing so would
- * immediately halt the system. Instead, this function is used to
- * enable an autoidle mode on the osc_ck. The existing
- * clk_enable/clk_disable()-based usecounting for osc_ck should be
- * replaced with autoidle-based usecounting.
- */
-void omap2_disable_osc_ck(struct clk_hw *clk)
-{
- u32 pcc;
-
- pcc = readl_relaxed(prcm_clksrc_ctrl);
-
- writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-}
-
-unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
- unsigned long parent_rate)
-{
- return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
-}
+++ /dev/null
-/*
- * OMAP2xxx sys_clk-specific clock code
- *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "clock2xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-void __iomem *prcm_clksrc_ctrl;
-
-u32 omap2xxx_get_sysclkdiv(void)
-{
- u32 div;
-
- div = readl_relaxed(prcm_clksrc_ctrl);
- div &= OMAP_SYSCLKDIV_MASK;
- div >>= OMAP_SYSCLKDIV_SHIFT;
-
- return div;
-}
-
-unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
- unsigned long parent_rate)
-{
- return parent_rate / omap2xxx_get_sysclkdiv();
-}
#define omap2430_clk_init() do { } while(0)
#endif
-extern void __iomem *prcm_clksrc_ctrl;
-
extern struct clk_hw *dclk_hw;
int omap2_enable_osc_ck(struct clk_hw *hw);
void omap2_disable_osc_ck(struct clk_hw *hw);
#define OMAP24XX_AUTO_DPLL_SHIFT 0
#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
#define OMAP24XX_APLLS_CLKIN_SHIFT 23
+#define OMAP24XX_APLLS_CLKIN_WIDTH 3
#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
/* Enable wake-up events */
omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
WKUP_MOD, PM_WKEN);
+
+ /* Enable SYS_CLKEN control when all domains idle */
+ omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
+ OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
}
int __init omap2_pm_init(void)
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff