# define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1
#endif
-#define OMAP1_MBOX_BASE IO_ADDRESS(OMAP16XX_MAILBOX_BASE)
+#define OMAP1_MBOX_BASE OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE)
static struct resource mbox_resources[] = {
{
* Register and offset definitions to be used in PM assembler code
* ----------------------------------------------------------------------------
*/
-#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
+#define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
#define ARM_IDLECT1_ASM_OFFSET 0x04
#define ARM_IDLECT2_ASM_OFFSET 0x08
-#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
+#define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
#define EMIFS_CONFIG_ASM_OFFSET 0x0c
#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
static struct plat_serial8250_port serial_platform_data[] = {
{
- .membase = IO_ADDRESS(OMAP_UART1_BASE),
+ .membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
.mapbase = OMAP_UART1_BASE,
.irq = INT_UART1,
.flags = UPF_BOOT_AUTOCONF,
.uartclk = OMAP16XX_BASE_BAUD * 16,
},
{
- .membase = IO_ADDRESS(OMAP_UART2_BASE),
+ .membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
.mapbase = OMAP_UART2_BASE,
.irq = INT_UART2,
.flags = UPF_BOOT_AUTOCONF,
.uartclk = OMAP16XX_BASE_BAUD * 16,
},
{
- .membase = IO_ADDRESS(OMAP_UART3_BASE),
+ .membase = OMAP1_IO_ADDRESS(OMAP_UART3_BASE),
.mapbase = OMAP_UART3_BASE,
.irq = INT_UART3,
.flags = UPF_BOOT_AUTOCONF,
ENTRY(omap1_sram_reprogram_clock)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
- mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
- orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000
- orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00
+ mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
+ orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
+ orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
- mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
- orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
- orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
+ mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
+ orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
+ orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
tst r0, #1 << 4 @ want lock mode?
beq newck @ nope
u32 read_tim; /* READ_TIM, R */
} omap_mpu_timer_regs_t;
-#define omap_mpu_timer_base(n) \
-((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
+#define omap_mpu_timer_base(n) \
+((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
(n)*OMAP_MPU_TIMER_OFFSET))
static inline unsigned long omap_mpu_timer_read(int nr)
static void __init gic_init_irq(void)
{
- gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
- gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+ gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
+ gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
}
static void __init omap_4430sdp_init_irq(void)
#include "prcm-common.h"
#define OMAP2420_CM_REGADDR(module, reg) \
- IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+ OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
#define OMAP2430_CM_REGADDR(module, reg) \
- IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+ OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg) \
- IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+ OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
/*
* Architecture-specific global CM registers
* for us: do so
*/
- gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+ gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
/*
* Synchronise with the boot thread.
regs[reg_count++].val = __raw_readl(reg)
#define DUMP_INTC_REG(reg, off) \
regs[reg_count].name = #reg; \
- regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
+ regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off)))
void omap2_pm_dump(int mode, int resume, unsigned int us)
{
#include "prcm-common.h"
#define OMAP2420_PRM_REGADDR(module, reg) \
- IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+ OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
#define OMAP2430_PRM_REGADDR(module, reg) \
- IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+ OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
#define OMAP34XX_PRM_REGADDR(module, reg) \
- IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+ OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
/*
* Architecture-specific global PRM registers
return __raw_readl(OMAP_SMS_REGADDR(reg));
}
#else
-#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
-#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
-#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
#endif /* __ASSEMBLER__ */
#endif
static struct plat_serial8250_port serial_platform_data0[] = {
{
- .membase = IO_ADDRESS(OMAP_UART1_BASE),
+ .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
.mapbase = OMAP_UART1_BASE,
.irq = 72,
.flags = UPF_BOOT_AUTOCONF,
static struct plat_serial8250_port serial_platform_data1[] = {
{
- .membase = IO_ADDRESS(OMAP_UART2_BASE),
+ .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
.mapbase = OMAP_UART2_BASE,
.irq = 73,
.flags = UPF_BOOT_AUTOCONF,
static struct plat_serial8250_port serial_platform_data2[] = {
{
- .membase = IO_ADDRESS(OMAP_UART3_BASE),
+ .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
.mapbase = OMAP_UART3_BASE,
.irq = 74,
.flags = UPF_BOOT_AUTOCONF,
prcm_mask_val:
.word 0xFFFF3FFC
omap242x_sdi_timer_32ksynct_cr:
- .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+ .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_ddr_init_sz)
.word . - omap242x_sram_ddr_init
ddr_prcm_mask_val:
.word 0xFFFF3FFC
omap242x_srs_timer_32ksynct:
- .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+ .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_reprogram_sdrc_sz)
.word . - omap242x_sram_reprogram_sdrc
prcm_mask_val:
.word 0xFFFF3FFC
omap243x_sdi_timer_32ksynct_cr:
- .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
+ .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
ENTRY(omap243x_sram_ddr_init_sz)
.word . - omap243x_sram_ddr_init
ddr_prcm_mask_val:
.word 0xFFFF3FFC
omap243x_srs_timer_32ksynct:
- .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
+ .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
ENTRY(omap243x_sram_reprogram_sdrc_sz)
.word . - omap243x_sram_reprogram_sdrc
static void __init omap2_gp_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
- twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
+ twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
#endif
omap_dm_timer_init();
int ch, r;
if (cpu_class_is_omap1()) {
- omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
+ omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap24xx()) {
- omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
+ omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap34xx()) {
- omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
+ omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap44xx()) {
- omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
+ omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else {
pr_err("DMA init failed for unsupported omap\n");
for (i = 0; i < dm_timer_count; i++) {
timer = &dm_timers[i];
- timer->io_base = IO_ADDRESS(timer->phys_base);
+ if (cpu_class_is_omap1())
+ timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
+ else
+ timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
if (cpu_class_is_omap2()) {
/*
* OMAP1510 GPIO registers
*/
-#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
+#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
#define OMAP1510_GPIO_DATA_INPUT 0x00
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
#define OMAP1510_GPIO_DIR_CONTROL 0x08
/*
* OMAP1610 specific GPIO registers
*/
-#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
-#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
-#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
-#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
+#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
+#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
+#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
+#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
#define OMAP1610_GPIO_REVISION 0x0000
#define OMAP1610_GPIO_SYSCONFIG 0x0010
#define OMAP1610_GPIO_SYSSTATUS 0x0014
/*
* OMAP730 specific GPIO registers
*/
-#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
-#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
-#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
-#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
-#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
-#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
+#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
+#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
+#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
+#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
+#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
+#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
#define OMAP730_GPIO_DATA_INPUT 0x00
#define OMAP730_GPIO_DATA_OUTPUT 0x04
#define OMAP730_GPIO_DIR_CONTROL 0x08
/*
* OMAP850 specific GPIO registers
*/
-#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
-#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
-#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
-#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
-#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
-#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
+#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
+#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
+#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
+#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
+#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
+#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
#define OMAP850_GPIO_DATA_INPUT 0x00
#define OMAP850_GPIO_DATA_OUTPUT 0x04
#define OMAP850_GPIO_DIR_CONTROL 0x08
#define OMAP850_GPIO_INT_MASK 0x10
#define OMAP850_GPIO_INT_STATUS 0x14
+#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP_MPUIO_BASE)
+
/*
* omap24xx specific GPIO registers
*/
-#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
-#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
-#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
-#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
+#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000)
+#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000)
+#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000)
+#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000)
-#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
-#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
-#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
-#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
-#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
+#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000)
+#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000)
+#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000)
+#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000)
+#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000)
#define OMAP24XX_GPIO_REVISION 0x0000
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
* omap34xx specific GPIO registers
*/
-#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
-#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
-#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
-#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
-#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
-#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
+#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000)
+#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000)
+#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000)
+#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000)
+#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000)
+#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000)
/*
* OMAP44XX specific GPIO registers
*/
-#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
-#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
-#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
-#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
-#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
-#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
-
-#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
+#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000)
+#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000)
+#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000)
+#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000)
+#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000)
+#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000)
struct gpio_bank {
void __iomem *base;
#ifdef CONFIG_ARCH_OMAP16XX
static struct gpio_bank gpio_bank_1610[5] = {
- { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
+ { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
{ OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
{ OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
{ OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
#ifdef CONFIG_ARCH_OMAP15XX
static struct gpio_bank gpio_bank_1510[2] = {
- { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
+ { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
};
#endif
#ifdef CONFIG_ARCH_OMAP730
static struct gpio_bank gpio_bank_730[7] = {
- { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
+ { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
{ OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
{ OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
#ifndef __ASSEMBLY__
#define OMAP242X_CTRL_REGADDR(reg) \
- IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+ OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
#define OMAP243X_CTRL_REGADDR(reg) \
- IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+ OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
- IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+ OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#else
-#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#endif /* __ASSEMBLY__ */
/*
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
+ ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
mov \irqstat, #0xffffffff
cmp \irqnr, #0
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
cmpeq \irqnr, #INT_IH2_IRQ
- ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
+ ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
addeqs \irqnr, \irqnr, #32
1510:
/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
#elif defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
+#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
#endif
#if defined(CONFIG_ARCH_OMAP4)
#include <mach/omap44xx.h>
* ----------------------------------------------------------------------------
*/
+#ifdef __ASSEMBLER__
+#define IOMEM(x) (x)
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
+#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
+#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
+
+#define OMAP2_IO_OFFSET 0x90000000
+#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
+
#if defined(CONFIG_ARCH_OMAP1)
#define IO_PHYS 0xFFFB0000
-#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
#define IO_SIZE 0x40000
-#define IO_VIRT (IO_PHYS - IO_OFFSET)
-#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
-#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
-#define io_v2p(va) ((va) + IO_OFFSET)
+#define IO_VIRT (IO_PHYS - OMAP1_IO_OFFSET)
#elif defined(CONFIG_ARCH_OMAP2)
#define OMAP243X_SMS_VIRT 0xFC000000
#define OMAP243X_SMS_SIZE SZ_1M
-#define IO_OFFSET 0x90000000
-#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
-#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
-#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
-
/* DSP */
#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
#define DSP_MEM_24XX_VIRT 0xe0000000
#define OMAP343X_SDRC_VIRT 0xFD000000
#define OMAP343X_SDRC_SIZE SZ_1M
-
-#define IO_OFFSET 0x90000000
-#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
-
/* DSP */
#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
#define DSP_MEM_34XX_VIRT 0xe0000000
#define OMAP44XX_GPMC_VIRT 0xe0000000
#define OMAP44XX_GPMC_SIZE SZ_1M
-
-#define IO_OFFSET 0x90000000
-#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
-
#endif
-#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
-#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
-#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
-
-#ifdef __ASSEMBLER__
-#define IOMEM(x) (x)
-#else
-#define IOMEM(x) ((void __force __iomem *)(x))
+#ifndef __ASSEMBLER__
/*
- * Functions to access the OMAP IO region
- *
- * NOTE: - Use omap_read/write[bwl] for physical register addresses
- * - Use __raw_read/write[bwl]() for virtual register addresses
- * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
- * - DO NOT use hardcoded virtual addresses to allow changing the
- * IO address space again if needed
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
*/
-#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
-#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
-#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
-#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
-#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
-#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
+extern u8 omap_readb(u32 pa);
+extern u16 omap_readw(u32 pa);
+extern u32 omap_readl(u32 pa);
+extern void omap_writeb(u8 v, u32 pa);
+extern void omap_writew(u16 v, u32 pa);
+extern void omap_writel(u32 v, u32 pa);
struct omap_sdrc_params;
} xip_omap_mpu_timer_regs_t;
#define xip_omap_mpu_timer_base(n) \
-((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
+((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
(n)*OMAP_MPU_TIMER_OFFSET))
static inline unsigned long xip_omap_mpu_timer_read(int nr)
#define IRQ_SIR_IRQ 0x0040
#define OMAP44XX_GIC_DIST_BASE 0x48241000
#define OMAP44XX_GIC_CPU_BASE 0x48240100
-#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
#define OMAP44XX_SCU_BASE 0x48240000
-#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE)
+#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
-#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
+#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
#define OMAP44XX_WKUPGEN_BASE 0x48281000
-#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
#endif /* __ASM_ARCH_OMAP44XX_H */
*/
#define OMAP242X_SMS_REGADDR(reg) \
- (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+ (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
#define OMAP243X_SMS_REGADDR(reg) \
- (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+ (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
#define OMAP343X_SMS_REGADDR(reg) \
- (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+ (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
/* SMS register offsets - read/write with sms_{read,write}_reg() */
__iounmap(addr);
}
EXPORT_SYMBOL(omap_iounmap);
+
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+ if (cpu_class_is_omap1())
+ return __raw_readb(OMAP1_IO_ADDRESS(pa));
+ else
+ return __raw_readb(OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+ if (cpu_class_is_omap1())
+ return __raw_readw(OMAP1_IO_ADDRESS(pa));
+ else
+ return __raw_readw(OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+ if (cpu_class_is_omap1())
+ return __raw_readl(OMAP1_IO_ADDRESS(pa));
+ else
+ return __raw_readl(OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+ if (cpu_class_is_omap1())
+ __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
+ else
+ __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+ if (cpu_class_is_omap1())
+ __raw_writew(v, OMAP1_IO_ADDRESS(pa));
+ else
+ __raw_writew(v, OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+ if (cpu_class_is_omap1())
+ __raw_writel(v, OMAP1_IO_ADDRESS(pa));
+ else
+ __raw_writel(v, OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writel);
#define SRAM_BOOTLOADER_SZ 0x80
#endif
-#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
-
-#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
-#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
-#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
-#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
-#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
-#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
+#define OMAP24XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68005058)
+
+#define OMAP34XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT OMAP2_IO_ADDRESS(0x480022F0)
#define GP_DEVICE 0x300
dispc_write_reg(DISPC_CONTROL, l);
/* Set bypass mode in RFBI module */
- l = __raw_readl(IO_ADDRESS(RFBI_CONTROL));
+ l = __raw_readl(OMAP2_IO_ADDRESS(RFBI_CONTROL));
l |= enable ? 0 : (1 << 1);
- __raw_writel(l, IO_ADDRESS(RFBI_CONTROL));
+ __raw_writel(l, OMAP2_IO_ADDRESS(RFBI_CONTROL));
}
static void set_lcd_data_lines(int data_lines)
}
/* L3 firewall setting: enable access to OCM RAM */
- __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
+ __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0));
if ((r = alloc_palette_ram()) < 0)
goto fail2;
projects / GitHub / LineageOS / G12 / android_kernel_amlogic_linux-4.9.git / commitdiff