Blackfin arch: do not allow L2 to be cached on BF561 SMP
authorMike Frysinger <vapier.adi@gmail.com>
Wed, 7 Jan 2009 15:14:38 +0000 (23:14 +0800)
committerBryan Wu <cooloney@kernel.org>
Wed, 7 Jan 2009 15:14:38 +0000 (23:14 +0800)
Signed-off-by: Bryan Wu <cooloney@kernel.org>
arch/blackfin/Kconfig

index b8bc5a402fa40e877b82e9c0cf48db9af3cbef87..f8edfbe5faed01e3d98fad67c430bafeb973a7c4 100644 (file)
@@ -866,7 +866,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
        bool "Cache L2 SRAM"
-       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
        default n
        help
          Select to make L2 SRAM cacheable in L1 data and instruction cache.