config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
+ select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
+ select CSRC_R4K
select CEVT_GT641XX
select DMA_NONCOHERENT
select HW_HAS_PCI
bool "DECstations"
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select NO_IOPORT
select IRQ_CPU
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select CEVT_R4K
+ select CSRC_R4K
select GENERIC_ISA_DMA
select IRQ_CPU
select I8253
config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
bool "Lemote Fulong mini-PC"
select ARCH_SPARSEMEM_ENABLE
select CEVT_R4K
+ select CSRC_R4K
select SYS_HAS_CPU_LOONGSON2
select DMA_NONCOHERENT
select BOOT_ELF32
bool "MIPS Atlas board"
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select IRQ_CPU
config MIPS_SEAD
bool "MIPS SEAD board"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_CPU
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
config MIPS_SIM
bool 'MIPS simulator (MIPSsim)'
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
config MARKEINS
bool "NEC EMMA2RH Mark-eins"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
config MACH_VR41XX
bool "NEC VR4100 series based machines"
select CEVT_R4K
+ select CSRC_R4K
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
config PMC_YOSEMITE
bool "PMC-Sierra Yosemite eval board"
select CEVT_R4K
+ select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
config QEMU
bool "Qemu"
select CEVT_R4K
+ select CSRC_R4K
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
select ARC32
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_EISA
select I8253
select ARC32
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HW_HAS_EISA
config TOSHIBA_RBTX4927
bool "Toshiba RBTX49[23]7 board"
select CEVT_R4K
+ select CSRC_R4K
select CEVT_TXX9
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
config TOSHIBA_RBTX4938
bool "Toshiba RBTX4938 board"
select CEVT_R4K
+ select CSRC_R4K
select CEVT_TXX9
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
config WR_PPMC
bool "Wind River PPMC board"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_CPU
select BOOT_ELF32
select DMA_NONCOHERENT
config CSRC_BCM1480
bool
+config CSRC_R4K
+ bool
+
config CSRC_SB1250
bool
bool
select 64BIT_PHYS_ADDR
select CEVT_R4K
+ select CSRC_R4K
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
+obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SMP_UP) += smp-up.o
obj-$(CONFIG_MIPS_MT) += mips-mt.o
obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+
+static cycle_t c0_hpt_read(void)
+{
+ return read_c0_count();
+}
+
+static struct clocksource clocksource_mips = {
+ .name = "MIPS",
+ .read = c0_hpt_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init init_mips_clocksource(void)
+{
+ /* Calclate a somewhat reasonable rating value */
+ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+
+ clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+
+ clocksource_register(&clocksource_mips);
+}
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * Symmetric Uniprocessor (TM) Support
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+/*
+ * Send inter-processor interrupt
+ */
+void up_send_ipi_single(int cpu, unsigned int action)
+{
+ panic(KERN_ERR "%s called", __func__);
+}
+
+static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)
+{
+ panic(KERN_ERR "%s called", __func__);
+}
+
+/*
+ * After we've done initial boot, this function is called to allow the
+ * board code to clean up state, if needed
+ */
+void __cpuinit up_init_secondary(void)
+{
+}
+
+void __cpuinit up_smp_finish(void)
+{
+}
+
+/* Hook for after all CPUs are online */
+void up_cpus_done(void)
+{
+}
+
+/*
+ * Firmware CPU startup hook
+ */
+void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
+{
+}
+
+void __init up_smp_setup(void)
+{
+}
+
+void __init up_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+struct plat_smp_ops up_smp_ops = {
+ .send_ipi_single = up_send_ipi_single,
+ .send_ipi_mask = up_send_ipi_mask,
+ .init_secondary = up_init_secondary,
+ .smp_finish = up_smp_finish,
+ .cpus_done = up_cpus_done,
+ .boot_secondary = up_boot_secondary,
+ .smp_setup = up_smp_setup,
+ .prepare_cpus = up_prepare_cpus,
+};
return rtc_mips_set_mmss(now.tv_sec);
}
-/*
- * High precision timer functions for a R4k-compatible timer.
- */
-static cycle_t c0_hpt_read(void)
-{
- return read_c0_count();
-}
-
int (*mips_timer_state)(void);
int null_perf_irq(void)
unsigned int mips_hpt_frequency;
-static struct clocksource clocksource_mips = {
- .name = "MIPS",
- .read = c0_hpt_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
{
u64 temp;
cd->mult = (u32) temp;
}
-static void __init init_mips_clocksource(void)
-{
- /* Calclate a somewhat reasonable rating value */
- clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
-
- clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
-
- clocksource_register(&clocksource_mips);
-}
-
void __init __weak plat_time_init(void)
{
}
config PMC_MSP4200_EVAL
bool "PMC-Sierra MSP4200 Eval Board"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_MSP_SLP
select HW_HAS_PCI
config PMC_MSP4200_GW
bool "PMC-Sierra MSP4200 VoIP Gateway"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_MSP_SLP
select HW_HAS_PCI
config CASIO_E55
bool "CASIO CASSIOPEIA E-10/15/55/65"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select ISA
config IBM_WORKPAD
bool "IBM WorkPad z50"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select ISA
config NEC_CMBVR4133
bool "NEC CMB-VR4133"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
config TANBAC_TB022X
bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
config VICTOR_MPC30X
bool "Victor MP-C303/304"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
config ZAO_CAPCELLA
bool "ZAO Networks Capcella"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
}
#endif
+/*
+ * Initialize the count register as a clocksource
+ */
+#ifdef CONFIG_CEVT_R4K
+extern void init_mips_clocksource(void);
+#else
+static inline void init_mips_clocksource(void)
+{
+}
+#endif
+
extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
extern void clockevent_set_clock(struct clock_event_device *cd,
unsigned int clock);
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff