endchoice
source "arch/sh/mm/Kconfig"
+
source "arch/sh/Kconfig.cpu"
-menu "Board support"
-
-config SOLUTION_ENGINE
- bool
-
-config SH_SOLUTION_ENGINE
- bool "SolutionEngine"
- select SOLUTION_ENGINE
- select CPU_HAS_IPR_IRQ
- depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \
- CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
- CPU_SUBTYPE_SH7750R
- help
- Select SolutionEngine if configuring for a Hitachi SH7705, SH7709,
- SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board.
-
-config SH_7206_SOLUTION_ENGINE
- bool "SolutionEngine7206"
- select SOLUTION_ENGINE
- depends on CPU_SUBTYPE_SH7206
- help
- Select 7206 SolutionEngine if configuring for a Hitachi SH7206
- evaluation board.
-
-config SH_7619_SOLUTION_ENGINE
- bool "SolutionEngine7619"
- select SOLUTION_ENGINE
- depends on CPU_SUBTYPE_SH7619
- help
- Select 7619 SolutionEngine if configuring for a Hitachi SH7619
- evaluation board.
-
-config SH_7721_SOLUTION_ENGINE
- bool "SolutionEngine7721"
- select SOLUTION_ENGINE
- depends on CPU_SUBTYPE_SH7721
- help
- Select 7721 SolutionEngine if configuring for a Hitachi SH7721
- evaluation board.
-
-config SH_7722_SOLUTION_ENGINE
- bool "SolutionEngine7722"
- select SOLUTION_ENGINE
- depends on CPU_SUBTYPE_SH7722
- help
- Select 7722 SolutionEngine if configuring for a Hitachi SH772
- evaluation board.
-
-config SH_7751_SOLUTION_ENGINE
- bool "SolutionEngine7751"
- select SOLUTION_ENGINE
- select CPU_HAS_IPR_IRQ
- depends on CPU_SUBTYPE_SH7751
- help
- Select 7751 SolutionEngine if configuring for a Hitachi SH7751
- evaluation board.
-
-config SH_7780_SOLUTION_ENGINE
- bool "SolutionEngine7780"
- select SOLUTION_ENGINE
- select SYS_SUPPORTS_PCI
- depends on CPU_SUBTYPE_SH7780
- help
- Select 7780 SolutionEngine if configuring for a Renesas SH7780
- evaluation board.
-
-config SH_7343_SOLUTION_ENGINE
- bool "SolutionEngine7343"
- select SOLUTION_ENGINE
- depends on CPU_SUBTYPE_SH7343
- help
- Select 7343 SolutionEngine if configuring for a Hitachi
- SH7343 (SH-Mobile 3AS) evaluation board.
-
-config SH_7751_SYSTEMH
- bool "SystemH7751R"
- depends on CPU_SUBTYPE_SH7751R
- help
- Select SystemH if you are configuring for a Renesas SystemH
- 7751R evaluation board.
-
-config SH_HP6XX
- bool "HP6XX"
- select SYS_SUPPORTS_APM_EMULATION
- select HD6446X_SERIES
- depends on CPU_SUBTYPE_SH7709
- help
- Select HP6XX if configuring for a HP jornada HP6xx.
- More information (hardware only) at
- <http://www.hp.com/jornada/>.
-
-config SH_DREAMCAST
- bool "Dreamcast"
- select SYS_SUPPORTS_PCI
- depends on CPU_SUBTYPE_SH7091
- help
- Select Dreamcast if configuring for a SEGA Dreamcast.
- More information at <http://www.linux-sh.org>
-
-config SH_SH03
- bool "Interface CTP/PCI-SH03"
- depends on CPU_SUBTYPE_SH7751
- select CPU_HAS_IPR_IRQ
- select SYS_SUPPORTS_PCI
- help
- CTP/PCI-SH03 is a CPU module computer that is produced
- by Interface Corporation.
- More information at <http://www.interface.co.jp>
-
-config SH_SECUREEDGE5410
- bool "SecureEdge5410"
- depends on CPU_SUBTYPE_SH7751R
- select CPU_HAS_IPR_IRQ
- select SYS_SUPPORTS_PCI
- help
- Select SecureEdge5410 if configuring for a SnapGear SH board.
- This includes both the OEM SecureEdge products as well as the
- SME product line.
-
-config SH_RTS7751R2D
- bool "RTS7751R2D"
- depends on CPU_SUBTYPE_SH7751R
- select SYS_SUPPORTS_PCI
- select IO_TRAPPED
- help
- Select RTS7751R2D if configuring for a Renesas Technology
- Sales SH-Graphics board.
-
-config SH_RSK7203
- bool "RSK7203"
- depends on CPU_SUBTYPE_SH7203
-
-config SH_SDK7780
- bool "SDK7780R3"
- depends on CPU_SUBTYPE_SH7780
- select SYS_SUPPORTS_PCI
- help
- Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3
- evaluation board.
-
-config SH_HIGHLANDER
- bool "Highlander"
- depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
- select SYS_SUPPORTS_PCI
- select IO_TRAPPED
-
-config SH_SH7785LCR
- bool "SH7785LCR"
- depends on CPU_SUBTYPE_SH7785
- select SYS_SUPPORTS_PCI
- select IO_TRAPPED
-
-config SH_SH7785LCR_29BIT_PHYSMAPS
- bool "SH7785LCR 29bit physmaps"
- depends on SH_SH7785LCR
- default y
- help
- This board has 2 physical memory maps. It can be changed with
- DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
- you can access all on-board device in 29bit address mode.
-
-config SH_MIGOR
- bool "Migo-R"
- depends on CPU_SUBTYPE_SH7722
- help
- Select Migo-R if configuring for the SH7722 Migo-R platform
- by Renesas System Solutions Asia Pte. Ltd.
-
-config SH_AP325RXA
- bool "AP-325RXA"
- depends on CPU_SUBTYPE_SH7723
- help
- Renesas "AP-325RXA" support.
- Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
-
-config SH_SH7763RDP
- bool "SH7763RDP"
- depends on CPU_SUBTYPE_SH7763
- help
- Select SH7763RDP if configuring for a Renesas SH7763
- evaluation board.
-
-config SH_EDOSK7705
- bool "EDOSK7705"
- depends on CPU_SUBTYPE_SH7705
-
-config SH_SH4202_MICRODEV
- bool "SH4-202 MicroDev"
- depends on CPU_SUBTYPE_SH4_202
- help
- Select SH4-202 MicroDev if configuring for a SuperH MicroDev board
- with an SH4-202 CPU.
-
-config SH_LANDISK
- bool "LANDISK"
- depends on CPU_SUBTYPE_SH7751R
- select SYS_SUPPORTS_PCI
- help
- I-O DATA DEVICE, INC. "LANDISK Series" support.
-
-config SH_TITAN
- bool "TITAN"
- depends on CPU_SUBTYPE_SH7751R
- select CPU_HAS_IPR_IRQ
- select SYS_SUPPORTS_PCI
- help
- Select Titan if you are configuring for a Nimble Microsystems
- NetEngine NP51R.
-
-config SH_SHMIN
- bool "SHMIN"
- depends on CPU_SUBTYPE_SH7706
- select CPU_HAS_IPR_IRQ
- help
- Select SHMIN if configuring for the SHMIN board.
-
-config SH_LBOX_RE2
- bool "L-BOX RE2"
- depends on CPU_SUBTYPE_SH7751R
- select SYS_SUPPORTS_PCI
- help
- Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
-
-config SH_X3PROTO
- bool "SH-X3 Prototype board"
- depends on CPU_SUBTYPE_SHX3
-
-config SH_MAGIC_PANEL_R2
- bool "Magic Panel R2"
- depends on CPU_SUBTYPE_SH7720
- help
- Select Magic Panel R2 if configuring for Magic Panel R2.
-
-config SH_CAYMAN
- bool "Hitachi Cayman"
- depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
- select SYS_SUPPORTS_PCI
-
-endmenu
-
-source "arch/sh/boards/mach-r2d/Kconfig"
-source "arch/sh/boards/mach-highlander/Kconfig"
-source "arch/sh/boards/mach-sdk7780/Kconfig"
-source "arch/sh/boards/mach-migor/Kconfig"
-source "arch/sh/boards/mach-magicpanelr2/Kconfig"
+source "arch/sh/boards/Kconfig"
menu "Timer and clock configuration"
core-y += arch/sh/kernel/ arch/sh/mm/
core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
-# Boards
-machdir-$(CONFIG_SH_SOLUTION_ENGINE) += mach-se/770x
-machdir-$(CONFIG_SH_7206_SOLUTION_ENGINE) += mach-se/7206
-machdir-$(CONFIG_SH_7619_SOLUTION_ENGINE) += mach-se/7619
-machdir-$(CONFIG_SH_7722_SOLUTION_ENGINE) += mach-se/7722
-machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) += mach-se/7751
-machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) += mach-se/7780
-machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) += mach-se/7343
-machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += mach-se/7721
+# Boards and Mach groups
+machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se
machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx
machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast
machdir-$(CONFIG_SH_SH03) += mach-sh03
machdir-$(CONFIG_SH_MAGIC_PANEL_R2) += mach-magicpanelr2
machdir-$(CONFIG_SH_CAYMAN) += mach-cayman
-incdir-y := $(notdir $(machdir-y))
-
ifneq ($(machdir-y),)
core-y += $(addprefix arch/sh/boards/, \
$(filter-out ., $(patsubst %,%/,$(machdir-y))))
boot := arch/sh/boot
cflags-y += -Iarch/sh/include/$(cpuincdir-y)
-cflags-y += $(foreach d, $(incdir-y), -Iarch/sh/include/mach-$(d))
+cflags-y += $(foreach d, $(machdir-y), -Iarch/sh/include/$(d))
KBUILD_CFLAGS += -pipe $(cflags-y)
KBUILD_CPPFLAGS += $(cflags-y)
--- /dev/null
+menu "Board support"
+
+config SOLUTION_ENGINE
+ bool
+
+config SH_SOLUTION_ENGINE
+ bool "SolutionEngine"
+ select SOLUTION_ENGINE
+ select CPU_HAS_IPR_IRQ
+ depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \
+ CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+ CPU_SUBTYPE_SH7750R
+ help
+ Select SolutionEngine if configuring for a Hitachi SH7705, SH7709,
+ SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board.
+
+config SH_7206_SOLUTION_ENGINE
+ bool "SolutionEngine7206"
+ select SOLUTION_ENGINE
+ depends on CPU_SUBTYPE_SH7206
+ help
+ Select 7206 SolutionEngine if configuring for a Hitachi SH7206
+ evaluation board.
+
+config SH_7619_SOLUTION_ENGINE
+ bool "SolutionEngine7619"
+ select SOLUTION_ENGINE
+ depends on CPU_SUBTYPE_SH7619
+ help
+ Select 7619 SolutionEngine if configuring for a Hitachi SH7619
+ evaluation board.
+
+config SH_7721_SOLUTION_ENGINE
+ bool "SolutionEngine7721"
+ select SOLUTION_ENGINE
+ depends on CPU_SUBTYPE_SH7721
+ help
+ Select 7721 SolutionEngine if configuring for a Hitachi SH7721
+ evaluation board.
+
+config SH_7722_SOLUTION_ENGINE
+ bool "SolutionEngine7722"
+ select SOLUTION_ENGINE
+ depends on CPU_SUBTYPE_SH7722
+ help
+ Select 7722 SolutionEngine if configuring for a Hitachi SH772
+ evaluation board.
+
+config SH_7751_SOLUTION_ENGINE
+ bool "SolutionEngine7751"
+ select SOLUTION_ENGINE
+ select CPU_HAS_IPR_IRQ
+ depends on CPU_SUBTYPE_SH7751
+ help
+ Select 7751 SolutionEngine if configuring for a Hitachi SH7751
+ evaluation board.
+
+config SH_7780_SOLUTION_ENGINE
+ bool "SolutionEngine7780"
+ select SOLUTION_ENGINE
+ select SYS_SUPPORTS_PCI
+ depends on CPU_SUBTYPE_SH7780
+ help
+ Select 7780 SolutionEngine if configuring for a Renesas SH7780
+ evaluation board.
+
+config SH_7343_SOLUTION_ENGINE
+ bool "SolutionEngine7343"
+ select SOLUTION_ENGINE
+ depends on CPU_SUBTYPE_SH7343
+ help
+ Select 7343 SolutionEngine if configuring for a Hitachi
+ SH7343 (SH-Mobile 3AS) evaluation board.
+
+config SH_7751_SYSTEMH
+ bool "SystemH7751R"
+ depends on CPU_SUBTYPE_SH7751R
+ help
+ Select SystemH if you are configuring for a Renesas SystemH
+ 7751R evaluation board.
+
+config SH_HP6XX
+ bool "HP6XX"
+ select SYS_SUPPORTS_APM_EMULATION
+ select HD6446X_SERIES
+ depends on CPU_SUBTYPE_SH7709
+ help
+ Select HP6XX if configuring for a HP jornada HP6xx.
+ More information (hardware only) at
+ <http://www.hp.com/jornada/>.
+
+config SH_DREAMCAST
+ bool "Dreamcast"
+ select SYS_SUPPORTS_PCI
+ depends on CPU_SUBTYPE_SH7091
+ help
+ Select Dreamcast if configuring for a SEGA Dreamcast.
+ More information at <http://www.linux-sh.org>
+
+config SH_SH03
+ bool "Interface CTP/PCI-SH03"
+ depends on CPU_SUBTYPE_SH7751
+ select CPU_HAS_IPR_IRQ
+ select SYS_SUPPORTS_PCI
+ help
+ CTP/PCI-SH03 is a CPU module computer that is produced
+ by Interface Corporation.
+ More information at <http://www.interface.co.jp>
+
+config SH_SECUREEDGE5410
+ bool "SecureEdge5410"
+ depends on CPU_SUBTYPE_SH7751R
+ select CPU_HAS_IPR_IRQ
+ select SYS_SUPPORTS_PCI
+ help
+ Select SecureEdge5410 if configuring for a SnapGear SH board.
+ This includes both the OEM SecureEdge products as well as the
+ SME product line.
+
+config SH_RTS7751R2D
+ bool "RTS7751R2D"
+ depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
+ select IO_TRAPPED
+ help
+ Select RTS7751R2D if configuring for a Renesas Technology
+ Sales SH-Graphics board.
+
+config SH_RSK7203
+ bool "RSK7203"
+ depends on CPU_SUBTYPE_SH7203
+
+config SH_SDK7780
+ bool "SDK7780R3"
+ depends on CPU_SUBTYPE_SH7780
+ select SYS_SUPPORTS_PCI
+ help
+ Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3
+ evaluation board.
+
+config SH_HIGHLANDER
+ bool "Highlander"
+ depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
+ select SYS_SUPPORTS_PCI
+ select IO_TRAPPED
+
+config SH_SH7785LCR
+ bool "SH7785LCR"
+ depends on CPU_SUBTYPE_SH7785
+ select SYS_SUPPORTS_PCI
+ select IO_TRAPPED
+
+config SH_SH7785LCR_29BIT_PHYSMAPS
+ bool "SH7785LCR 29bit physmaps"
+ depends on SH_SH7785LCR
+ default y
+ help
+ This board has 2 physical memory maps. It can be changed with
+ DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
+ you can access all on-board device in 29bit address mode.
+
+config SH_MIGOR
+ bool "Migo-R"
+ depends on CPU_SUBTYPE_SH7722
+ help
+ Select Migo-R if configuring for the SH7722 Migo-R platform
+ by Renesas System Solutions Asia Pte. Ltd.
+
+config SH_AP325RXA
+ bool "AP-325RXA"
+ depends on CPU_SUBTYPE_SH7723
+ help
+ Renesas "AP-325RXA" support.
+ Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
+
+config SH_SH7763RDP
+ bool "SH7763RDP"
+ depends on CPU_SUBTYPE_SH7763
+ help
+ Select SH7763RDP if configuring for a Renesas SH7763
+ evaluation board.
+
+config SH_EDOSK7705
+ bool "EDOSK7705"
+ depends on CPU_SUBTYPE_SH7705
+
+config SH_SH4202_MICRODEV
+ bool "SH4-202 MicroDev"
+ depends on CPU_SUBTYPE_SH4_202
+ help
+ Select SH4-202 MicroDev if configuring for a SuperH MicroDev board
+ with an SH4-202 CPU.
+
+config SH_LANDISK
+ bool "LANDISK"
+ depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
+ help
+ I-O DATA DEVICE, INC. "LANDISK Series" support.
+
+config SH_TITAN
+ bool "TITAN"
+ depends on CPU_SUBTYPE_SH7751R
+ select CPU_HAS_IPR_IRQ
+ select SYS_SUPPORTS_PCI
+ help
+ Select Titan if you are configuring for a Nimble Microsystems
+ NetEngine NP51R.
+
+config SH_SHMIN
+ bool "SHMIN"
+ depends on CPU_SUBTYPE_SH7706
+ select CPU_HAS_IPR_IRQ
+ help
+ Select SHMIN if configuring for the SHMIN board.
+
+config SH_LBOX_RE2
+ bool "L-BOX RE2"
+ depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
+ help
+ Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
+
+config SH_X3PROTO
+ bool "SH-X3 Prototype board"
+ depends on CPU_SUBTYPE_SHX3
+
+config SH_MAGIC_PANEL_R2
+ bool "Magic Panel R2"
+ depends on CPU_SUBTYPE_SH7720
+ help
+ Select Magic Panel R2 if configuring for Magic Panel R2.
+
+config SH_CAYMAN
+ bool "Hitachi Cayman"
+ depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
+ select SYS_SUPPORTS_PCI
+
+endmenu
+
+source "arch/sh/boards/mach-r2d/Kconfig"
+source "arch/sh/boards/mach-highlander/Kconfig"
+source "arch/sh/boards/mach-sdk7780/Kconfig"
+source "arch/sh/boards/mach-migor/Kconfig"
+source "arch/sh/boards/mach-magicpanelr2/Kconfig"
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
-#include <asm/se7206.h>
+#include <mach-se/mach/se7206.h>
static inline void delay(void)
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/interrupt.h>
-#include <asm/se7206.h>
+#include <mach-se/mach/se7206.h>
#define INTSTS0 0x31800000
#define INTSTS1 0x31800002
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
-#include <asm/se7206.h>
+#include <mach-se/mach/se7206.h>
#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/heartbeat.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/se7343.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach-se/mach/se7343.h>
static void disable_se7343_irq(unsigned int irq)
{
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
-#include <machvec.h>
-#include <mach/se7343.h>
+#include <asm/machvec.h>
+#include <mach-se/mach/se7343.h>
#include <asm/heartbeat.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
/* MS7750 requires special versions of in*, out* routines, since
PC-like io ports are located at upper half byte of 16-bit word which
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
static struct ipr_data ipr_irq_table[] = {
/*
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
#include <asm/io.h>
#include <asm/smc37c93x.h>
#include <asm/heartbeat.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
-#include <asm/se7721.h>
+#include <mach-se/mach/se7721.h>
enum {
UNUSED = 0,
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
-#include <asm/se7721.h>
+#include <mach-se/mach/se7721.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/se7722.h>
+#include <mach-se/mach/se7722.h>
static void disable_se7722_irq(unsigned int irq)
{
#include <linux/smc91x.h>
#include <asm/machvec.h>
#include <asm/clock.h>
-#include <asm/se7722.h>
+#include <mach-se/mach/se7722.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <asm/sh_keysc.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/io.h>
-#include <asm/se7751.h>
+#include <mach-se/mach/se7751.h>
#include <asm/addrspace.h>
static inline volatile u16 *port2adr(unsigned int port)
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/irq.h>
-#include <asm/se7751.h>
+#include <mach-se/mach/se7751.h>
static struct ipr_data ipr_irq_table[] = {
{ 13, 3, 3, 2 },
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
-#include <asm/se7751.h>
+#include <mach-se/mach/se7751.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/se7780.h>
+#include <mach-se/mach/se7780.h>
/*
* Initialize IRQ setting
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
-#include <asm/se7780.h>
+#include <mach-se/mach/se7780.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
--- /dev/null
+obj-$(CONFIG_SH_SOLUTION_ENGINE) += 770x/
+obj-$(CONFIG_SH_7206_SOLUTION_ENGINE) += 7206/
+obj-$(CONFIG_SH_7619_SOLUTION_ENGINE) += 7619/
+obj-$(CONFIG_SH_7722_SOLUTION_ENGINE) += 7722/
+obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/
+obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/
+obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/
+obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
-#include <asm/se7780.h>
+#include <mach-se/mach/se7780.h>
#include <asm/io.h>
#include "pci-sh4.h"
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_SE_H
-#define __ASM_SH_HITACHI_SE_H
-
-/*
- * linux/include/asm-sh/hitachi_se.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * Hitachi SolutionEngine support
- */
-
-/* Box specific addresses. */
-
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_FROM 0x01000000 /* EPROM */
-#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0x12000000
-#define PA_EXT4_SIZE 0x02000000
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
-
-#define PA_83902 0xb0000000 /* DP83902A */
-#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
-#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
-
-#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
-#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
-#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
-#define PA_LED 0xb0c00000 /* LED */
-#if defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define PA_BCR 0xb0e00000
-#else
-#define PA_BCR 0xb1400000 /* FPGA */
-#endif
-
-#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA (PA_BCR + 0)
-#define BCR_ILCRB (PA_BCR + 2)
-#define BCR_ILCRC (PA_BCR + 4)
-#define BCR_ILCRD (PA_BCR + 6)
-#define BCR_ILCRE (PA_BCR + 8)
-#define BCR_ILCRF (PA_BCR + 10)
-#define BCR_ILCRG (PA_BCR + 12)
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define IRQ_STNIC 12
-#define IRQ_CFCARD 14
-#else
-#define IRQ_STNIC 10
-#define IRQ_CFCARD 7
-#endif
-
-/* SH Ether support (SH7710/SH7712) */
-/* Base address */
-#define SH_ETH0_BASE 0xA7000000
-#define SH_ETH1_BASE 0xA7000400
-/* PHY ID */
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
-# define PHY_ID 0x00
-#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
-# define PHY_ID 0x01
-#endif
-/* Ether IRQ */
-#define SH_ETH0_IRQ 80
-#define SH_ETH1_IRQ 81
-#define SH_TSU_IRQ 82
-
-void init_se_IRQ(void);
-
-#define __IO_PREFIX se
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_HITACHI_SE_H */
+++ /dev/null
-#ifndef __ASM_SH_SE7206_H
-#define __ASM_SH_SE7206_H
-
-#define PA_SMSC 0x30000000
-#define PA_MRSHPC 0x34000000
-#define PA_LED 0x31400000
-
-void init_se7206_IRQ(void);
-
-#define __IO_PREFIX se7206
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_SE7206_H */
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_SE7343_H
-#define __ASM_SH_HITACHI_SE7343_H
-
-/*
- * include/asm-sh/se/se7343.h
- *
- * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
- *
- * SH-Mobile SolutionEngine 7343 support
- */
-
-/* Box specific addresses. */
-
-/* Area 0 */
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
-#define PA_FROM 0x00400000 /* Flash ROM */
-#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
-#define PA_SRAM 0x00800000 /* SRAM */
-#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
-/* Area 1 */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-/* Area 2 */
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-/* Area 3 */
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-/* Area 4 */
-#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
-#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-#define PA_LED 0xb0C00000 /* LED */
-#define LED_SHIFT 0
-#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
-#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
-#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
-#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
-/* Area 5 */
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-/* Area 6 */
-#define PA_LCD1 0xb8000000
-#define PA_LCD2 0xb8800000
-
-#define PORT_PACR 0xA4050100
-#define PORT_PBCR 0xA4050102
-#define PORT_PCCR 0xA4050104
-#define PORT_PDCR 0xA4050106
-#define PORT_PECR 0xA4050108
-#define PORT_PFCR 0xA405010A
-#define PORT_PGCR 0xA405010C
-#define PORT_PHCR 0xA405010E
-#define PORT_PJCR 0xA4050110
-#define PORT_PKCR 0xA4050112
-#define PORT_PLCR 0xA4050114
-#define PORT_PMCR 0xA4050116
-#define PORT_PNCR 0xA4050118
-#define PORT_PQCR 0xA405011A
-#define PORT_PRCR 0xA405011C
-#define PORT_PSCR 0xA405011E
-#define PORT_PTCR 0xA4050140
-#define PORT_PUCR 0xA4050142
-#define PORT_PVCR 0xA4050144
-#define PORT_PWCR 0xA4050146
-#define PORT_PYCR 0xA4050148
-#define PORT_PZCR 0xA405014A
-
-#define PORT_PSELA 0xA405014C
-#define PORT_PSELB 0xA405014E
-#define PORT_PSELC 0xA4050150
-#define PORT_PSELD 0xA4050152
-#define PORT_PSELE 0xA4050154
-
-#define PORT_HIZCRA 0xA4050156
-#define PORT_HIZCRB 0xA4050158
-#define PORT_HIZCRC 0xA405015C
-
-#define PORT_DRVCR 0xA4050180
-
-#define PORT_PADR 0xA4050120
-#define PORT_PBDR 0xA4050122
-#define PORT_PCDR 0xA4050124
-#define PORT_PDDR 0xA4050126
-#define PORT_PEDR 0xA4050128
-#define PORT_PFDR 0xA405012A
-#define PORT_PGDR 0xA405012C
-#define PORT_PHDR 0xA405012E
-#define PORT_PJDR 0xA4050130
-#define PORT_PKDR 0xA4050132
-#define PORT_PLDR 0xA4050134
-#define PORT_PMDR 0xA4050136
-#define PORT_PNDR 0xA4050138
-#define PORT_PQDR 0xA405013A
-#define PORT_PRDR 0xA405013C
-#define PORT_PTDR 0xA4050160
-#define PORT_PUDR 0xA4050162
-#define PORT_PVDR 0xA4050164
-#define PORT_PWDR 0xA4050166
-#define PORT_PYDR 0xA4050168
-
-#define FPGA_IN 0xb1400000
-#define FPGA_OUT 0xb1400002
-
-#define __IO_PREFIX sh7343se
-#include <asm/io_generic.h>
-
-#define IRQ0_IRQ 32
-#define IRQ1_IRQ 33
-#define IRQ4_IRQ 36
-#define IRQ5_IRQ 37
-
-#define SE7343_FPGA_IRQ_MRSHPC0 0
-#define SE7343_FPGA_IRQ_MRSHPC1 1
-#define SE7343_FPGA_IRQ_MRSHPC2 2
-#define SE7343_FPGA_IRQ_MRSHPC3 3
-#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
-#define SE7343_FPGA_IRQ_USB 8
-
-#define SE7343_FPGA_IRQ_NR 11
-#define SE7343_FPGA_IRQ_BASE 120
-
-#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
-#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
-#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
-#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
-#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
-#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
-
-/* arch/sh/boards/se/7343/irq.c */
-void init_7343se_IRQ(void);
-
-#endif /* __ASM_SH_HITACHI_SE7343_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * Hitachi UL SolutionEngine 7721 Support.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-
-#ifndef __ASM_SH_SE7721_H
-#define __ASM_SH_SE7721_H
-#include <asm/addrspace.h>
-
-/* Box specific addresses. */
-#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
-#define PA_ROM 0xa0000000 /* EPROM */
-#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
-#define PA_FROM 0xa1000000 /* Flash-ROM */
-#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
-#define PA_EXT1 0xa4000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0xb0000000
-#define PA_EXT4_SIZE 0x04000000
-
-#define PA_PERIPHERAL 0xB8000000
-
-#define PA_PCIC PA_PERIPHERAL
-#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
-#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
-#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
-#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define PA_LED 0xB6800000 /* 8bit LED */
-#define PA_FPGA 0xB7000000 /* FPGA base address */
-
-#define MRSHPC_IRQ0 10
-
-#define FPGA_ILSR1 (PA_FPGA + 0x02)
-#define FPGA_ILSR2 (PA_FPGA + 0x03)
-#define FPGA_ILSR3 (PA_FPGA + 0x04)
-#define FPGA_ILSR4 (PA_FPGA + 0x05)
-#define FPGA_ILSR5 (PA_FPGA + 0x06)
-#define FPGA_ILSR6 (PA_FPGA + 0x07)
-#define FPGA_ILSR7 (PA_FPGA + 0x08)
-#define FPGA_ILSR8 (PA_FPGA + 0x09)
-
-void init_se7721_IRQ(void);
-
-#define __IO_PREFIX se7721
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_SE7721_H */
+++ /dev/null
-#ifndef __ASM_SH_SE7722_H
-#define __ASM_SH_SE7722_H
-
-/*
- * linux/include/asm-sh/se7722.h
- *
- * Copyright (C) 2007 Nobuhiro Iwamatsu
- *
- * Hitachi UL SolutionEngine 7722 Support.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-#include <asm/addrspace.h>
-
-/* Box specific addresses. */
-#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
-#define PA_ROM 0xa0000000 /* EPROM */
-#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
-#define PA_FROM 0xa1000000 /* Flash-ROM */
-#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
-#define PA_EXT1 0xa4000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0xb0000000
-#define PA_EXT4_SIZE 0x04000000
-
-#define PA_PERIPHERAL 0xB0000000
-
-#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
-#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
-#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
-
-#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
-/* GPIO */
-#define FPGA_IN 0xb1840000UL
-#define FPGA_OUT 0xb1840004UL
-
-#define PORT_PECR 0xA4050108UL
-#define PORT_PJCR 0xA4050110UL
-#define PORT_PSELD 0xA4050154UL
-#define PORT_PSELB 0xA4050150UL
-
-#define PORT_PSELC 0xA4050152UL
-#define PORT_PKCR 0xA4050112UL
-#define PORT_PHCR 0xA405010EUL
-#define PORT_PLCR 0xA4050114UL
-#define PORT_PMCR 0xA4050116UL
-#define PORT_PRCR 0xA405011CUL
-#define PORT_PXCR 0xA4050148UL
-#define PORT_PSELA 0xA405014EUL
-#define PORT_PYCR 0xA405014AUL
-#define PORT_PZCR 0xA405014CUL
-#define PORT_HIZCRA 0xA4050158UL
-#define PORT_HIZCRC 0xA405015CUL
-
-/* IRQ */
-#define IRQ0_IRQ 32
-#define IRQ1_IRQ 33
-
-#define IRQ01_MODE 0xb1800000
-#define IRQ01_STS 0xb1800004
-#define IRQ01_MASK 0xb1800008
-
-/* Bits in IRQ01_* registers */
-
-#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
-#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
-#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
-#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
-#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
-#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
-
-#define SE7722_FPGA_IRQ_NR 6
-#define SE7722_FPGA_IRQ_BASE 110
-
-#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
-#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
-#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
-#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
-#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
-#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
-
-/* arch/sh/boards/se/7722/irq.c */
-void init_se7722_IRQ(void);
-
-#define __IO_PREFIX se7722
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_SE7722_H */
+++ /dev/null
-#ifndef __ASM_SH_HITACHI_7751SE_H
-#define __ASM_SH_HITACHI_7751SE_H
-
-/*
- * linux/include/asm-sh/hitachi_7751se.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * Hitachi SolutionEngine support
-
- * Modified for 7751 Solution Engine by
- * Ian da Silva and Jeremy Siegel, 2001.
- */
-
-/* Box specific addresses. */
-
-#define PA_ROM 0x00000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_FROM 0x01000000 /* EPROM */
-#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_EXT1 0x04000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_EXT2 0x08000000
-#define PA_EXT2_SIZE 0x04000000
-#define PA_SDRAM 0x0c000000
-#define PA_SDRAM_SIZE 0x04000000
-
-#define PA_EXT4 0x12000000
-#define PA_EXT4_SIZE 0x02000000
-#define PA_EXT5 0x14000000
-#define PA_EXT5_SIZE 0x04000000
-#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
-
-#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
-#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
-#define PA_LED 0xba000000 /* LED */
-#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
-
-#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
-#define MRSHPC_MODE (PA_MRSHPC + 4)
-#define MRSHPC_OPTION (PA_MRSHPC + 6)
-#define MRSHPC_CSR (PA_MRSHPC + 8)
-#define MRSHPC_ISR (PA_MRSHPC + 10)
-#define MRSHPC_ICR (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
-#define MRSHPC_CDCR (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA (PA_BCR + 0)
-#define BCR_ILCRB (PA_BCR + 2)
-#define BCR_ILCRC (PA_BCR + 4)
-#define BCR_ILCRD (PA_BCR + 6)
-#define BCR_ILCRE (PA_BCR + 8)
-#define BCR_ILCRF (PA_BCR + 10)
-#define BCR_ILCRG (PA_BCR + 12)
-
-#define IRQ_79C973 13
-
-void init_7751se_IRQ(void);
-
-#define __IO_PREFIX sh7751se
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_HITACHI_7751SE_H */
+++ /dev/null
-#ifndef __ASM_SH_SE7780_H
-#define __ASM_SH_SE7780_H
-
-/*
- * linux/include/asm-sh/se7780.h
- *
- * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
- *
- * Hitachi UL SolutionEngine 7780 Support.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <asm/addrspace.h>
-
-/* Box specific addresses. */
-#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
-#define PA_ROM 0xa0000000 /* EPROM */
-#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
-#define PA_FROM 0xa1000000 /* Flash-ROM */
-#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
-#define PA_EXT1 0xa4000000
-#define PA_EXT1_SIZE 0x04000000
-#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
-#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
-#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
-#define PA_SDRAM_SIZE 0x08000000
-
-#define PA_EXT4 0xb0000000
-#define PA_EXT4_SIZE 0x04000000
-#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
-
-#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
-
-#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
-#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
-#define DISP_CHAR_RAM (7 << 3)
-#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
-#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
-#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
-#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
-#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
-#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
-#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
-#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
-
-#define DISP_UDC_RAM (5 << 3)
-#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
-
-/* FPGA register address and bit */
-#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
-#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
-#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
-#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
-#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
-#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
-#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
-#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
-#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
-#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
-#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
-#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
-#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
-#define PA_LED FPGA_DBG_LED
-#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
-#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
-#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
-
-/* FPGA INTSEL position */
-/* INTSEL1 */
-#define IRQPOS_SMC91CX (0 * 4)
-#define IRQPOS_SM501 (1 * 4)
-/* INTSEL2 */
-#define IRQPOS_EXTINT1 (0 * 4)
-#define IRQPOS_EXTINT2 (1 * 4)
-#define IRQPOS_EXTINT3 (2 * 4)
-#define IRQPOS_EXTINT4 (3 * 4)
-/* INTSEL3 */
-#define IRQPOS_PCCPW (0 * 4)
-
-/* IDE interrupt */
-#define IRQ_IDE0 67 /* iVDR */
-
-/* SMC interrupt */
-#define SMC_IRQ 8
-
-/* SM501 interrupt */
-#define SM501_IRQ 0
-
-/* interrupt pin */
-#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
-#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
-#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
-#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
-#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
-#define IRQPIN_PCC0 5 /* IRQ5 pin */
-#define IRQPIN_PCC2 6 /* IRQ6 pin */
-#define IRQPIN_SM501 7 /* IRQ7 pin */
-#define IRQPIN_PCCPW 7 /* IRQ7 pin */
-
-/* arch/sh/boards/se/7780/irq.c */
-void init_se7780_IRQ(void);
-
-#define __IO_PREFIX se7780
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_SE7780_H */
--- /dev/null
+#ifndef __ASM_SH_HITACHI_SE_H
+#define __ASM_SH_HITACHI_SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_se.h
+ *
+ * Copyright (C) 2000 Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+ */
+
+/* Box specific addresses. */
+
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_FROM 0x01000000 /* EPROM */
+#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0x12000000
+#define PA_EXT4_SIZE 0x02000000
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
+
+#define PA_83902 0xb0000000 /* DP83902A */
+#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
+#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
+
+#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
+#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
+#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
+#define PA_LED 0xb0c00000 /* LED */
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define PA_BCR 0xb0e00000
+#else
+#define PA_BCR 0xb1400000 /* FPGA */
+#endif
+
+#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA (PA_BCR + 0)
+#define BCR_ILCRB (PA_BCR + 2)
+#define BCR_ILCRC (PA_BCR + 4)
+#define BCR_ILCRD (PA_BCR + 6)
+#define BCR_ILCRE (PA_BCR + 8)
+#define BCR_ILCRF (PA_BCR + 10)
+#define BCR_ILCRG (PA_BCR + 12)
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define IRQ_STNIC 12
+#define IRQ_CFCARD 14
+#else
+#define IRQ_STNIC 10
+#define IRQ_CFCARD 7
+#endif
+
+/* SH Ether support (SH7710/SH7712) */
+/* Base address */
+#define SH_ETH0_BASE 0xA7000000
+#define SH_ETH1_BASE 0xA7000400
+/* PHY ID */
+#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+# define PHY_ID 0x00
+#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
+# define PHY_ID 0x01
+#endif
+/* Ether IRQ */
+#define SH_ETH0_IRQ 80
+#define SH_ETH1_IRQ 81
+#define SH_TSU_IRQ 82
+
+void init_se_IRQ(void);
+
+#define __IO_PREFIX se
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_HITACHI_SE_H */
--- /dev/null
+#ifndef __ASM_SH_SE7206_H
+#define __ASM_SH_SE7206_H
+
+#define PA_SMSC 0x30000000
+#define PA_MRSHPC 0x34000000
+#define PA_LED 0x31400000
+
+void init_se7206_IRQ(void);
+
+#define __IO_PREFIX se7206
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7206_H */
--- /dev/null
+#ifndef __ASM_SH_HITACHI_SE7343_H
+#define __ASM_SH_HITACHI_SE7343_H
+
+/*
+ * include/asm-sh/se/se7343.h
+ *
+ * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
+ *
+ * SH-Mobile SolutionEngine 7343 support
+ */
+
+/* Box specific addresses. */
+
+/* Area 0 */
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
+#define PA_FROM 0x00400000 /* Flash ROM */
+#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
+#define PA_SRAM 0x00800000 /* SRAM */
+#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
+/* Area 1 */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+/* Area 2 */
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+/* Area 3 */
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+/* Area 4 */
+#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+#define PA_LED 0xb0C00000 /* LED */
+#define LED_SHIFT 0
+#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
+#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
+#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
+#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
+/* Area 5 */
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+/* Area 6 */
+#define PA_LCD1 0xb8000000
+#define PA_LCD2 0xb8800000
+
+#define PORT_PACR 0xA4050100
+#define PORT_PBCR 0xA4050102
+#define PORT_PCCR 0xA4050104
+#define PORT_PDCR 0xA4050106
+#define PORT_PECR 0xA4050108
+#define PORT_PFCR 0xA405010A
+#define PORT_PGCR 0xA405010C
+#define PORT_PHCR 0xA405010E
+#define PORT_PJCR 0xA4050110
+#define PORT_PKCR 0xA4050112
+#define PORT_PLCR 0xA4050114
+#define PORT_PMCR 0xA4050116
+#define PORT_PNCR 0xA4050118
+#define PORT_PQCR 0xA405011A
+#define PORT_PRCR 0xA405011C
+#define PORT_PSCR 0xA405011E
+#define PORT_PTCR 0xA4050140
+#define PORT_PUCR 0xA4050142
+#define PORT_PVCR 0xA4050144
+#define PORT_PWCR 0xA4050146
+#define PORT_PYCR 0xA4050148
+#define PORT_PZCR 0xA405014A
+
+#define PORT_PSELA 0xA405014C
+#define PORT_PSELB 0xA405014E
+#define PORT_PSELC 0xA4050150
+#define PORT_PSELD 0xA4050152
+#define PORT_PSELE 0xA4050154
+
+#define PORT_HIZCRA 0xA4050156
+#define PORT_HIZCRB 0xA4050158
+#define PORT_HIZCRC 0xA405015C
+
+#define PORT_DRVCR 0xA4050180
+
+#define PORT_PADR 0xA4050120
+#define PORT_PBDR 0xA4050122
+#define PORT_PCDR 0xA4050124
+#define PORT_PDDR 0xA4050126
+#define PORT_PEDR 0xA4050128
+#define PORT_PFDR 0xA405012A
+#define PORT_PGDR 0xA405012C
+#define PORT_PHDR 0xA405012E
+#define PORT_PJDR 0xA4050130
+#define PORT_PKDR 0xA4050132
+#define PORT_PLDR 0xA4050134
+#define PORT_PMDR 0xA4050136
+#define PORT_PNDR 0xA4050138
+#define PORT_PQDR 0xA405013A
+#define PORT_PRDR 0xA405013C
+#define PORT_PTDR 0xA4050160
+#define PORT_PUDR 0xA4050162
+#define PORT_PVDR 0xA4050164
+#define PORT_PWDR 0xA4050166
+#define PORT_PYDR 0xA4050168
+
+#define FPGA_IN 0xb1400000
+#define FPGA_OUT 0xb1400002
+
+#define __IO_PREFIX sh7343se
+#include <asm/io_generic.h>
+
+#define IRQ0_IRQ 32
+#define IRQ1_IRQ 33
+#define IRQ4_IRQ 36
+#define IRQ5_IRQ 37
+
+#define SE7343_FPGA_IRQ_MRSHPC0 0
+#define SE7343_FPGA_IRQ_MRSHPC1 1
+#define SE7343_FPGA_IRQ_MRSHPC2 2
+#define SE7343_FPGA_IRQ_MRSHPC3 3
+#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
+#define SE7343_FPGA_IRQ_USB 8
+
+#define SE7343_FPGA_IRQ_NR 11
+#define SE7343_FPGA_IRQ_BASE 120
+
+#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
+#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
+
+/* arch/sh/boards/se/7343/irq.c */
+void init_7343se_IRQ(void);
+
+#endif /* __ASM_SH_HITACHI_SE7343_H */
--- /dev/null
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#ifndef __ASM_SH_SE7721_H
+#define __ASM_SH_SE7721_H
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
+#define PA_ROM 0xa0000000 /* EPROM */
+#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
+#define PA_FROM 0xa1000000 /* Flash-ROM */
+#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
+#define PA_EXT1 0xa4000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0xb0000000
+#define PA_EXT4_SIZE 0x04000000
+
+#define PA_PERIPHERAL 0xB8000000
+
+#define PA_PCIC PA_PERIPHERAL
+#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
+#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
+#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
+#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define PA_LED 0xB6800000 /* 8bit LED */
+#define PA_FPGA 0xB7000000 /* FPGA base address */
+
+#define MRSHPC_IRQ0 10
+
+#define FPGA_ILSR1 (PA_FPGA + 0x02)
+#define FPGA_ILSR2 (PA_FPGA + 0x03)
+#define FPGA_ILSR3 (PA_FPGA + 0x04)
+#define FPGA_ILSR4 (PA_FPGA + 0x05)
+#define FPGA_ILSR5 (PA_FPGA + 0x06)
+#define FPGA_ILSR6 (PA_FPGA + 0x07)
+#define FPGA_ILSR7 (PA_FPGA + 0x08)
+#define FPGA_ILSR8 (PA_FPGA + 0x09)
+
+void init_se7721_IRQ(void);
+
+#define __IO_PREFIX se7721
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7721_H */
--- /dev/null
+#ifndef __ASM_SH_SE7722_H
+#define __ASM_SH_SE7722_H
+
+/*
+ * linux/include/asm-sh/se7722.h
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7722 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
+#define PA_ROM 0xa0000000 /* EPROM */
+#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
+#define PA_FROM 0xa1000000 /* Flash-ROM */
+#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
+#define PA_EXT1 0xa4000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0xb0000000
+#define PA_EXT4_SIZE 0x04000000
+
+#define PA_PERIPHERAL 0xB0000000
+
+#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
+#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
+
+#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
+/* GPIO */
+#define FPGA_IN 0xb1840000UL
+#define FPGA_OUT 0xb1840004UL
+
+#define PORT_PECR 0xA4050108UL
+#define PORT_PJCR 0xA4050110UL
+#define PORT_PSELD 0xA4050154UL
+#define PORT_PSELB 0xA4050150UL
+
+#define PORT_PSELC 0xA4050152UL
+#define PORT_PKCR 0xA4050112UL
+#define PORT_PHCR 0xA405010EUL
+#define PORT_PLCR 0xA4050114UL
+#define PORT_PMCR 0xA4050116UL
+#define PORT_PRCR 0xA405011CUL
+#define PORT_PXCR 0xA4050148UL
+#define PORT_PSELA 0xA405014EUL
+#define PORT_PYCR 0xA405014AUL
+#define PORT_PZCR 0xA405014CUL
+#define PORT_HIZCRA 0xA4050158UL
+#define PORT_HIZCRC 0xA405015CUL
+
+/* IRQ */
+#define IRQ0_IRQ 32
+#define IRQ1_IRQ 33
+
+#define IRQ01_MODE 0xb1800000
+#define IRQ01_STS 0xb1800004
+#define IRQ01_MASK 0xb1800008
+
+/* Bits in IRQ01_* registers */
+
+#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
+#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
+#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
+
+#define SE7722_FPGA_IRQ_NR 6
+#define SE7722_FPGA_IRQ_BASE 110
+
+#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
+#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
+
+/* arch/sh/boards/se/7722/irq.c */
+void init_se7722_IRQ(void);
+
+#define __IO_PREFIX se7722
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7722_H */
--- /dev/null
+#ifndef __ASM_SH_HITACHI_7751SE_H
+#define __ASM_SH_HITACHI_7751SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_7751se.h
+ *
+ * Copyright (C) 2000 Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+
+ * Modified for 7751 Solution Engine by
+ * Ian da Silva and Jeremy Siegel, 2001.
+ */
+
+/* Box specific addresses. */
+
+#define PA_ROM 0x00000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_FROM 0x01000000 /* EPROM */
+#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_EXT1 0x04000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_EXT2 0x08000000
+#define PA_EXT2_SIZE 0x04000000
+#define PA_SDRAM 0x0c000000
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0x12000000
+#define PA_EXT4_SIZE 0x02000000
+#define PA_EXT5 0x14000000
+#define PA_EXT5_SIZE 0x04000000
+#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
+#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
+#define PA_LED 0xba000000 /* LED */
+#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE (PA_MRSHPC + 4)
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA (PA_BCR + 0)
+#define BCR_ILCRB (PA_BCR + 2)
+#define BCR_ILCRC (PA_BCR + 4)
+#define BCR_ILCRD (PA_BCR + 6)
+#define BCR_ILCRE (PA_BCR + 8)
+#define BCR_ILCRF (PA_BCR + 10)
+#define BCR_ILCRG (PA_BCR + 12)
+
+#define IRQ_79C973 13
+
+void init_7751se_IRQ(void);
+
+#define __IO_PREFIX sh7751se
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_HITACHI_7751SE_H */
--- /dev/null
+#ifndef __ASM_SH_SE7780_H
+#define __ASM_SH_SE7780_H
+
+/*
+ * linux/include/asm-sh/se7780.h
+ *
+ * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7780 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
+#define PA_ROM 0xa0000000 /* EPROM */
+#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
+#define PA_FROM 0xa1000000 /* Flash-ROM */
+#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
+#define PA_EXT1 0xa4000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
+#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
+#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE 0x08000000
+
+#define PA_EXT4 0xb0000000
+#define PA_EXT4_SIZE 0x04000000
+#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
+
+#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
+
+#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
+#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
+#define DISP_CHAR_RAM (7 << 3)
+#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
+#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
+#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
+#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
+#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
+#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
+#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
+#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
+
+#define DISP_UDC_RAM (5 << 3)
+#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
+
+/* FPGA register address and bit */
+#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
+#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
+#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
+#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
+#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
+#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
+#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
+#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
+#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
+#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
+#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
+#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
+#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
+#define PA_LED FPGA_DBG_LED
+#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
+#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
+#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
+
+/* FPGA INTSEL position */
+/* INTSEL1 */
+#define IRQPOS_SMC91CX (0 * 4)
+#define IRQPOS_SM501 (1 * 4)
+/* INTSEL2 */
+#define IRQPOS_EXTINT1 (0 * 4)
+#define IRQPOS_EXTINT2 (1 * 4)
+#define IRQPOS_EXTINT3 (2 * 4)
+#define IRQPOS_EXTINT4 (3 * 4)
+/* INTSEL3 */
+#define IRQPOS_PCCPW (0 * 4)
+
+/* IDE interrupt */
+#define IRQ_IDE0 67 /* iVDR */
+
+/* SMC interrupt */
+#define SMC_IRQ 8
+
+/* SM501 interrupt */
+#define SM501_IRQ 0
+
+/* interrupt pin */
+#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
+#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
+#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
+#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
+#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
+#define IRQPIN_PCC0 5 /* IRQ5 pin */
+#define IRQPIN_PCC2 6 /* IRQ6 pin */
+#define IRQPIN_SM501 7 /* IRQ7 pin */
+#define IRQPIN_PCCPW 7 /* IRQ7 pin */
+
+/* arch/sh/boards/se/7780/irq.c */
+void init_se7780_IRQ(void);
+
+#define __IO_PREFIX se7780
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7780_H */
}
#if defined(CONFIG_SH_SOLUTION_ENGINE)
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
-#include <asm/se7722.h>
+#include <mach-se/mach/se7722.h>
#elif defined(CONFIG_SH_7721_SOLUTION_ENGINE)
-#include <asm/se7721.h>
+#include <mach-se/mach/se7721.h>
#endif
/*
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff