MIPS: Add architectural FDC IRQ fields

Add architectural field definitions relating to the Fast Debug Channel
(FDC) interrupt, namely the pending bit in Cause and the field in
IntCtl to specify which CPU IRQ line the FDC interrupt is routed to.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9139/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9e28922e5ef4efadd150b10b03e0a9b0521b3d6c..73447951204d8ca58ab3f6e418b512a6b261bbf0 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -428,6 +428,8 @@
  *
  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  */
+#define INTCTLB_IPFDC          23
+#define INTCTLF_IPFDC          (_ULCAST_(7) << INTCTLB_IPFDC)
 #define INTCTLB_IPPCI          26
 #define INTCTLF_IPPCI          (_ULCAST_(7) << INTCTLB_IPPCI)
 #define INTCTLB_IPTI           29
@@ -458,6 +460,8 @@
 #define         CAUSEF_IP6             (_ULCAST_(1)   << 14)
 #define         CAUSEB_IP7             15
 #define         CAUSEF_IP7             (_ULCAST_(1)   << 15)
+#define         CAUSEB_FDCI            21
+#define         CAUSEF_FDCI            (_ULCAST_(1)   << 21)
 #define         CAUSEB_IV              23
 #define         CAUSEF_IV              (_ULCAST_(1)   << 23)
 #define         CAUSEB_PCI             26