OMAPDSS: add dss_calc_clock_rates() back
authorTomi Valkeinen <tomi.valkeinen@ti.com>
Mon, 15 Oct 2012 10:27:04 +0000 (13:27 +0300)
committerTomi Valkeinen <tomi.valkeinen@ti.com>
Mon, 5 Nov 2012 09:14:05 +0000 (11:14 +0200)
dss_calc_clock_rates() was removed earlier as it was not used, but it is
needed for DSI PLL calculations, so this patch adds it back.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
drivers/video/omap2/dss/dss.c
drivers/video/omap2/dss/dss.h

index 456118beb1f8bb942eed5a33eda5eed657568a2a..d40653bf7a6c74732d43668450a43799d8aef810 100644 (file)
@@ -432,6 +432,29 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
        }
 }
 
+/* calculate clock rates using dividers in cinfo */
+int dss_calc_clock_rates(struct dss_clock_info *cinfo)
+{
+       if (dss.dpll4_m4_ck) {
+               unsigned long prate;
+
+               if (cinfo->fck_div > dss.feat->fck_div_max ||
+                               cinfo->fck_div == 0)
+                       return -EINVAL;
+
+               prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+
+               cinfo->fck = prate / cinfo->fck_div *
+                       dss.feat->dss_fck_multiplier;
+       } else {
+               if (cinfo->fck_div != 0)
+                       return -EINVAL;
+               cinfo->fck = clk_get_rate(dss.dss_clk);
+       }
+
+       return 0;
+}
+
 int dss_set_clock_div(struct dss_clock_info *cinfo)
 {
        if (dss.dpll4_m4_ck) {
index ff7a55b54b8e6e3d03b61a58e3e70c11ab0452cd..e637f8d9dcf35966357668d31850fcf74cc4feb6 100644 (file)
@@ -296,6 +296,7 @@ void dss_set_venc_output(enum omap_dss_venc_type type);
 void dss_set_dac_pwrdn_bgz(bool enable);
 
 unsigned long dss_get_dpll4_rate(void);
+int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 int dss_set_clock_div(struct dss_clock_info *cinfo);
 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
                struct dispc_clock_info *dispc_cinfo);