static int (*put_power)(void);
static int (*get_cdclk)(void);
-int hda_display_power(bool enable)
+int hda_display_power(struct hda_intel *hda, bool enable)
{
if (!get_power || !put_power)
return -ENODEV;
return put_power();
}
-void haswell_set_bclk(struct azx *chip)
+void haswell_set_bclk(struct hda_intel *hda)
{
int cdclk_freq;
unsigned int bclk_m, bclk_n;
break;
}
- azx_writew(chip, EM4, bclk_m);
- azx_writew(chip, EM5, bclk_n);
+ azx_writew(&hda->chip, EM4, bclk_m);
+ azx_writew(&hda->chip, EM5, bclk_n);
}
-int hda_i915_init(void)
+int hda_i915_init(struct hda_intel *hda)
{
int err = 0;
return err;
}
-int hda_i915_exit(void)
+int hda_i915_exit(struct hda_intel *hda)
{
if (get_power) {
symbol_put(i915_request_power_well);
pci_save_state(pci);
pci_set_power_state(pci, PCI_D3hot);
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
- hda_display_power(false);
+ hda_display_power(hda, false);
return 0;
}
return 0;
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
- hda_display_power(true);
- haswell_set_bclk(chip);
+ hda_display_power(hda, true);
+ haswell_set_bclk(hda);
}
pci_set_power_state(pci, PCI_D0);
pci_restore_state(pci);
azx_enter_link_reset(chip);
azx_clear_irq_pending(chip);
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
- hda_display_power(false);
+ hda_display_power(hda, false);
return 0;
}
return 0;
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
- hda_display_power(true);
- haswell_set_bclk(chip);
+ hda_display_power(hda, true);
+ haswell_set_bclk(hda);
}
/* Read STATESTS before controller reset */
release_firmware(chip->fw);
#endif
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
- hda_display_power(false);
- hda_i915_exit();
+ hda_display_power(hda, false);
+ hda_i915_exit(hda);
}
kfree(hda);
/* initialize chip */
azx_init_pci(chip);
- if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
- haswell_set_bclk(chip);
+ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
+ struct hda_intel *hda;
+
+ hda = container_of(chip, struct hda_intel, chip);
+ haswell_set_bclk(hda);
+ }
azx_init_chip(chip, (probe_only[dev] & 2) == 0);
/* Request power well for Haswell HDA controller and codec */
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
#ifdef CONFIG_SND_HDA_I915
- err = hda_i915_init();
+ err = hda_i915_init(hda);
if (err < 0) {
dev_err(chip->card->dev,
"Error request power-well from i915\n");
goto out_free;
}
- err = hda_display_power(true);
+ err = hda_display_power(hda, true);
if (err < 0) {
dev_err(chip->card->dev,
"Cannot turn on display power on i915\n");
};
#ifdef CONFIG_SND_HDA_I915
-int hda_display_power(bool enable);
-void haswell_set_bclk(struct azx *chip);
-int hda_i915_init(void);
-int hda_i915_exit(void);
+int hda_display_power(struct hda_intel *hda, bool enable);
+void haswell_set_bclk(struct hda_intel *hda);
+int hda_i915_init(struct hda_intel *hda);
+int hda_i915_exit(struct hda_intel *hda);
#else
-static inline int hda_display_power(bool enable) { return 0; }
-static inline void haswell_set_bclk(struct azx *chip) { return; }
-static inline int hda_i915_init(void)
+static inline int hda_display_power(struct hda_intel *hda, bool enable)
+{
+ return 0;
+}
+static inline void haswell_set_bclk(struct hda_intel *hda) { return; }
+static inline int hda_i915_init(struct hda_intel *hda)
{
return -ENODEV;
}
-static inline int hda_i915_exit(void)
+static inline int hda_i915_exit(struct hda_intel *hda)
{
return 0;
}