drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

v2: Use SKL_DPLLx symbolic names instead of raw numbers

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b2e3148a5bf39960917119d6784cdba38c00c9f..9e3fdb3722751a2ca24eccd25907d14a5dd6194b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7438,8 +7438,8 @@ enum skl_disp_power_wells {
 #define  DPLL_CFGCR2_PDIV_7 (4<<2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
 
-#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
-#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
+#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
+#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL                 0x6d000

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c115773ef4b13fa41b6451ec877c7d9245a0a19..2d3cc82dd8a4c6258eadec83276b1ba08585c9a4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -969,8 +969,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
        uint32_t cfgcr1_val, cfgcr2_val;
        uint32_t p0, p1, p2, dco_freq;
 
-       cfgcr1_reg = GET_CFG_CR1_REG(dpll);
-       cfgcr2_reg = GET_CFG_CR2_REG(dpll);
+       cfgcr1_reg = DPLL_CFGCR1(dpll);
+       cfgcr2_reg = DPLL_CFGCR2(dpll);
 
        cfgcr1_val = I915_READ(cfgcr1_reg);
        cfgcr2_val = I915_READ(cfgcr2_reg);
@@ -2504,20 +2504,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
        {
                /* DPLL 1 */
                .ctl = LCPLL2_CTL,
-               .cfgcr1 = DPLL1_CFGCR1,
-               .cfgcr2 = DPLL1_CFGCR2,
+               .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
+               .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
        },
        {
                /* DPLL 2 */
                .ctl = WRPLL_CTL1,
-               .cfgcr1 = DPLL2_CFGCR1,
-               .cfgcr2 = DPLL2_CFGCR2,
+               .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
+               .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
        },
        {
                /* DPLL 3 */
                .ctl = WRPLL_CTL2,
-               .cfgcr1 = DPLL3_CFGCR1,
-               .cfgcr2 = DPLL3_CFGCR2,
+               .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
+               .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
        },
 };