drm/nv40/pm: implement first type of pwm fanspeed funcs
authorBen Skeggs <bskeggs@redhat.com>
Thu, 28 Jul 2011 00:40:48 +0000 (10:40 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 21 Dec 2011 09:01:09 +0000 (19:01 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_pm.h
drivers/gpu/drm/nouveau/nouveau_state.c
drivers/gpu/drm/nouveau/nv40_pm.c

index 8ac02cdd03a1039067c444c811fcfeecb0ab5554..bbab7013aed102a0c6d9f46acb98dd4604c647be 100644 (file)
@@ -56,6 +56,8 @@ void nv04_pm_clock_set(struct drm_device *, void *);
 int nv40_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
 void *nv40_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
 void nv40_pm_clocks_set(struct drm_device *, void *);
+int nv40_pm_fanspeed_get(struct drm_device *);
+int nv40_pm_fanspeed_set(struct drm_device *, int percent);
 
 /* nv50_pm.c */
 int nv50_pm_clock_get(struct drm_device *, u32 id);
index d8831ab42bb90344a28b8a146624aa4aca69d8c5..06664e779792ebdb79b2978f35ca9d250ae4e08a 100644 (file)
@@ -292,6 +292,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                engine->pm.voltage_get          = nouveau_voltage_gpio_get;
                engine->pm.voltage_set          = nouveau_voltage_gpio_set;
                engine->pm.temp_get             = nv40_temp_get;
+               switch (dev_priv->chipset) {
+               case 0x40:
+               case 0x49:
+                       engine->pm.fanspeed_get = nv40_pm_fanspeed_get;
+                       engine->pm.fanspeed_set = nv40_pm_fanspeed_set;
+                       break;
+               default:
+                       break;
+               }
                engine->vram.init               = nouveau_mem_detect;
                engine->vram.takedown           = nouveau_stub_takedown;
                engine->vram.flags_valid        = nouveau_mem_flags_valid;
index e676b0d534786ee140017691b83c4580e0e6bbc3..c969bcbab5474b2f756e9dbd79be2e24341dd864 100644 (file)
@@ -346,3 +346,29 @@ resume:
 
        kfree(info);
 }
+
+int
+nv40_pm_fanspeed_get(struct drm_device *dev)
+{
+       u32 reg = nv_rd32(dev, 0x0010f0);
+       if (reg & 0x80000000) {
+               u32 duty = (reg & 0x7fff0000) >> 16;
+               u32 divs = (reg & 0x00007fff);
+               if (divs && divs >= duty)
+                       return ((divs - duty) * 100) / divs;
+       }
+
+       return 100;
+}
+
+int
+nv40_pm_fanspeed_set(struct drm_device *dev, int percent)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+       u32 divs = pm->pwm_divisor;
+       u32 duty = ((100 - percent) * divs) / 100;
+
+       nv_wr32(dev, 0x0010f0, 0x80000000 | (duty << 16) | divs);
+       return 0;
+}