ARM: mach-shmobile: Add support for PINT though INTC macros

Add a INTC_PINT() macro with various helper bits to allow SoCs
like sh73a0 to suppor the PINT hardware using regular INTC tables.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h
index 1cd8b36678ee7f6cc4e73738d0e63d3a1613fb04..8b22258c8caaa738109d621013e52da209cfc1e0 100644 (file)
--- a/arch/arm/mach-shmobile/include/mach/intc.h
+++ b/arch/arm/mach-shmobile/include/mach/intc.h
@@ -192,4 +192,55 @@ static struct intc_desc p ## _desc __initdata = {                  \
                             p ## _sense_registers, p ## _ack_registers) \
 }
 
+#define INTC_PINT_E_EMPTY
+#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0,
+#define INTC_PINT_E(p)                                                 \
+       PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \
+       PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7,
+
+#define INTC_PINT_V_NONE
+#define INTC_PINT_V(p, vect)                                   \
+       vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1),       \
+       vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3),       \
+       vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5),       \
+       vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7),
+
+#define INTC_PINT(p, mask_reg, sense_base, str,                                \
+       enums_1, enums_2, enums_3, enums_4,                             \
+       vect_1, vect_2, vect_3, vect_4,                                 \
+       mask_a, mask_b, mask_c, mask_d,                                 \
+       sense_a, sense_b, sense_c, sense_d)                             \
+                                                                       \
+enum {                                                                 \
+       PINT ## p ## _UNUSED = 0,                                       \
+       enums_1 enums_2 enums_3 enums_4                                 \
+};                                                                     \
+                                                                       \
+static struct intc_vect p ## _vectors[] __initdata = {                 \
+       vect_1 vect_2 vect_3 vect_4                                     \
+};                                                                     \
+                                                                       \
+static struct intc_mask_reg p ## _mask_registers[] __initdata = {      \
+       { mask_reg, 0, 32, /* PINTER */                                 \
+         { mask_a mask_b mask_c mask_d } }                             \
+};                                                                     \
+                                                                       \
+static struct intc_sense_reg p ## _sense_registers[] __initdata = {    \
+       { sense_base + 0x00, 16, 2, /* PINTCR */                        \
+         { sense_a } },                                                \
+       { sense_base + 0x04, 16, 2, /* PINTCR */                        \
+         { sense_b } },                                                \
+       { sense_base + 0x08, 16, 2, /* PINTCR */                        \
+         { sense_c } },                                                \
+       { sense_base + 0x0c, 16, 2, /* PINTCR */                        \
+         { sense_d } },                                                \
+};                                                                     \
+                                                                       \
+static struct intc_desc p ## _desc __initdata = {                      \
+       .name = str,                                                    \
+       .hw = INTC_HW_DESC(p ## _vectors, NULL,                         \
+                            p ## _mask_registers, NULL,                \
+                            p ## _sense_registers, NULL),              \
+}
+
 #endif  /* __ASM_MACH_INTC_H */