};
static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj,
- bool pipelined);
+ struct intel_ring_buffer *pipelined);
static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
- int write);
+ bool write);
static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
uint64_t offset,
uint64_t size);
mutex_lock(&dev->struct_mutex);
BUG_ON(obj->pin_count && !obj->pin_mappable);
- if (obj->gtt_space) {
- if (!obj->map_and_fenceable) {
- ret = i915_gem_object_unbind(obj);
- if (ret)
- goto unlock;
- }
+ if (!obj->map_and_fenceable) {
+ ret = i915_gem_object_unbind(obj);
+ if (ret)
+ goto unlock;
}
if (!obj->gtt_space) {
if (reg->gpu) {
int ret;
- ret = i915_gem_object_flush_gpu_write_domain(obj, true);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, NULL);
if (ret)
return ret;
/** Flushes any GPU write domain for the object if it's dirty. */
static int
i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj,
- bool pipelined)
+ struct intel_ring_buffer *pipelined)
{
struct drm_device *dev = obj->base.dev;
i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
BUG_ON(obj->base.write_domain);
- if (pipelined)
+ if (pipelined && pipelined == obj->ring)
return 0;
return i915_gem_object_wait_rendering(obj, true);
if (obj->gtt_space == NULL)
return -EINVAL;
- ret = i915_gem_object_flush_gpu_write_domain(obj, false);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, NULL);
if (ret != 0)
return ret;
*/
int
i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
- bool pipelined)
+ struct intel_ring_buffer *pipelined)
{
uint32_t old_read_domains;
int ret;
if (obj->gtt_space == NULL)
return -EINVAL;
- ret = i915_gem_object_flush_gpu_write_domain(obj, true);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
if (ret)
return ret;
* flushes to occur.
*/
static int
-i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, int write)
+i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
{
uint32_t old_write_domain, old_read_domains;
int ret;
int
intel_pin_and_fence_fb_obj(struct drm_device *dev,
struct drm_i915_gem_object *obj,
- bool pipelined)
+ struct intel_ring_buffer *pipelined)
{
u32 alignment;
int ret;
mutex_lock(&dev->struct_mutex);
ret = intel_pin_and_fence_fb_obj(dev,
to_intel_framebuffer(crtc->fb)->obj,
- false);
+ NULL);
if (ret != 0) {
mutex_unlock(&dev->struct_mutex);
return ret;
obj = intel_fb->obj;
mutex_lock(&dev->struct_mutex);
- ret = intel_pin_and_fence_fb_obj(dev, obj, true);
+ ret = intel_pin_and_fence_fb_obj(dev, obj, &dev_priv->render_ring);
if (ret)
goto cleanup_work;