drm/nouveau/fifo/gk104-: abstract mmu fault data structures

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index ddab2c82c6d539158cac803352629bb9ae28cbb5..67d440b374f057bdc6db4435b40d02535e4a2ab6 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -25,7 +25,6 @@
 #include "changk104.h"
 
 #include <core/client.h>
-#include <core/enum.h>
 #include <core/gpuobj.h>
 #include <subdev/bar.h>
 #include <subdev/top.h>
@@ -283,111 +282,6 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo)
        nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat);
 }
 
-static const struct nvkm_enum
-gk104_fifo_fault_engine[] = {
-       { 0x00, "GR", NULL, NVKM_ENGINE_GR },
-       { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
-       { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
-       { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
-       { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO },
-       { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO },
-       { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO },
-       { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
-       { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
-       { 0x13, "PERF" },
-       { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
-       { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
-       { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
-       { 0x17, "PMU" },
-       { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
-       { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
-       {}
-};
-
-static const struct nvkm_enum
-gk104_fifo_fault_reason[] = {
-       { 0x00, "PDE" },
-       { 0x01, "PDE_SIZE" },
-       { 0x02, "PTE" },
-       { 0x03, "VA_LIMIT_VIOLATION" },
-       { 0x04, "UNBOUND_INST_BLOCK" },
-       { 0x05, "PRIV_VIOLATION" },
-       { 0x06, "RO_VIOLATION" },
-       { 0x07, "WO_VIOLATION" },
-       { 0x08, "PITCH_MASK_VIOLATION" },
-       { 0x09, "WORK_CREATION" },
-       { 0x0a, "UNSUPPORTED_APERTURE" },
-       { 0x0b, "COMPRESSION_FAILURE" },
-       { 0x0c, "UNSUPPORTED_KIND" },
-       { 0x0d, "REGION_VIOLATION" },
-       { 0x0e, "BOTH_PTES_VALID" },
-       { 0x0f, "INFO_TYPE_POISONED" },
-       {}
-};
-
-static const struct nvkm_enum
-gk104_fifo_fault_hubclient[] = {
-       { 0x00, "VIP" },
-       { 0x01, "CE0" },
-       { 0x02, "CE1" },
-       { 0x03, "DNISO" },
-       { 0x04, "FE" },
-       { 0x05, "FECS" },
-       { 0x06, "HOST" },
-       { 0x07, "HOST_CPU" },
-       { 0x08, "HOST_CPU_NB" },
-       { 0x09, "ISO" },
-       { 0x0a, "MMU" },
-       { 0x0b, "MSPDEC" },
-       { 0x0c, "MSPPP" },
-       { 0x0d, "MSVLD" },
-       { 0x0e, "NISO" },
-       { 0x0f, "P2P" },
-       { 0x10, "PD" },
-       { 0x11, "PERF" },
-       { 0x12, "PMU" },
-       { 0x13, "RASTERTWOD" },
-       { 0x14, "SCC" },
-       { 0x15, "SCC_NB" },
-       { 0x16, "SEC" },
-       { 0x17, "SSYNC" },
-       { 0x18, "GR_CE" },
-       { 0x19, "CE2" },
-       { 0x1a, "XV" },
-       { 0x1b, "MMU_NB" },
-       { 0x1c, "MSENC" },
-       { 0x1d, "DFALCON" },
-       { 0x1e, "SKED" },
-       { 0x1f, "AFALCON" },
-       {}
-};
-
-static const struct nvkm_enum
-gk104_fifo_fault_gpcclient[] = {
-       { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
-       { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
-       { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
-       { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
-       { 0x0c, "RAST" },
-       { 0x0d, "GCC" },
-       { 0x0e, "GPCCS" },
-       { 0x0f, "PROP_0" },
-       { 0x10, "PROP_1" },
-       { 0x11, "PROP_2" },
-       { 0x12, "PROP_3" },
-       { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
-       { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
-       { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
-       { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
-       { 0x1f, "GPM" },
-       { 0x20, "LTP_UTLB_0" },
-       { 0x21, "LTP_UTLB_1" },
-       { 0x22, "LTP_UTLB_2" },
-       { 0x23, "LTP_UTLB_3" },
-       { 0x24, "GPC_RGG_UTLB" },
-       {}
-};
-
 static void
 gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
 {
@@ -408,12 +302,12 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
        unsigned long flags;
        char gpcid[8] = "";
 
-       er = nvkm_enum_find(gk104_fifo_fault_reason, reason);
-       eu = nvkm_enum_find(gk104_fifo_fault_engine, unit);
+       er = nvkm_enum_find(fifo->func->fault.reason, reason);
+       eu = nvkm_enum_find(fifo->func->fault.engine, unit);
        if (hub) {
-               ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client);
+               ec = nvkm_enum_find(fifo->func->fault.hubclient, client);
        } else {
-               ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client);
+               ec = nvkm_enum_find(fifo->func->fault.gpcclient, client);
                snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
        }
 
@@ -827,8 +721,117 @@ gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device,
        return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base);
 }
 
+const struct nvkm_enum
+gk104_fifo_fault_engine[] = {
+       { 0x00, "GR", NULL, NVKM_ENGINE_GR },
+       { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
+       { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
+       { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
+       { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO },
+       { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO },
+       { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO },
+       { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
+       { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
+       { 0x13, "PERF" },
+       { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
+       { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
+       { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
+       { 0x17, "PMU" },
+       { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
+       { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
+       {}
+};
+
+const struct nvkm_enum
+gk104_fifo_fault_reason[] = {
+       { 0x00, "PDE" },
+       { 0x01, "PDE_SIZE" },
+       { 0x02, "PTE" },
+       { 0x03, "VA_LIMIT_VIOLATION" },
+       { 0x04, "UNBOUND_INST_BLOCK" },
+       { 0x05, "PRIV_VIOLATION" },
+       { 0x06, "RO_VIOLATION" },
+       { 0x07, "WO_VIOLATION" },
+       { 0x08, "PITCH_MASK_VIOLATION" },
+       { 0x09, "WORK_CREATION" },
+       { 0x0a, "UNSUPPORTED_APERTURE" },
+       { 0x0b, "COMPRESSION_FAILURE" },
+       { 0x0c, "UNSUPPORTED_KIND" },
+       { 0x0d, "REGION_VIOLATION" },
+       { 0x0e, "BOTH_PTES_VALID" },
+       { 0x0f, "INFO_TYPE_POISONED" },
+       {}
+};
+
+const struct nvkm_enum
+gk104_fifo_fault_hubclient[] = {
+       { 0x00, "VIP" },
+       { 0x01, "CE0" },
+       { 0x02, "CE1" },
+       { 0x03, "DNISO" },
+       { 0x04, "FE" },
+       { 0x05, "FECS" },
+       { 0x06, "HOST" },
+       { 0x07, "HOST_CPU" },
+       { 0x08, "HOST_CPU_NB" },
+       { 0x09, "ISO" },
+       { 0x0a, "MMU" },
+       { 0x0b, "MSPDEC" },
+       { 0x0c, "MSPPP" },
+       { 0x0d, "MSVLD" },
+       { 0x0e, "NISO" },
+       { 0x0f, "P2P" },
+       { 0x10, "PD" },
+       { 0x11, "PERF" },
+       { 0x12, "PMU" },
+       { 0x13, "RASTERTWOD" },
+       { 0x14, "SCC" },
+       { 0x15, "SCC_NB" },
+       { 0x16, "SEC" },
+       { 0x17, "SSYNC" },
+       { 0x18, "GR_CE" },
+       { 0x19, "CE2" },
+       { 0x1a, "XV" },
+       { 0x1b, "MMU_NB" },
+       { 0x1c, "MSENC" },
+       { 0x1d, "DFALCON" },
+       { 0x1e, "SKED" },
+       { 0x1f, "AFALCON" },
+       {}
+};
+
+const struct nvkm_enum
+gk104_fifo_fault_gpcclient[] = {
+       { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
+       { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
+       { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
+       { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
+       { 0x0c, "RAST" },
+       { 0x0d, "GCC" },
+       { 0x0e, "GPCCS" },
+       { 0x0f, "PROP_0" },
+       { 0x10, "PROP_1" },
+       { 0x11, "PROP_2" },
+       { 0x12, "PROP_3" },
+       { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
+       { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
+       { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
+       { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
+       { 0x1f, "GPM" },
+       { 0x20, "LTP_UTLB_0" },
+       { 0x21, "LTP_UTLB_1" },
+       { 0x22, "LTP_UTLB_2" },
+       { 0x23, "LTP_UTLB_3" },
+       { 0x24, "GPC_RGG_UTLB" },
+       {}
+};
+
 static const struct gk104_fifo_func
 gk104_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gk104_fifo_gpfifo_oclass,
                NULL

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
index 703b437c5cc1c9ea3640c7fc1a7c37f51f5ef11a..e720402e728ab32d9f797cd424ac7876c296d83b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
@@ -3,6 +3,7 @@
 #define gk104_fifo(p) container_of((p), struct gk104_fifo, base)
 #include "priv.h"
 
+#include <core/enum.h>
 #include <subdev/mmu.h>
 
 struct gk104_fifo_chan;
@@ -41,7 +42,13 @@ struct gk104_fifo {
 };
 
 struct gk104_fifo_func {
-       int dummy;
+       struct {
+               const struct nvkm_enum *engine;
+               const struct nvkm_enum *reason;
+               const struct nvkm_enum *hubclient;
+               const struct nvkm_enum *gpcclient;
+       } fault;
+
        const struct nvkm_fifo_chan_oclass *chan[];
 };
 
@@ -69,4 +76,9 @@ gk104_fifo_engine_subdev(int engine)
                return 0;
        }
 }
+
+extern const struct nvkm_enum gk104_fifo_fault_engine[];
+extern const struct nvkm_enum gk104_fifo_fault_reason[];
+extern const struct nvkm_enum gk104_fifo_fault_hubclient[];
+extern const struct nvkm_enum gk104_fifo_fault_gpcclient[];
 #endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
index 061cf29a77c57f4e974e7f719290f2f8680c5374..b2f8ab7bf84711936618a804869bf0e49eb2bfcc 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
@@ -26,6 +26,10 @@
 
 static const struct gk104_fifo_func
 gk110_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gk110_fifo_gpfifo_oclass,
                NULL

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
index 6e0d0d700a4915396f0d56d910e0eeb135689feb..160617d376e4876c0f04628655118761ca8d3da2 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
@@ -26,6 +26,10 @@
 
 static const struct gk104_fifo_func
 gk208_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gk104_fifo_gpfifo_oclass,
                NULL

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
index dab911d4b292afad49253ce44c46ed9ff3722afb..be9f5c16ed7dd1e3aa1e168ac56bc940ebfd49e0 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
@@ -24,6 +24,10 @@
 
 static const struct gk104_fifo_func
 gk20a_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gk104_fifo_gpfifo_oclass,
                NULL

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
index ad9bb67476f28ac75dd1d46012813ede94e69548..39ab736b131002240705e9d257ae6075bba2727a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
@@ -26,6 +26,10 @@
 
 static const struct gk104_fifo_func
 gm107_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gk110_fifo_gpfifo_oclass,
                NULL

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
index 86cc11f0aa28b8fa07069741612b95717b3286af..bdfeb4049d0887d95135a9b6348f6bb23eb88c24 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
@@ -26,6 +26,10 @@
 
 static const struct gk104_fifo_func
 gm200_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gm200_fifo_gpfifo_oclass,
                NULL

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
index 1b288d7bc69879adabbc3db71137353fd624bce3..eea93f86a89980be7d70cad29e237f883eb9297b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
@@ -24,6 +24,10 @@
 
 static const struct gk104_fifo_func
 gm20b_fifo = {
+       .fault.engine = gk104_fifo_fault_engine,
+       .fault.reason = gk104_fifo_fault_reason,
+       .fault.hubclient = gk104_fifo_fault_hubclient,
+       .fault.gpcclient = gk104_fifo_fault_gpcclient,
        .chan = {
                &gm200_fifo_gpfifo_oclass,
                NULL