ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size

Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.

List of CPUs with cache line size != 32 should be expanded later.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index feaa75f0013eafcfcf5323954ade694bc40e343f..66c160b8547fdda1bc4e3f17f14c3229f1e0d940 100644 (file)
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -4,7 +4,7 @@
 #ifndef __ASMARM_CACHE_H
 #define __ASMARM_CACHE_H
 
-#define L1_CACHE_SHIFT         5
+#define L1_CACHE_SHIFT         CONFIG_ARM_L1_CACHE_SHIFT
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
 /*

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5fe595aeba6961f47d486a2959f237c375249790..8d43e58f9244349601d6001ec6332d6909634017 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -771,3 +771,8 @@ config CACHE_XSC3L2
        select OUTER_CACHE
        help
          This option enables the L2 cache on XScale3.
+
+config ARM_L1_CACHE_SHIFT
+       int
+       default 6 if ARCH_OMAP3
+       default 5