return 0;
}
+static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
+{
+ /* Mask all interrupts.*/
+ bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
+ bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
+ bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+ bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
+ bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
+ bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+}
+
static int init_umac(struct bcmgenet_priv *priv)
{
struct device *kdev = &priv->pdev->dev;
if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
- /* Mask all interrupts.*/
- bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
- bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
- bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+ bcmgenet_intr_disable(priv);
cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
}
+static void bcmgenet_netif_start(struct net_device *dev)
+{
+ struct bcmgenet_priv *priv = netdev_priv(dev);
+
+ /* Start the network engine */
+ napi_enable(&priv->napi);
+
+ umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
+
+ if (phy_is_internal(priv->phydev))
+ bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
+
+ netif_tx_start_all_queues(dev);
+
+ phy_start(priv->phydev);
+}
+
static int bcmgenet_open(struct net_device *dev)
{
struct bcmgenet_priv *priv = netdev_priv(dev);
/* disable ethernet MAC while updating its registers */
umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
+ /* Make sure we reflect the value of CRC_CMD_FWD */
+ reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+ priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
+
bcmgenet_set_hw_addr(priv, dev->dev_addr);
if (phy_is_internal(priv->phydev)) {
bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
}
+ device_set_wakeup_capable(&dev->dev, 1);
+
/* Disable RX/TX DMA and flush TX queues */
dma_ctrl = bcmgenet_dma_disable(priv);
goto err_irq0;
}
- /* Start the network engine */
- napi_enable(&priv->napi);
-
- umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
-
- /* Make sure we reflect the value of CRC_CMD_FWD */
- reg = bcmgenet_umac_readl(priv, UMAC_CMD);
- priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
-
- device_set_wakeup_capable(&dev->dev, 1);
-
- if (phy_is_internal(priv->phydev))
- bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
-
- netif_tx_start_all_queues(dev);
-
- phy_start(priv->phydev);
+ bcmgenet_netif_start(dev);
return 0;
return ret;
}
+static void bcmgenet_netif_stop(struct net_device *dev)
+{
+ struct bcmgenet_priv *priv = netdev_priv(dev);
+
+ netif_tx_stop_all_queues(dev);
+ napi_disable(&priv->napi);
+ phy_stop(priv->phydev);
+
+ bcmgenet_intr_disable(priv);
+
+ /* Wait for pending work items to complete. Since interrupts are
+ * disabled no new work will be scheduled.
+ */
+ cancel_work_sync(&priv->bcmgenet_irq_work);
+}
+
static int bcmgenet_close(struct net_device *dev)
{
struct bcmgenet_priv *priv = netdev_priv(dev);
netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
- phy_stop(priv->phydev);
+ bcmgenet_netif_stop(dev);
/* Disable MAC receive */
umac_enable_set(priv, CMD_RX_EN, false);
- netif_tx_stop_all_queues(dev);
-
ret = bcmgenet_dma_teardown(priv);
if (ret)
return ret;
/* Disable MAC transmit. TX DMA disabled have to done before this */
umac_enable_set(priv, CMD_TX_EN, false);
- napi_disable(&priv->napi);
-
/* tx reclaim */
bcmgenet_tx_reclaim_all(dev);
bcmgenet_fini_dma(priv);
free_irq(priv->irq0, priv);
free_irq(priv->irq1, priv);
- /* Wait for pending work items to complete - we are stopping
- * the clock now. Since interrupts are disabled, no new work
- * will be scheduled.
- */
- cancel_work_sync(&priv->bcmgenet_irq_work);
-
if (phy_is_internal(priv->phydev))
bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
return 0;
}
-
static struct platform_driver bcmgenet_driver = {
.probe = bcmgenet_probe,
.remove = bcmgenet_remove,