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clk: renesas: r8a7796: Add PCIe clocks
authorHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Wed, 19 Apr 2017 17:46:39 +0000 (02:46 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 May 2017 07:46:31 +0000 (09:46 +0200)
This patch adds PCIEC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a7796-cpg-mssr.c patch | blob | blame | history

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index ab8ad5e6f53771ce04e3701ccd326b981d18ae34..3ccd0551bbd6faa6f65c564c58b6ae4a14d02429 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -136,6 +136,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
        DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
        DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
+       DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
+       DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
        DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
        DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
        DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),