arm64: perf: Convert event enums to #defines

The enums are not necessary and this allows the event values to be
used to construct static strings at compile time.

Signed-off-by: Drew Richardson <drew.richardson@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 5b1897e8ca2476b20336658c65e3e19665bf0cdd..7e4372ee4dfb5e48b7c7ff91853840af9976dec3 100644 (file)
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -29,60 +29,55 @@
  * ARMv8 PMUv3 Performance Events handling code.
  * Common event types.
  */
-enum armv8_pmuv3_perf_types {
-       /* Required events. */
-       ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR                        = 0x00,
-       ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL                    = 0x03,
-       ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS                    = 0x04,
-       ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED                  = 0x10,
-       ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES                        = 0x11,
-       ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED                      = 0x12,
-
-       /* At least one of the following is required. */
-       ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED                      = 0x08,
-       ARMV8_PMUV3_PERFCTR_OP_SPEC                             = 0x1B,
-
-       /* Common architectural events. */
-       ARMV8_PMUV3_PERFCTR_MEM_READ                            = 0x06,
-       ARMV8_PMUV3_PERFCTR_MEM_WRITE                           = 0x07,
-       ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           = 0x09,
-       ARMV8_PMUV3_PERFCTR_EXC_EXECUTED                        = 0x0A,
-       ARMV8_PMUV3_PERFCTR_CID_WRITE                           = 0x0B,
-       ARMV8_PMUV3_PERFCTR_PC_WRITE                            = 0x0C,
-       ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH                       = 0x0D,
-       ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN                      = 0x0E,
-       ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS                = 0x0F,
-       ARMV8_PMUV3_PERFCTR_TTBR_WRITE                          = 0x1C,
-
-       /* Common microarchitectural events. */
-       ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL                    = 0x01,
-       ARMV8_PMUV3_PERFCTR_ITLB_REFILL                         = 0x02,
-       ARMV8_PMUV3_PERFCTR_DTLB_REFILL                         = 0x05,
-       ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          = 0x13,
-       ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS                    = 0x14,
-       ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB                        = 0x15,
-       ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS                     = 0x16,
-       ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL                     = 0x17,
-       ARMV8_PMUV3_PERFCTR_L2_CACHE_WB                         = 0x18,
-       ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          = 0x19,
-       ARMV8_PMUV3_PERFCTR_MEM_ERROR                           = 0x1A,
-       ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          = 0x1D,
-};
+
+/* Required events. */
+#define ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR                       0x00
+#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL                   0x03
+#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS                   0x04
+#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED                 0x10
+#define ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES                       0x11
+#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED                     0x12
+
+/* At least one of the following is required. */
+#define ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED                     0x08
+#define ARMV8_PMUV3_PERFCTR_OP_SPEC                            0x1B
+
+/* Common architectural events. */
+#define ARMV8_PMUV3_PERFCTR_MEM_READ                           0x06
+#define ARMV8_PMUV3_PERFCTR_MEM_WRITE                          0x07
+#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                          0x09
+#define ARMV8_PMUV3_PERFCTR_EXC_EXECUTED                       0x0A
+#define ARMV8_PMUV3_PERFCTR_CID_WRITE                          0x0B
+#define ARMV8_PMUV3_PERFCTR_PC_WRITE                           0x0C
+#define ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH                      0x0D
+#define ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN                     0x0E
+#define ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS               0x0F
+#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE                         0x1C
+
+/* Common microarchitectural events. */
+#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL                   0x01
+#define ARMV8_PMUV3_PERFCTR_ITLB_REFILL                                0x02
+#define ARMV8_PMUV3_PERFCTR_DTLB_REFILL                                0x05
+#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                         0x13
+#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS                   0x14
+#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB                       0x15
+#define ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS                    0x16
+#define ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL                    0x17
+#define ARMV8_PMUV3_PERFCTR_L2_CACHE_WB                                0x18
+#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                         0x19
+#define ARMV8_PMUV3_PERFCTR_MEM_ERROR                          0x1A
+#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                         0x1D
 
 /* ARMv8 Cortex-A53 specific event types. */
-enum armv8_a53_pmu_perf_types {
-       ARMV8_A53_PERFCTR_PREFETCH_LINEFILL                     = 0xC2,
-};
+#define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL                    0xC2
 
 /* ARMv8 Cortex-A57 specific event types. */
-enum armv8_a57_perf_types {
-       ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD                   = 0x40,
-       ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST                   = 0x41,
-       ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD                   = 0x42,
-       ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_ST                   = 0x43,
-       ARMV8_A57_PERFCTR_DTLB_REFILL_LD                        = 0x4c,
-       ARMV8_A57_PERFCTR_DTLB_REFILL_ST                        = 0x4d,
-};
+#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD                  0x40
+#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST                  0x41
+#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD                  0x42
+#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_ST                  0x43
+#define ARMV8_A57_PERFCTR_DTLB_REFILL_LD                       0x4c
+#define ARMV8_A57_PERFCTR_DTLB_REFILL_ST                       0x4d
 
 /* PMUv3 HW events mapping. */
 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {