drm/i915: use render gen to switch ring irq functions

Top-level interrupt bits are usually found in the display block. It
therefore makes sense to use HAS_PCH_SPLIT in i915_irq.c

But the irq stuff in intel_ring.c only concerns itself with render
core/gt-level interrupt sources. It therefore makes more sense to
switch based on gpu gen.

Kills a vlv special case.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 98ac5c0ca37ae14dab0ce96bcf72821d60f5e1c9..465a7da3b30d8ccc47198bd15e5aded113488abc 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -687,7 +687,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
 
        spin_lock(&ring->irq_lock);
        if (ring->irq_refcount++ == 0) {
-               if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+               if (INTEL_INFO(dev)->gen >= 5)
                        ironlake_enable_irq(dev_priv,
                                            GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
                else
@@ -706,7 +706,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
 
        spin_lock(&ring->irq_lock);
        if (--ring->irq_refcount == 0) {
-               if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+               if (INTEL_INFO(dev)->gen >= 5)
                        ironlake_disable_irq(dev_priv,
                                             GT_USER_INTERRUPT |
                                             GT_PIPE_NOTIFY);