ARM: dts: sh73a0: Add missing interrupt-affinity to PMU node

[ Upstream commit 57a66497e1b7486609250a482f05935eae5035e9 ]

The PMU node references two interrupts, but lacks the interrupt-affinity
property, which is required in that case:

    hw perfevents: no interrupt-affinity property for /pmu, guessing.

Add the missing property to fix this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 4ea5c5a16c57eed5235fc0f7365ce1a9d5e005f5..5fc24d4c2d5d4cbdc0dfce67440aefd5b5a4d8de 100644 (file)
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -22,7 +22,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
@@ -30,7 +30,7 @@
                        power-domains = <&pd_a2sl>;
                        next-level-cache = <&L2>;
                };
-               cpu@1 {
+               cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
@@ -89,6 +89,7 @@
                compatible = "arm,cortex-a9-pmu";
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
        };
 
        cmt1: timer@e6138000 {