# ifndef __ASSEMBLER__
#include <linux/clk/ti.h>
-extern void __iomem *cm_base;
-extern void __iomem *cm2_base;
+
+#include "prcm-common.h"
+
+extern struct omap_domain_base cm_base;
+extern struct omap_domain_base cm2_base;
extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
# endif
static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
{
- return readl_relaxed(cm_base + module + idx);
+ return readl_relaxed(cm_base.va + module + idx);
}
static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
- writel_relaxed(val, cm_base + module + idx);
+ writel_relaxed(val, cm_base.va + module + idx);
}
/* Read-modify-write a register in a CM module. Caller must lock */
/* Read a register in a CM instance */
static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
{
- return readl_relaxed(cm_base + inst + idx);
+ return readl_relaxed(cm_base.va + inst + idx);
}
/* Write into a register in a CM */
static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
{
- writel_relaxed(val, cm_base + inst + idx);
+ writel_relaxed(val, cm_base.va + inst + idx);
}
/* Read-modify-write a register in CM */
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
{
- omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
+ omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va +
+ OMAP3430_IVA2_MOD);
return cm_register(&omap3xxx_cm_ll_data);
}
static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
/* cm_base: base virtual address of the CM IP block */
-void __iomem *cm_base;
+struct omap_domain_base cm_base;
/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
-void __iomem *cm2_base;
+struct omap_domain_base cm2_base;
#define CM_NO_CLOCKS 0x1
#define CM_SINGLE_INSTANCE 0x2
*/
void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
{
- cm_base = cm;
- cm2_base = cm2;
+ cm_base.va = cm;
+ cm2_base.va = cm2;
}
/**
struct device_node *np;
const struct of_device_id *match;
struct omap_prcm_init_data *data;
- void __iomem *mem;
+ struct resource res;
+ int ret;
+ struct omap_domain_base *mem = NULL;
for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
data = (struct omap_prcm_init_data *)match->data;
- mem = of_iomap(np, 0);
- if (!mem)
- return -ENOMEM;
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
if (data->index == TI_CLKM_CM)
- cm_base = mem + data->offset;
+ mem = &cm_base;
if (data->index == TI_CLKM_CM2)
- cm2_base = mem + data->offset;
+ mem = &cm2_base;
+
+ data->mem = ioremap(res.start, resource_size(&res));
- data->mem = mem;
+ if (mem) {
+ mem->pa = res.start + data->offset;
+ mem->va = data->mem + data->offset;
+ }
data->np = np;
if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
- (cm_base && cm2_base)))
+ (cm_base.va && cm2_base.va)))
data->init(data);
}
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3
-static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+static struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
/**
* omap_cm_base_init - Populates the cm partitions
*/
static void omap_cm_base_init(void)
{
- _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
- _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
- _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
- _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+ memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base));
+ memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base));
+ memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base));
+ memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
+ sizeof(prcm_mpu_base));
}
/* Private functions */
{
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
- !_cm_bases[part]);
- return readl_relaxed(_cm_bases[part] + inst + idx);
+ !_cm_bases[part].va);
+ return readl_relaxed(_cm_bases[part].va + inst + idx);
}
/* Write into a register in a CM instance */
{
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
- !_cm_bases[part]);
- writel_relaxed(val, _cm_bases[part] + inst + idx);
+ !_cm_bases[part].va);
+ writel_relaxed(val, _cm_bases[part].va + inst + idx);
}
/* Read-modify-write a register in CM1. Caller must lock */
.priority = _priority \
}
+struct omap_domain_base {
+ u32 pa;
+ void __iomem *va;
+};
+
/**
* struct omap_prcm_init_data - PRCM driver init data
* @index: clock memory mapping index to be used
* @mem: IO mem pointer for this module
+ * @phys: IO mem physical base address for this module
* @offset: module base address offset from the IO base
* @flags: PRCM module init flags
* @device_inst_offset: device instance offset within the module address space
struct omap_prcm_init_data {
int index;
void __iomem *mem;
+ u32 phys;
s16 offset;
u16 flags;
s32 device_inst_offset;
* prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
* block registers
*/
-void __iomem *prcm_mpu_base;
+struct omap_domain_base prcm_mpu_base;
/* PRCM_MPU low-level functions */
*/
void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
{
- prcm_mpu_base = prcm_mpu;
+ prcm_mpu_base.va = prcm_mpu;
}
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
+#include "prcm-common.h"
+
+extern struct omap_domain_base prcm_mpu_base;
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
#include "prcm-common.h"
# ifndef __ASSEMBLER__
-extern void __iomem *prm_base;
+extern struct omap_domain_base prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int omap_prcm_init(void);
/* Power/reset management domain register get/set */
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
- return readl_relaxed(prm_base + module + idx);
+ return readl_relaxed(prm_base.va + module + idx);
}
static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
- writel_relaxed(val, prm_base + module + idx);
+ writel_relaxed(val, prm_base.va + module + idx);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
/* Read a register in a PRM instance */
static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
{
- return readl_relaxed(prm_base + inst + idx);
+ return readl_relaxed(prm_base.va + inst + idx);
}
/* Write into a register in a PRM instance */
static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
{
- writel_relaxed(val, prm_base + inst + idx);
+ writel_relaxed(val, prm_base.va + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
{
omap2_clk_legacy_provider_init(TI_CLKM_PRM,
- prm_base + OMAP3430_IVA2_MOD);
+ prm_base.va + OMAP3430_IVA2_MOD);
if (omap3_has_io_wakeup())
prm_features |= PRM_HAS_IO_WAKEUP;
/* Read a register in a CM/PRM instance in the PRM module */
static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
{
- return readl_relaxed(prm_base + inst + reg);
+ return readl_relaxed(prm_base.va + inst + reg);
}
/* Write into a register in a CM/PRM instance in the PRM module */
static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
{
- writel_relaxed(val, prm_base + inst + reg);
+ writel_relaxed(val, prm_base.va + inst + reg);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
static struct omap_prcm_irq_setup *prcm_irq_setup;
/* prm_base: base virtual address of the PRM IP block */
-void __iomem *prm_base;
+struct omap_domain_base prm_base;
u16 prm_features;
for (i = 0; i < irq_setup->nr_regs; i++) {
gc = irq_alloc_generic_chip("PRCM", 1,
- irq_setup->base_irq + i * 32, prm_base,
+ irq_setup->base_irq + i * 32, prm_base.va,
handle_level_irq);
if (!gc) {
*/
void __init omap2_set_globals_prm(void __iomem *prm)
{
- prm_base = prm;
+ prm_base.va = prm;
}
/**
struct device_node *np;
const struct of_device_id *match;
struct omap_prcm_init_data *data;
- void __iomem *mem;
+ struct resource res;
+ int ret;
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
data = (struct omap_prcm_init_data *)match->data;
- mem = of_iomap(np, 0);
- if (!mem)
- return -ENOMEM;
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
- if (data->index == TI_CLKM_PRM)
- prm_base = mem + data->offset;
+ data->mem = ioremap(res.start, resource_size(&res));
- data->mem = mem;
+ if (data->index == TI_CLKM_PRM) {
+ prm_base.va = data->mem + data->offset;
+ prm_base.pa = res.start + data->offset;
+ }
data->np = np;
#include "prcm_mpu44xx.h"
#include "soc.h"
-static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
*/
void omap_prm_base_init(void)
{
- _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
- _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+ memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
+ sizeof(prm_base));
+ memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
+ sizeof(prcm_mpu_base));
}
s32 omap4_prmst_get_prm_dev_inst(void)
{
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
- !_prm_bases[part]);
- return readl_relaxed(_prm_bases[part] + inst + idx);
+ !_prm_bases[part].va);
+ return readl_relaxed(_prm_bases[part].va + inst + idx);
}
/* Write into a register in a PRM instance */
{
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
- !_prm_bases[part]);
- writel_relaxed(val, _prm_bases[part] + inst + idx);
+ !_prm_bases[part].va);
+ writel_relaxed(val, _prm_bases[part].va + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff