drm/tegra: dc: Rename register for consistency
authorThierry Reding <treding@nvidia.com>
Mon, 27 Apr 2015 12:48:35 +0000 (14:48 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 13 Aug 2015 11:47:43 +0000 (13:47 +0200)
The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the
TRM. Modify the driver to use the same naming for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dc.h
drivers/gpu/drm/tegra/hdmi.c

index 5edae2653f09e65fcb7ff31b0fd21fde44caa7c6..87700bf601086666411ca51442b9a456d7b5447c 100644 (file)
 #define DC_COM_CRC_CHECKSUM_LATCHED            0x329
 
 #define DC_DISP_DISP_SIGNAL_OPTIONS0           0x400
-#define H_PULSE_0_ENABLE (1 <<  8)
-#define H_PULSE_1_ENABLE (1 << 10)
-#define H_PULSE_2_ENABLE (1 << 12)
+#define H_PULSE0_ENABLE (1 <<  8)
+#define H_PULSE1_ENABLE (1 << 10)
+#define H_PULSE2_ENABLE (1 << 12)
 
 #define DC_DISP_DISP_SIGNAL_OPTIONS1           0x401
 
index 06ab1783bba11e7b1299e3d950accf1547e20285..58f0cff65ff83a1eeadc9de62d806fd48ec9a145 100644 (file)
@@ -878,7 +878,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
        /* video_preamble uses h_pulse2 */
        pulse_start = 1 + h_sync_width + h_back_porch - 10;
 
-       tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
+       tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
 
        value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
                PULSE_LAST_END_A;