net: stmmac: prepare irq_status for mtl
authorJoao Pinto <Joao.Pinto@synopsys.com>
Fri, 10 Mar 2017 18:24:57 +0000 (18:24 +0000)
committerDavid S. Miller <davem@davemloft.net>
Mon, 13 Mar 2017 06:41:04 +0000 (23:41 -0700)
This patch prepares mac irq status treatment for multiple queues.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

index 7a175e9893d1fa388dbc8a30ccc646d84a138295..23c9e2a1bb6fd08917ac6edf9083340fd96e7842 100644 (file)
@@ -472,6 +472,8 @@ struct stmmac_ops {
        /* Handle extra events on specific interrupts hw dependent */
        int (*host_irq_status)(struct mac_device_info *hw,
                               struct stmmac_extra_stats *x);
+       /* Handle MTL interrupts */
+       int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
        /* Multicast filter setting */
        void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
        /* Flow control setting */
index 773f25b8e40399b3e3ed53c502150de475330e68..1ddf75c0eab5fe33517b39e4df9f1b806be53de2 100644 (file)
@@ -175,7 +175,7 @@ enum power_event {
 #define MTL_OPERATION_RAA_WSP          (0x1 << 2)
 
 #define MTL_INT_STATUS                 0x00000c20
-#define MTL_INT_Q0                     BIT(0)
+#define MTL_INT_QX(x)                  BIT(x)
 
 #define MTL_RXQ_DMA_MAP0               0x00000c30 /* queue 0 to 3 */
 #define MTL_RXQ_DMA_MAP1               0x00000c34 /* queue 4 to 7 */
index 3069defb7eb1530192dc348f01f4885d303ea121..f0f2dce79d099bf4ca0eaee6d6e10758ccef18f4 100644 (file)
@@ -416,11 +416,34 @@ static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
        }
 }
 
+static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
+{
+       void __iomem *ioaddr = hw->pcsr;
+       u32 mtl_int_qx_status;
+       int ret = 0;
+
+       mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
+
+       /* Check MTL Interrupt */
+       if (mtl_int_qx_status & MTL_INT_QX(chan)) {
+               /* read Queue x Interrupt status */
+               u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
+
+               if (status & MTL_RX_OVERFLOW_INT) {
+                       /*  clear Interrupt */
+                       writel(status | MTL_RX_OVERFLOW_INT,
+                              ioaddr + MTL_CHAN_INT_CTRL(chan));
+                       ret = CORE_IRQ_MTL_RX_OVERFLOW;
+               }
+       }
+
+       return ret;
+}
+
 static int dwmac4_irq_status(struct mac_device_info *hw,
                             struct stmmac_extra_stats *x)
 {
        void __iomem *ioaddr = hw->pcsr;
-       u32 mtl_int_qx_status;
        u32 intr_status;
        int ret = 0;
 
@@ -439,20 +462,6 @@ static int dwmac4_irq_status(struct mac_device_info *hw,
                x->irq_receive_pmt_irq_n++;
        }
 
-       mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
-       /* Check MTL Interrupt: Currently only one queue is used: Q0. */
-       if (mtl_int_qx_status & MTL_INT_Q0) {
-               /* read Queue 0 Interrupt status */
-               u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
-
-               if (status & MTL_RX_OVERFLOW_INT) {
-                       /*  clear Interrupt */
-                       writel(status | MTL_RX_OVERFLOW_INT,
-                              ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
-                       ret = CORE_IRQ_MTL_RX_OVERFLOW;
-               }
-       }
-
        dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
        if (intr_status & PCS_RGSMIIIS_IRQ)
                dwmac4_phystatus(ioaddr, x);
@@ -554,6 +563,7 @@ static const struct stmmac_ops dwmac4_ops = {
        .map_mtl_to_dma = dwmac4_map_mtl_dma,
        .dump_regs = dwmac4_dump_regs,
        .host_irq_status = dwmac4_irq_status,
+       .host_mtl_irq_status = dwmac4_irq_mtl_status,
        .flow_ctrl = dwmac4_flow_ctrl,
        .pmt = dwmac4_pmt,
        .set_umac_addr = dwmac4_set_umac_addr,
index f453fc5a2eda4c129f05da7c0d7981323977ac72..2449487be53461c9d31b85c15f4c034430cf156a 100644 (file)
@@ -2901,6 +2901,11 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
        if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
                int status = priv->hw->mac->host_irq_status(priv->hw,
                                                            &priv->xstats);
+
+               if (priv->synopsys_id >= DWMAC_CORE_4_00)
+                       status |= priv->hw->mac->host_mtl_irq_status(priv->hw,
+                                                               STMMAC_CHAN0);
+
                if (unlikely(status)) {
                        /* For LPI we need to save the tx status */
                        if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)