drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE

commit 25f09f858835b0e9a06213811031190a17d8ab78 upstream.

Recommended by the hw team.

Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b2eecfc9042e151b6fcb9d21069c766017510908..53186c5e1066b0cc269290df6c79324a57829824 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1534,25 +1534,6 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v9_0_init_compute_vmid(adev);
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       /*
-        * making sure that the following register writes will be broadcasted
-        * to all the shaders
-        */
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-
-       WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
-                  (adev->gfx.config.sc_prim_fifo_size_frontend <<
-                       PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
-                  (adev->gfx.config.sc_prim_fifo_size_backend <<
-                       PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
-                  (adev->gfx.config.sc_hiz_tile_fifo_size <<
-                       PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
-                  (adev->gfx.config.sc_earlyz_tile_fifo_size <<
-                       PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
-       mutex_unlock(&adev->grbm_idx_mutex);
-
 }
 
 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)