ARM: dts: AM43xx: clk: Add RNG clk node
authorLokesh Vutla <lokeshvutla@ti.com>
Wed, 1 Jun 2016 09:06:45 +0000 (12:06 +0300)
committerTony Lindgren <tony@atomide.com>
Wed, 22 Jun 2016 07:44:07 +0000 (00:44 -0700)
Add clk node for RNG module.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/am43xx-clocks.dtsi
drivers/clk/ti/clk-43xx.c

index 7630ba1d89e4fb6e306668526d7632a6bbcf345e..d1d73b725f4769952452f425148c30aed751e8c3 100644 (file)
                clock-div = <1>;
        };
 
+       rng_fck: rng_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
        ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
index 097fc90bf19ab2d241cee438dc272892f27d3acf..3f157a40bbd1a07d2577919f1ffd53f034f5d4e9 100644 (file)
@@ -58,6 +58,7 @@ static struct ti_dt_clk am43xx_clks[] = {
        DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
        DT_CLK(NULL, "sha0_fck", "sha0_fck"),
        DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+       DT_CLK(NULL, "rng_fck", "rng_fck"),
        DT_CLK(NULL, "timer1_fck", "timer1_fck"),
        DT_CLK(NULL, "timer2_fck", "timer2_fck"),
        DT_CLK(NULL, "timer3_fck", "timer3_fck"),