drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

v2:
- set the override disable flag too on stepping F0 (mika)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a071b1062e30b84ec10b6cbb883036e81ffde24e..6ab5765c30615cf2398c9bf01d6b455ce2cdb004 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 {
        struct drm_device *dev = ring->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
+       uint32_t tmp;
 
        /* WaDisablePartialInstShootdown:skl,bxt */
        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -967,6 +968,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
                WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
                                  PIXEL_MASK_CAMMING_DISABLE);
 
+       /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+       tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+       if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
+           (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
+               tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+       WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+
        return 0;
 }
 
@@ -1043,7 +1051,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
        struct drm_device *dev = ring->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       uint32_t tmp;
 
        gen9_init_workarounds(ring);
 
@@ -1058,12 +1065,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
                        GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
        }
 
-       /* WaForceContextSaveRestoreNonCoherent:bxt */
-       tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-       if (INTEL_REVID(dev) >= BXT_REVID_B0)
-               tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
-       WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
-
        return 0;
 }