drm/nv84/disp: move hdmi control into core
authorBen Skeggs <bskeggs@redhat.com>
Fri, 9 Nov 2012 00:54:38 +0000 (10:54 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 28 Nov 2012 23:57:51 +0000 (09:57 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
drivers/gpu/drm/nouveau/nouveau_hdmi.c

index 900707ef53c5e4c0be241bdd2d1dadbdc6c093e3..ae9151af9e083787609b21460babd9f0718ee9e2 100644 (file)
@@ -140,6 +140,8 @@ nouveau-y += core/engine/disp/nve0.o
 nouveau-y += core/engine/disp/dacnv50.o
 nouveau-y += core/engine/disp/hdanva3.o
 nouveau-y += core/engine/disp/hdanvd0.o
+nouveau-y += core/engine/disp/hdminv84.o
+nouveau-y += core/engine/disp/hdminva3.o
 nouveau-y += core/engine/disp/hdminvd0.o
 nouveau-y += core/engine/disp/sornv50.o
 nouveau-y += core/engine/disp/sornv94.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
new file mode 100644 (file)
index 0000000..0d36bdc
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/os.h>
+#include <core/class.h>
+
+#include "nv50.h"
+
+int
+nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
+{
+       const u32 hoff = (head * 0x800);
+
+       if (!(data & NV84_DISP_SOR_HDMI_PWR_STATE_ON)) {
+               nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000);
+               nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
+               nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
+               return 0;
+       }
+
+       /* AVI InfoFrame */
+       nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
+       nv_wr32(priv, 0x616528 + hoff, 0x000d0282);
+       nv_wr32(priv, 0x61652c + hoff, 0x0000006f);
+       nv_wr32(priv, 0x616530 + hoff, 0x00000000);
+       nv_wr32(priv, 0x616534 + hoff, 0x00000000);
+       nv_wr32(priv, 0x616538 + hoff, 0x00000000);
+       nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001);
+
+       /* Audio InfoFrame */
+       nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
+       nv_wr32(priv, 0x616508 + hoff, 0x000a0184);
+       nv_wr32(priv, 0x61650c + hoff, 0x00000071);
+       nv_wr32(priv, 0x616510 + hoff, 0x00000000);
+       nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
+
+       /* ??? */
+       nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
+       nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
+       nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
+
+       /* HDMI_CTRL */
+       nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, data | 0x1f000000 /* ??? */);
+       return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
new file mode 100644 (file)
index 0000000..f065fc2
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/os.h>
+#include <core/class.h>
+
+#include "nv50.h"
+
+int
+nva3_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
+{
+       const u32 soff = (or * 0x800);
+
+       if (!(data & NV84_DISP_SOR_HDMI_PWR_STATE_ON)) {
+               nv_mask(priv, 0x61c5a4 + soff, 0x40000000, 0x00000000);
+               nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000);
+               nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000);
+               return 0;
+       }
+
+       /* AVI InfoFrame */
+       nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000);
+       nv_wr32(priv, 0x61c528 + soff, 0x000d0282);
+       nv_wr32(priv, 0x61c52c + soff, 0x0000006f);
+       nv_wr32(priv, 0x61c530 + soff, 0x00000000);
+       nv_wr32(priv, 0x61c534 + soff, 0x00000000);
+       nv_wr32(priv, 0x61c538 + soff, 0x00000000);
+       nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000001);
+
+       /* Audio InfoFrame */
+       nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000);
+       nv_wr32(priv, 0x61c508 + soff, 0x000a0184);
+       nv_wr32(priv, 0x61c50c + soff, 0x00000071);
+       nv_wr32(priv, 0x61c510 + soff, 0x00000000);
+       nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001);
+
+       /* ??? */
+       nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
+       nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
+       nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
+
+       /* HDMI_CTRL */
+       nv_mask(priv, 0x61c5a4 + soff, 0x5f1f007f, data | 0x1f000000 /* ??? */);
+       return 0;
+}
index 08e06ae3407f13b9837766051bf3fcada8132e94..18aa5c0a67a0641a60107d086b5884c5255978f6 100644 (file)
@@ -49,6 +49,8 @@ int nv50_dac_sense(struct nv50_disp_priv *, int, u32);
 int nva3_hda_eld(struct nv50_disp_priv *, int, u8 *, u32);
 int nvd0_hda_eld(struct nv50_disp_priv *, int, u8 *, u32);
 
+int nv84_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
+int nva3_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
 int nvd0_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
 
 int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);
index 4a52cb7a718c5554299df8541abad6f0f21468bb..806e24a8c00ded18df6550ce3766ecbbf49e2562 100644 (file)
@@ -78,6 +78,7 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->dac.power = nv50_dac_power;
        priv->dac.sense = nv50_dac_sense;
        priv->sor.power = nv50_sor_power;
+       priv->sor.hdmi = nv84_hdmi_ctrl;
 
        INIT_LIST_HEAD(&priv->base.vblank.list);
        spin_lock_init(&priv->base.vblank.lock);
index 3f3cc838e537f079a29882fe9c06540c7f86b933..cde10e7568e3153d4ddebe84237129b83e1c8d7d 100644 (file)
@@ -84,6 +84,7 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->dac.power = nv50_dac_power;
        priv->dac.sense = nv50_dac_sense;
        priv->sor.power = nv50_sor_power;
+       priv->sor.hdmi = nv84_hdmi_ctrl;
        priv->sor.dp_train = nv94_sor_dp_train;
        priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
        priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
index 7f247580db3a425a5ffe74f558ccb2c304a778b5..5d63902cdeda857f820f3c7c714554bd41be2069 100644 (file)
@@ -69,6 +69,7 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->dac.power = nv50_dac_power;
        priv->dac.sense = nv50_dac_sense;
        priv->sor.power = nv50_sor_power;
+       priv->sor.hdmi = nv84_hdmi_ctrl;
 
        INIT_LIST_HEAD(&priv->base.vblank.list);
        spin_lock_init(&priv->base.vblank.lock);
index b2ffcd9186f9a3f326bb6020f2ce8eaf4ef296b7..a38ea93ebef6af6f3188871e8fc85601676501eb 100644 (file)
@@ -86,6 +86,7 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->dac.sense = nv50_dac_sense;
        priv->sor.power = nv50_sor_power;
        priv->sor.hda_eld = nva3_hda_eld;
+       priv->sor.hdmi = nva3_hdmi_ctrl;
        priv->sor.dp_train = nv94_sor_dp_train;
        priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
        priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
index 59b5f75ba4a3e6966ee0a05a320603ba422e9c5a..f730de3197954eb1d8faf2ccb07231b34f8b7c99 100644 (file)
@@ -43,38 +43,6 @@ hdmi_sor(struct drm_encoder *encoder)
        return true;
 }
 
-static inline u32
-hdmi_base(struct drm_encoder *encoder)
-{
-       struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
-       struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
-       if (!hdmi_sor(encoder))
-               return 0x616500 + (nv_crtc->index * 0x800);
-       return 0x61c500 + (nv_encoder->or * 0x800);
-}
-
-static void
-hdmi_wr32(struct drm_encoder *encoder, u32 reg, u32 val)
-{
-       struct nouveau_device *device = nouveau_dev(encoder->dev);
-       nv_wr32(device, hdmi_base(encoder) + reg, val);
-}
-
-static u32
-hdmi_rd32(struct drm_encoder *encoder, u32 reg)
-{
-       struct nouveau_device *device = nouveau_dev(encoder->dev);
-       return nv_rd32(device, hdmi_base(encoder) + reg);
-}
-
-static u32
-hdmi_mask(struct drm_encoder *encoder, u32 reg, u32 mask, u32 val)
-{
-       u32 tmp = hdmi_rd32(encoder, reg);
-       hdmi_wr32(encoder, reg, (tmp & ~mask) | val);
-       return tmp;
-}
-
 static void
 nouveau_audio_disconnect(struct drm_encoder *encoder)
 {
@@ -108,115 +76,27 @@ nouveau_audio_mode_set(struct drm_encoder *encoder,
        }
 }
 
-static void
-nouveau_hdmi_infoframe(struct drm_encoder *encoder, u32 ctrl, u8 *frame)
-{
-       /* calculate checksum for the infoframe */
-       u8 sum = 0, i;
-       for (i = 0; i < frame[2]; i++)
-               sum += frame[i];
-       frame[3] = 256 - sum;
-
-       /* disable infoframe, and write header */
-       hdmi_mask(encoder, ctrl + 0x00, 0x00000001, 0x00000000);
-       hdmi_wr32(encoder, ctrl + 0x08, *(u32 *)frame & 0xffffff);
-
-       /* register scans tell me the audio infoframe has only one set of
-        * subpack regs, according to tegra (gee nvidia, it'd be nice if we
-        * could get those docs too!), the hdmi block pads out the rest of
-        * the packet on its own.
-        */
-       if (ctrl == 0x020)
-               frame[2] = 6;
-
-       /* write out checksum and data, weird weird 7 byte register pairs */
-       for (i = 0; i < frame[2] + 1; i += 7) {
-               u32 rsubpack = ctrl + 0x0c + ((i / 7) * 8);
-               u32 *subpack = (u32 *)&frame[3 + i];
-               hdmi_wr32(encoder, rsubpack + 0, subpack[0]);
-               hdmi_wr32(encoder, rsubpack + 4, subpack[1] & 0xffffff);
-       }
-
-       /* enable the infoframe */
-       hdmi_mask(encoder, ctrl, 0x00000001, 0x00000001);
-}
-
-static void
-nouveau_hdmi_video_infoframe(struct drm_encoder *encoder,
-                            struct drm_display_mode *mode)
-{
-       const u8 Y = 0, A = 0, B = 0, S = 0, C = 0, M = 0, R = 0;
-       const u8 ITC = 0, EC = 0, Q = 0, SC = 0, VIC = 0, PR = 0;
-       const u8 bar_top = 0, bar_bottom = 0, bar_left = 0, bar_right = 0;
-       u8 frame[20];
-
-       frame[0x00] = 0x82; /* AVI infoframe */
-       frame[0x01] = 0x02; /* version */
-       frame[0x02] = 0x0d; /* length */
-       frame[0x03] = 0x00;
-       frame[0x04] = (Y << 5) | (A << 4) | (B << 2) | S;
-       frame[0x05] = (C << 6) | (M << 4) | R;
-       frame[0x06] = (ITC << 7) | (EC << 4) | (Q << 2) | SC;
-       frame[0x07] = VIC;
-       frame[0x08] = PR;
-       frame[0x09] = bar_top & 0xff;
-       frame[0x0a] = bar_top >> 8;
-       frame[0x0b] = bar_bottom & 0xff;
-       frame[0x0c] = bar_bottom >> 8;
-       frame[0x0d] = bar_left & 0xff;
-       frame[0x0e] = bar_left >> 8;
-       frame[0x0f] = bar_right & 0xff;
-       frame[0x10] = bar_right >> 8;
-       frame[0x11] = 0x00;
-       frame[0x12] = 0x00;
-       frame[0x13] = 0x00;
-
-       nouveau_hdmi_infoframe(encoder, 0x020, frame);
-}
-
-static void
-nouveau_hdmi_audio_infoframe(struct drm_encoder *encoder,
-                            struct drm_display_mode *mode)
-{
-       const u8 CT = 0x00, CC = 0x01, ceaSS = 0x00, SF = 0x00, FMT = 0x00;
-       const u8 CA = 0x00, DM_INH = 0, LSV = 0x00;
-       u8 frame[12];
-
-       frame[0x00] = 0x84;     /* Audio infoframe */
-       frame[0x01] = 0x01;     /* version */
-       frame[0x02] = 0x0a;     /* length */
-       frame[0x03] = 0x00;
-       frame[0x04] = (CT << 4) | CC;
-       frame[0x05] = (SF << 2) | ceaSS;
-       frame[0x06] = FMT;
-       frame[0x07] = CA;
-       frame[0x08] = (DM_INH << 7) | (LSV << 3);
-       frame[0x09] = 0x00;
-       frame[0x0a] = 0x00;
-       frame[0x0b] = 0x00;
-
-       nouveau_hdmi_infoframe(encoder, 0x000, frame);
-}
-
 static void
 nouveau_hdmi_disconnect(struct drm_encoder *encoder)
 {
-       nouveau_audio_disconnect(encoder);
+       struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+       struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
+       struct nv50_display *priv = nv50_display(encoder->dev);
+       const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
 
-       /* disable audio and avi infoframes */
-       hdmi_mask(encoder, 0x000, 0x00000001, 0x00000000);
-       hdmi_mask(encoder, 0x020, 0x00000001, 0x00000000);
+       nouveau_audio_disconnect(encoder);
 
-       /* disable hdmi */
-       hdmi_mask(encoder, 0x0a4, 0x40000000, 0x00000000);
+       nv_call(priv->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
 }
 
 void
 nouveau_hdmi_mode_set(struct drm_encoder *encoder,
                      struct drm_display_mode *mode)
 {
-       struct nouveau_device *device = nouveau_dev(encoder->dev);
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+       struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
+       struct nv50_display *priv = nv50_display(encoder->dev);
+       const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
        struct nouveau_connector *nv_connector;
        u32 max_ac_packet, rekey;
 
@@ -227,17 +107,6 @@ nouveau_hdmi_mode_set(struct drm_encoder *encoder,
                return;
        }
 
-       nouveau_hdmi_video_infoframe(encoder, mode);
-       nouveau_hdmi_audio_infoframe(encoder, mode);
-
-       hdmi_mask(encoder, 0x0d0, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
-       hdmi_mask(encoder, 0x068, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
-       hdmi_mask(encoder, 0x078, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
-
-       nv_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
-       nv_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
-       nv_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
-
        /* value matches nvidia binary driver, and tegra constant */
        rekey = 56;
 
@@ -246,11 +115,9 @@ nouveau_hdmi_mode_set(struct drm_encoder *encoder,
        max_ac_packet -= 18; /* constant from tegra */
        max_ac_packet /= 32;
 
-       /* enable hdmi */
-       hdmi_mask(encoder, 0x0a4, 0x5f1f003f, 0x40000000 | /* enable */
-                                             0x1f000000 | /* unknown */
-                                             max_ac_packet << 16 |
-                                             rekey);
+       nv_call(priv->core, NV84_DISP_SOR_HDMI_PWR + moff,
+                           NV84_DISP_SOR_HDMI_PWR_STATE_ON |
+                           (max_ac_packet << 16) | rekey);
 
        nouveau_audio_mode_set(encoder, mode);
 }