PCI: xgene: Add register accessors

Add device-specific register accessors for consistency across host drivers.
No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index f1481b2206f4ff0c0e25e6b9335899c0dc766e3e..1de23d74783f88d4a3dc59cd69810c172b7bf5cc 100644 (file)
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -76,6 +76,16 @@ struct xgene_pcie_port {
        u32                     version;
 };
 
+static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
+{
+       return readl(port->csr_base + reg);
+}
+
+static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
+{
+       writel(val, port->csr_base + reg);
+}
+
 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
 {
        return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
@@ -112,9 +122,9 @@ static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
        if (!pci_is_root_bus(bus))
                rtdid_val = (b << 8) | (d << 3) | f;
 
-       writel(rtdid_val, port->csr_base + RTDID);
+       xgene_pcie_writel(port, RTDID, rtdid_val);
        /* read the register back to ensure flush */
-       readl(port->csr_base + RTDID);
+       xgene_pcie_readl(port, RTDID);
 }
 
 /*
@@ -182,26 +192,25 @@ static struct pci_ops xgene_pcie_ops = {
 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
                                  u32 flags, u64 size)
 {
-       void __iomem *csr_base = port->csr_base;
        u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
        u32 val32 = 0;
        u32 val;
 
-       val32 = readl(csr_base + addr);
+       val32 = xgene_pcie_readl(port, addr);
        val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
-       writel(val, csr_base + addr);
+       xgene_pcie_writel(port, addr, val);
 
-       val32 = readl(csr_base + addr + 0x04);
+       val32 = xgene_pcie_readl(port, addr + 0x04);
        val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
-       writel(val, csr_base + addr + 0x04);
+       xgene_pcie_writel(port, addr + 0x04, val);
 
-       val32 = readl(csr_base + addr + 0x04);
+       val32 = xgene_pcie_readl(port, addr + 0x04);
        val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
-       writel(val, csr_base + addr + 0x04);
+       xgene_pcie_writel(port, addr + 0x04, val);
 
-       val32 = readl(csr_base + addr + 0x08);
+       val32 = xgene_pcie_readl(port, addr + 0x08);
        val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
-       writel(val, csr_base + addr + 0x08);
+       xgene_pcie_writel(port, addr + 0x08, val);
 
        return mask;
 }
@@ -209,15 +218,14 @@ static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
                                   u32 *lanes, u32 *speed)
 {
-       void __iomem *csr_base = port->csr_base;
        u32 val32;
 
        port->link_up = false;
-       val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
+       val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
        if (val32 & LINK_UP_MASK) {
                port->link_up = true;
                *speed = PIPE_PHY_RATE_RD(val32);
-               val32 = readl(csr_base + BRIDGE_STATUS_0);
+               val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
                *lanes = val32 >> 26;
        }
 }
@@ -266,7 +274,6 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
                                    struct resource *res, u32 offset,
                                    u64 cpu_addr, u64 pci_addr)
 {
-       void __iomem *base = port->csr_base + offset;
        struct device *dev = port->dev;
        resource_size_t size = resource_size(res);
        u64 restype = resource_type(res);
@@ -287,22 +294,21 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
                dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
                         (u64)size, min_size);
 
-       writel(lower_32_bits(cpu_addr), base);
-       writel(upper_32_bits(cpu_addr), base + 0x04);
-       writel(lower_32_bits(mask), base + 0x08);
-       writel(upper_32_bits(mask), base + 0x0c);
-       writel(lower_32_bits(pci_addr), base + 0x10);
-       writel(upper_32_bits(pci_addr), base + 0x14);
+       xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
+       xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
+       xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
+       xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
+       xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
+       xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
 }
 
 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
 {
-       void __iomem *csr_base = port->csr_base;
        u64 addr = port->cfg_addr;
 
-       writel(lower_32_bits(addr), csr_base + CFGBARL);
-       writel(upper_32_bits(addr), csr_base + CFGBARH);
-       writel(EN_REG, csr_base + CFGCTL);
+       xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
+       xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
+       xgene_pcie_writel(port, CFGCTL, EN_REG);
 }
 
 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
@@ -353,12 +359,11 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
                                  u64 pim, u64 size)
 {
-       void __iomem *addr = port->csr_base;
-
-       writel(lower_32_bits(pim), addr + pim_reg);
-       writel(upper_32_bits(pim) | EN_COHERENCY, addr + pim_reg + 0x04);
-       writel(lower_32_bits(size), addr + pim_reg + 0x10);
-       writel(upper_32_bits(size), addr + pim_reg + 0x14);
+       xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
+       xgene_pcie_writel(port, pim_reg + 0x04,
+                         upper_32_bits(pim) | EN_COHERENCY);
+       xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
+       xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
 }
 
 /*
@@ -388,7 +393,6 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
                                    struct of_pci_range *range, u8 *ib_reg_mask)
 {
-       void __iomem *csr_base = port->csr_base;
        void __iomem *cfg_base = port->cfg_base;
        struct device *dev = port->dev;
        void *bar_addr;
@@ -420,17 +424,15 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
                pim_reg = PIM1_1L;
                break;
        case 1:
-               bar_addr = csr_base + IBAR2;
-               writel(bar_low, bar_addr);
-               writel(lower_32_bits(mask), csr_base + IR2MSK);
+               xgene_pcie_writel(port, IBAR2, bar_low);
+               xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
                pim_reg = PIM2_1L;
                break;
        case 2:
-               bar_addr = csr_base + IBAR3L;
-               writel(bar_low, bar_addr);
-               writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
-               writel(lower_32_bits(mask), csr_base + IR3MSKL);
-               writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
+               xgene_pcie_writel(port, IBAR3L, bar_low);
+               xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
+               xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
+               xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
                pim_reg = PIM3_1L;
                break;
        }
@@ -486,7 +488,7 @@ static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
        int i;
 
        for (i = PIM1_1L; i <= CFGCTL; i += 4)
-               writel(0x0, port->csr_base + i);
+               xgene_pcie_writel(port, i, 0);
 }
 
 static int xgene_pcie_setup(struct xgene_pcie_port *port,
@@ -501,7 +503,7 @@ static int xgene_pcie_setup(struct xgene_pcie_port *port,
 
        /* setup the vendor and device IDs correctly */
        val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
-       writel(val, port->csr_base + BRIDGE_CFG_0);
+       xgene_pcie_writel(port, BRIDGE_CFG_0, val);
 
        ret = xgene_pcie_map_ranges(port, res, io_base);
        if (ret)