ixgbe: Fix SR-IOV VLAN pool configuration

The code for checking the PF bit in ixgbe_set_vf_vlan_msg was using the
wrong offset and as a result it was pulling the VLAN off of the PF even if
there were VFs numbered greater than 40 that still had the VLAN enabled.

Signed-off-by: Alexander Duyck <aduyck@mirantis.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
index 31de6cf7adb010c3e98ba72a5e8589756a86f90e..61a054ace56dc40feb93f7d739c35a8a5623a0b0 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
@@ -887,10 +887,10 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter,
                        bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2));
                        bits &= ~(1 << VMDQ_P(0));
                        bits |= IXGBE_READ_REG(hw,
-                                              IXGBE_VLVFB(reg_ndx * 2) + 1);
+                                              IXGBE_VLVFB(reg_ndx * 2 + 1));
                } else {
                        bits = IXGBE_READ_REG(hw,
-                                             IXGBE_VLVFB(reg_ndx * 2) + 1);
+                                             IXGBE_VLVFB(reg_ndx * 2 + 1));
                        bits &= ~(1 << (VMDQ_P(0) - 32));
                        bits |= IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2));
                }