ARM: dts: OMAP3+: add clock nodes for CPU
authorNishanth Menon <nm@ti.com>
Wed, 29 Jan 2014 18:19:17 +0000 (12:19 -0600)
committerTony Lindgren <tony@atomide.com>
Fri, 28 Feb 2014 23:04:28 +0000 (15:04 -0800)
OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.

OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
dpll_mpu clock.

Latency used is the generic latency defined in omap-cpufreq
driver.

Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/am33xx.dtsi
arch/arm/boot/dts/am4372.dtsi
arch/arm/boot/dts/dra7.dtsi
arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap4.dtsi
arch/arm/boot/dts/omap5.dtsi

index 3b605411ba057085b5f58480f11ccaa6c7b72029..d0ecefd75cc2f5426322a1a300203ee007e0fb57 100644 (file)
                                275000  1125000
                        >;
                        voltage-tolerance = <2>; /* 2 percentage */
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
index bcf77a870e675adc38bf85106b276300f934cef3..eb74ab82aa94005156880b347d1824d06a1d0fc5 100644 (file)
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <0>;
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
 
index bff4348f48fa10ac95ea066c59a7f0f38b267725..17f3b5adb7c20b6dd1344840122202b312c80f9c 100644 (file)
                                1000000 1060000
                                1176000 1160000
                                >;
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
                };
                cpu@1 {
                        device_type = "cpu";
index 1019b628f080b443c847c36c7d0ae8d5d34322aa..d3924198e5fd4c18ddfb4cdac234724878a92e67 100644 (file)
                        compatible = "arm,cortex-a8";
                        device_type = "cpu";
                        reg = <0x0>;
+
+                       clocks = <&dpll1_ck>;
+                       clock-names = "cpu";
+
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
 
index fd27392866d962b9d41712db670ad0bb6b8a85d3..89022378062083f05ec11c55b5e53edf2f12ff59 100644 (file)
                        device_type = "cpu";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
index 9ba5c18771729e5e6d9b4143791af7722ee0413b..f15c31cebc27a8e37d0b947c1f170cdc3d0fc42a 100644 (file)
                                1000000 1060000
                                1500000 1250000
                        >;
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
+
                        /* cooling options */
                        cooling-min-level = <0>;
                        cooling-max-level = <2>;