it8213/piix/slc90e66: remove {it8213,piix,slc90e66}_dma_2_pio()
authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Tue, 16 Oct 2007 20:29:54 +0000 (22:29 +0200)
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Tue, 16 Oct 2007 20:29:54 +0000 (22:29 +0200)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
drivers/ide/pci/it8213.c
drivers/ide/pci/piix.c
drivers/ide/pci/slc90e66.c

index ecf4ce078dce601863cf0d6cf18ff51e08cf9d71..6dab0daf4943c0e0fe6ad5e513e4312f058d59d1 100644 (file)
 
 #include <asm/io.h>
 
-/**
- *     it8213_dma_2_pio                -       return the PIO mode matching DMA
- *     @xfer_rate: transfer speed
- *
- *     Returns the nearest equivalent PIO timing for the DMA
- *     mode requested by the controller.
- */
-
-static u8 it8213_dma_2_pio (u8 xfer_rate) {
-       switch(xfer_rate) {
-               case XFER_UDMA_6:
-               case XFER_UDMA_5:
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-               case XFER_MW_DMA_2:
-                       return 4;
-               case XFER_MW_DMA_1:
-                       return 3;
-               case XFER_SW_DMA_2:
-                       return 2;
-               case XFER_MW_DMA_0:
-               case XFER_SW_DMA_1:
-               case XFER_SW_DMA_0:
-               default:
-                       return 0;
-       }
-}
-
 /**
  *     it8213_set_pio_mode     -       set host controller for PIO mode
  *     @drive: drive
@@ -124,7 +93,7 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
        int w_flag              = 0x10 << drive->dn;
        int u_speed             = 0;
        u16                     reg4042, reg4a;
-       u8                      reg48, reg54, reg55;
+       u8                      reg48, reg54, reg55, pio;
 
        pci_read_config_word(dev, maslave, &reg4042);
        pci_read_config_byte(dev, 0x48, &reg48);
@@ -165,7 +134,11 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
                                pci_write_config_byte(dev, 0x54, reg54 | v_flag);
                } else
                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
+
+               pio = 4;
        } else {
+               const u8 mwdma_to_pio[] = { 0, 3, 4 };
+
                if (reg48 & u_flag)
                        pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
                if (reg4a & a_speed)
@@ -174,9 +147,14 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
                if (reg55 & w_flag)
                        pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
+
+               if (speed >= XFER_MW_DMA_0)
+                       pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
+               else
+                       pio = 2; /* only SWDMA2 is allowed */
        }
 
-       it8213_set_pio_mode(drive, it8213_dma_2_pio(speed));
+       it8213_set_pio_mode(drive, pio);
 }
 
 /**
index 38c91ba6497b30252796f4020b5af9293535438b..4b397d6418489497133dbcb5aaf3afc4ba20596a 100644 (file)
 
 static int no_piix_dma;
 
-/**
- *     piix_dma_2_pio          -       return the PIO mode matching DMA
- *     @xfer_rate: transfer speed
- *
- *     Returns the nearest equivalent PIO timing for the DMA
- *     mode requested by the controller.
- */
-static u8 piix_dma_2_pio (u8 xfer_rate) {
-       switch(xfer_rate) {
-               case XFER_UDMA_6:
-               case XFER_UDMA_5:
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-               case XFER_MW_DMA_2:
-                       return 4;
-               case XFER_MW_DMA_1:
-                       return 3;
-               case XFER_SW_DMA_2:
-                       return 2;
-               case XFER_MW_DMA_0:
-               case XFER_SW_DMA_1:
-               case XFER_SW_DMA_0:
-               default:
-                       return 0;
-       }
-}
-
 /**
  *     piix_set_pio_mode       -       set host controller for PIO mode
  *     @drive: drive
@@ -225,7 +194,7 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
        int u_speed             = 0;
        int                     sitre;
        u16                     reg4042, reg4a;
-       u8                      reg48, reg54, reg55;
+       u8                      reg48, reg54, reg55, pio;
 
        pci_read_config_word(dev, maslave, &reg4042);
        sitre = (reg4042 & 0x4000) ? 1 : 0;
@@ -262,7 +231,11 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
                                pci_write_config_byte(dev, 0x54, reg54 | v_flag);
                } else
                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
+
+               pio = 4;
        } else {
+               const u8 mwdma_to_pio[] = { 0, 3, 4 };
+
                if (reg48 & u_flag)
                        pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
                if (reg4a & a_speed)
@@ -271,9 +244,14 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
                if (reg55 & w_flag)
                        pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
+
+               if (speed >= XFER_MW_DMA_0)
+                       pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
+               else
+                       pio = 2; /* only SWDMA2 is allowed */
        }
 
-       piix_set_pio_mode(drive, piix_dma_2_pio(speed));
+       piix_set_pio_mode(drive, pio);
 }
 
 /**
index 31cb0263dbd2bc9576402a615b7363ed4090499a..772b58671bb2ac0407904dedff1d81114a8cea28 100644 (file)
 
 #include <asm/io.h>
 
-static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
-       switch(xfer_rate) {
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-               case XFER_MW_DMA_2:
-                       return 4;
-               case XFER_MW_DMA_1:
-                       return 3;
-               case XFER_SW_DMA_2:
-                       return 2;
-               case XFER_MW_DMA_0:
-               case XFER_SW_DMA_1:
-               case XFER_SW_DMA_0:
-               default:
-                       return 0;
-       }
-}
-
 static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
 {
        ide_hwif_t *hwif        = HWIF(drive);
@@ -103,6 +82,7 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
        int sitre = 0, a_speed  = 7 << (drive->dn * 4);
        int u_speed = 0, u_flag = 1 << drive->dn;
        u16                     reg4042, reg44, reg48, reg4a;
+       u8                      pio;
 
        pci_read_config_word(dev, maslave, &reg4042);
        sitre = (reg4042 & 0x4000) ? 1 : 0;
@@ -131,14 +111,23 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
                        pci_read_config_word(dev, 0x4a, &reg4a);
                        pci_write_config_word(dev, 0x4a, reg4a|u_speed);
                }
+
+               pio = 4;
        } else {
+               const u8 mwdma_to_pio[] = { 0, 3, 4 };
+
                if (reg48 & u_flag)
                        pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
                if (reg4a & a_speed)
                        pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
+
+               if (speed >= XFER_MW_DMA_0)
+                       pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
+               else
+                       pio = 2; /* only SWDMA2 is allowed */
        }
 
-       slc90e66_set_pio_mode(drive, slc90e66_dma_2_pio(speed));
+       slc90e66_set_pio_mode(drive, pio);
 }
 
 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)