drm/i915: add new Haswell DIP controls registers

Haswell has different DIP control registers and offsets which we need to
use for infoframes, which this patch adds.

Note that this does not adds full DIP frames support, but only the basic
functionality necessary for HDMI to work in early enablement.

v2: replace infoframe handling with a debug message, proper support will
be added via a patch from Paulo Zanoni later.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a97db25cd348ef749907d62ee06c676f601e057..fb76b19e32b22e5aba18cc4e2ce5c2a99610a4ab 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3524,6 +3524,42 @@
 #define VLV_TVIDEO_DIP_GCP(pipe) \
        _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
 
+/* Haswell DIP controls */
+#define HSW_VIDEO_DIP_CTL_A            0x60200
+#define HSW_VIDEO_DIP_AVI_DATA_A       0x60220
+#define HSW_VIDEO_DIP_VS_DATA_A                0x60260
+#define HSW_VIDEO_DIP_SPD_DATA_A       0x602A0
+#define HSW_VIDEO_DIP_GMP_DATA_A       0x602E0
+#define HSW_VIDEO_DIP_VSC_DATA_A       0x60320
+#define HSW_VIDEO_DIP_AVI_ECC_A                0x60240
+#define HSW_VIDEO_DIP_VS_ECC_A         0x60280
+#define HSW_VIDEO_DIP_SPD_ECC_A                0x602C0
+#define HSW_VIDEO_DIP_GMP_ECC_A                0x60300
+#define HSW_VIDEO_DIP_VSC_ECC_A                0x60344
+#define HSW_VIDEO_DIP_GCP_A            0x60210
+
+#define HSW_VIDEO_DIP_CTL_B            0x61200
+#define HSW_VIDEO_DIP_AVI_DATA_B       0x61220
+#define HSW_VIDEO_DIP_VS_DATA_B                0x61260
+#define HSW_VIDEO_DIP_SPD_DATA_B       0x612A0
+#define HSW_VIDEO_DIP_GMP_DATA_B       0x612E0
+#define HSW_VIDEO_DIP_VSC_DATA_B       0x61320
+#define HSW_VIDEO_DIP_BVI_ECC_B                0x61240
+#define HSW_VIDEO_DIP_VS_ECC_B         0x61280
+#define HSW_VIDEO_DIP_SPD_ECC_B                0x612C0
+#define HSW_VIDEO_DIP_GMP_ECC_B                0x61300
+#define HSW_VIDEO_DIP_VSC_ECC_B                0x61344
+#define HSW_VIDEO_DIP_GCP_B            0x61210
+
+#define HSW_TVIDEO_DIP_CTL(pipe) \
+        _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
+#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
+        _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
+#define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
+        _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
+#define HSW_TVIDEO_DIP_GCP(pipe) \
+       _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
+
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
 #define _TRANS_HSYNC_B           0xe1008

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e240d99dbf92b532264a66b831b6f67328973fea..4a9d553719f6ed0c862714738685826ef61e2803 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -277,6 +277,18 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
        I915_WRITE(reg, val);
 }
 
+static void hsw_write_infoframe(struct drm_encoder *encoder,
+                                    struct dip_infoframe *frame)
+{
+       /* Not implemented yet, so avoid doing anything at all.
+        * This is the placeholder for Paulo Zanoni's infoframe writing patch
+        */
+       DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n");
+
+       return;
+
+}
+
 static void intel_set_infoframe(struct drm_encoder *encoder,
                                struct dip_infoframe *frame)
 {
@@ -660,6 +672,13 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
                intel_hdmi->write_infoframe = vlv_write_infoframe;
                for_each_pipe(i)
                        I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
+       } else if (IS_HASWELL(dev)) {
+               /* FIXME: Haswell has a new set of DIP frame registers, but we are
+                * just doing the minimal required for HDMI to work at this stage.
+                */
+               intel_hdmi->write_infoframe = hsw_write_infoframe;
+               for_each_pipe(i)
+                       I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
        } else if (HAS_PCH_IBX(dev)) {
                intel_hdmi->write_infoframe = ibx_write_infoframe;
                for_each_pipe(i)