perf_counter: Rename L2 to LL cache

The top (fastest) and last level (biggest) caches are the most
interesting ones, performance wise.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
[ Fixed the Nehalem LL table to LLC Reference/Miss events ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index 73956f084b295dd90fbda529fc9ecebff2d1babf..07bd308a5fa748247f3ea0472d5d973eb6576523 100644 (file)
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -561,7 +561,7 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                [C(OP_WRITE)] = {       -1,             -1      },
                [C(OP_PREFETCH)] = {    0,              0       },
        },
-       [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+       [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0,              0       },
                [C(OP_WRITE)] = {       0,              0       },
                [C(OP_PREFETCH)] = {    0xc34,          0       },

diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index 5f8b7741e970238744d632ad1a55df937a5b14d8..41e5d2d958d4c89a13df1840731dfd0b82eab49d 100644 (file)
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -632,7 +632,7 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                [C(OP_WRITE)] = {       -1,             -1              },
                [C(OP_PREFETCH)] = {    0,              0               },
        },
-       [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+       [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0,              0               },
                [C(OP_WRITE)] = {       0,              0               },
                [C(OP_PREFETCH)] = {    0xc50c3,        0               },

diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index d54723ab627dc71da637ac9a527b09c074234a9f..05600b66221ae0e491c9b947bfdbe649983ab18f 100644 (file)
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -574,7 +574,7 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                [C(OP_WRITE)] = {       -1,             -1              },
                [C(OP_PREFETCH)] = {    0,              0               },
        },
-       [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+       [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0,              0x3c309b        },
                [C(OP_WRITE)] = {       0,              0               },
                [C(OP_PREFETCH)] = {    0xc50c3,        0               },

diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index 0cd406ee765b63d53030c4d61f3e3e0ebc4927e8..46f74bebcfd92e8f30d4dc3187c1437baec22e76 100644 (file)
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -493,7 +493,7 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                [C(OP_WRITE)] = {       -1,             -1              },
                [C(OP_PREFETCH)] = {    0x4008c,        0               },
        },
-       [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+       [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0x150730,       0x250532        },
                [C(OP_WRITE)] = {       0x250432,       0x150432        },
                [C(OP_PREFETCH)] = {    0x810a6,        0               },

diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index 060e0deb399e6c16a4b71103b1fdc95ba9c04a27..b3f7d1216bae8b8299735a8e3b03f267ddafcd5d 100644 (file)
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -320,7 +320,7 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                [C(OP_WRITE)] = {       -1,             -1      },
                [C(OP_PREFETCH)] = {    0x408a,         0       },
        },
-       [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+       [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0x6080,         0x6084  },
                [C(OP_WRITE)] = {       0x6082,         0x6086  },
                [C(OP_PREFETCH)] = {    0,              0       },

diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index 46a20640942039962a91c4dd5fcef8678601a953..ba0a357a89f405f8e70d6cd7255928e40b906d86 100644 (file)
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -445,7 +445,7 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                [C(OP_WRITE)] = {       -1,             -1      },
                [C(OP_PREFETCH)] = {    0,              0       },
        },
-       [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+       [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
                [C(OP_READ)] = {        0,              0       },
                [C(OP_WRITE)] = {       0,              0       },
                [C(OP_PREFETCH)] = {    0x733,          0       },

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 572fb434a66633107d4ddec9db599ba964cb550d..895c82e78455036810b21302cf2bea49a40466a1 100644 (file)
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -131,7 +131,7 @@ static const u64 nehalem_hw_cache_event_ids
                [ C(RESULT_MISS)   ] = 0x0,
        },
  },
- [ C(L2  ) ] = {
+ [ C(LL  ) ] = {
        [ C(OP_READ) ] = {
                [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
                [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
@@ -141,8 +141,8 @@ static const u64 nehalem_hw_cache_event_ids
                [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
        },
        [ C(OP_PREFETCH) ] = {
-               [ C(RESULT_ACCESS) ] = 0xc024, /* L2_RQSTS.PREFETCHES          */
-               [ C(RESULT_MISS)   ] = 0x8024, /* L2_RQSTS.PREFETCH_MISS       */
+               [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
+               [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
        },
  },
  [ C(DTLB) ] = {
@@ -222,7 +222,7 @@ static const u64 core2_hw_cache_event_ids
                [ C(RESULT_MISS)   ] = 0,
        },
  },
- [ C(L2  ) ] = {
+ [ C(LL  ) ] = {
        [ C(OP_READ) ] = {
                [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
                [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
@@ -313,7 +313,7 @@ static const u64 atom_hw_cache_event_ids
                [ C(RESULT_MISS)   ] = 0,
        },
  },
- [ C(L2  ) ] = {
+ [ C(LL  ) ] = {
        [ C(OP_READ) ] = {
                [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
                [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
@@ -422,7 +422,7 @@ static const u64 amd_0f_hw_cache_event_ids
                [ C(RESULT_MISS)   ] = 0,
        },
  },
- [ C(L2  ) ] = {
+ [ C(LL  ) ] = {
        [ C(OP_READ) ] = {
                [ C(RESULT_ACCESS) ] = 0,
                [ C(RESULT_MISS)   ] = 0,

diff --git a/include/linux/perf_counter.h b/include/linux/perf_counter.h
index 887df88a9c2aef9101a84afc78df65d767aad5d5..20cf5af27ade7ce20886a791ed3b3be5d778c32e 100644 (file)
--- a/include/linux/perf_counter.h
+++ b/include/linux/perf_counter.h
@@ -56,14 +56,14 @@ enum perf_hw_id {
 /*
  * Generalized hardware cache counters:
  *
- *       { L1-D, L1-I, L2, LLC, ITLB, DTLB, BPU } x
+ *       { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x
  *       { read, write, prefetch } x
  *       { accesses, misses }
  */
 enum perf_hw_cache_id {
        PERF_COUNT_HW_CACHE_L1D         = 0,
        PERF_COUNT_HW_CACHE_L1I         = 1,
-       PERF_COUNT_HW_CACHE_L2          = 2,
+       PERF_COUNT_HW_CACHE_LL          = 2,
        PERF_COUNT_HW_CACHE_DTLB        = 3,
        PERF_COUNT_HW_CACHE_ITLB        = 4,
        PERF_COUNT_HW_CACHE_BPU         = 5,