net: stmmac: dwmac-rk: Add integrated PHY supprot for rk3328

There are two mac controllers in the rk3328, the one connects
to external PHY, and the other one connects to integrated PHY.
Like the mac of external PHY, the integrated PHY's mac also
needs to configure the related mac registers at GRF.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index b6db3ff38606d4212691f61bc09e4c40be8d634e..2176403c72d821f878d3f9bd310236982719d5d1 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -323,6 +323,8 @@ static const struct rk_gmac_ops rk3288_ops = {
 
 #define RK3328_GRF_MAC_CON0    0x0900
 #define RK3328_GRF_MAC_CON1    0x0904
+#define RK3328_GRF_MAC_CON2    0x0908
+#define RK3328_GRF_MACPHY_CON1 0xb04
 
 /* RK3328_GRF_MAC_CON0 */
 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
@@ -349,6 +351,9 @@ static const struct rk_gmac_ops rk3288_ops = {
 #define RK3328_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(1)
 #define RK3328_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(0)
 
+/* RK3328_GRF_MACPHY_CON1 */
+#define RK3328_MACPHY_RMII_MODE                GRF_BIT(9)
+
 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
                                int tx_delay, int rx_delay)
 {
@@ -373,13 +378,17 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 {
        struct device *dev = &bsp_priv->pdev->dev;
+       unsigned int reg;
 
        if (IS_ERR(bsp_priv->grf)) {
                dev_err(dev, "Missing rockchip,grf property\n");
                return;
        }
 
-       regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+       reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
+                 RK3328_GRF_MAC_CON1;
+
+       regmap_write(bsp_priv->grf, reg,
                     RK3328_GMAC_PHY_INTF_SEL_RMII |
                     RK3328_GMAC_RMII_MODE);
 }
@@ -409,29 +418,40 @@ static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 {
        struct device *dev = &bsp_priv->pdev->dev;
+       unsigned int reg;
 
        if (IS_ERR(bsp_priv->grf)) {
                dev_err(dev, "Missing rockchip,grf property\n");
                return;
        }
 
+       reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
+                 RK3328_GRF_MAC_CON1;
+
        if (speed == 10)
-               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+               regmap_write(bsp_priv->grf, reg,
                             RK3328_GMAC_RMII_CLK_2_5M |
                             RK3328_GMAC_SPEED_10M);
        else if (speed == 100)
-               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+               regmap_write(bsp_priv->grf, reg,
                             RK3328_GMAC_RMII_CLK_25M |
                             RK3328_GMAC_SPEED_100M);
        else
                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 }
 
+static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
+{
+       regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
+                    RK3328_MACPHY_RMII_MODE);
+}
+
 static const struct rk_gmac_ops rk3328_ops = {
        .set_to_rgmii = rk3328_set_to_rgmii,
        .set_to_rmii = rk3328_set_to_rmii,
        .set_rgmii_speed = rk3328_set_rgmii_speed,
        .set_rmii_speed = rk3328_set_rmii_speed,
+       .integrated_phy_powerup =  rk3328_integrated_phy_powerup,
 };
 
 #define RK3366_GRF_SOC_CON6    0x0418