pwm: mediatek: Disable clock on PWM configuration failure

Make sure to disable the PWM clock if the PWM cannot be configured due
to the clock divider exceeding the maximum value.

While at it, replace the hardcoded maximum clock divider with a defined
constant to improve code readability.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 6370459983180c6bbe5944653ca1b72fe3fe976a..b52f3afb2ba1f0f19f1241697ee7dcab92cc0057 100644 (file)
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -30,6 +30,8 @@
 #define PWMDWIDTH              0x2c
 #define PWMTHRES               0x30
 
+#define PWM_CLK_DIV_MAX                7
+
 enum {
        MTK_CLK_MAIN = 0,
        MTK_CLK_TOP,
@@ -130,8 +132,11 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
                clkdiv++;
        }
 
-       if (clkdiv > 7)
+       if (clkdiv > PWM_CLK_DIV_MAX) {
+               mtk_pwm_clk_disable(chip, pwm);
+               dev_err(chip->dev, "period %d not supported\n", period_ns);
                return -EINVAL;
+       }
 
        mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
        mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);