clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 4 Aug 2015 12:28:03 +0000 (14:28 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 12 Aug 2015 01:31:27 +0000 (10:31 +0900)
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
arch/arm/mach-shmobile/Kconfig
drivers/clk/shmobile/clk-r8a7778.c

index 2f3747fdcf1c53057be743af116a35d0f91833d6..e4cdaf1cb3333012c797039c8aec1c7638ac5646 100644 (file)
@@ -1,7 +1,9 @@
 * Renesas R8A7778 Clock Pulse Generator (CPG)
 
 The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 
@@ -10,10 +12,18 @@ Required Properties:
   - #clock-cells: Must be 1
   - clock-output-names: The names of the clocks. Supported clocks are
     "plla", "pllb", "b", "out", "p", "s", and "s1".
+  - #power-domain-cells: Must be 0
 
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
 
-Example
--------
+
+Examples
+--------
+
+  - CPG device node:
 
        cpg_clocks: cpg_clocks@ffc80000 {
                compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example
                clocks = <&extal_clk>;
                clock-output-names = "plla", "pllb", "b",
                                     "out", "p", "s", "s1";
+               #power-domain-cells = <0>;
+       };
+
+
+  - CPG/MSTP Clock Domain member device node:
+
+       sdhi0: sd@ffe4c000 {
+               compatible = "renesas,sdhi-r8a7778";
+               reg = <0xffe4c000 0x100>;
+               interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
        };
index 45006479d4617bf3b862eb98147323b216573dfd..e14fa5e87475a0d100ed25f3ed70dd44724f2159 100644 (file)
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
 
 config PM_RCAR
        bool
+       select PM_GENERIC_DOMAINS if PM
 
 config PM_RMOBILE
        bool
index cb33b57274bf9f55c016637bddd410610fc6dd26..fa45684e220c78ae542b32311ae76d1b9cbfc4b8 100644 (file)
@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
        }
 
        of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+       cpg_mstp_add_clk_domain(np);
 }
 
 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",