drm/radeon/dpm: implement force performance levels for 7xx/eg/btc
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 2 Jul 2013 22:40:35 +0000 (18:40 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 5 Jul 2013 22:09:30 +0000 (18:09 -0400)
Allows you to limit the selected power levels via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/btc_dpm.c
drivers/gpu/drm/radeon/cypress_dpm.c
drivers/gpu/drm/radeon/ppsmc.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/rv770_dpm.c
drivers/gpu/drm/radeon/rv770_dpm.h

index f072660c7665a6e1b653254527cf3075d9bfd112..91567448c55d446659a5a125bf13aa0377eadb59 100644 (file)
@@ -2326,9 +2326,9 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
                return ret;
        }
 
-       ret = rv770_unrestrict_performance_levels_after_switch(rdev);
+       ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
        if (ret) {
-               DRM_ERROR("rv770_unrestrict_performance_levels_after_switch failed\n");
+               DRM_ERROR("rv770_dpm_force_performance_level failed\n");
                return ret;
        }
 
index 5ada922e5cec8b566c430fc12690b4fc0dca3d13..9ef840807dd1e0ff73233ab3618a1d72b8de72fc 100644 (file)
@@ -2014,9 +2014,9 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev)
        if (eg_pi->pcie_performance_request)
                cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
 
-       ret = rv770_unrestrict_performance_levels_after_switch(rdev);
+       ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
        if (ret) {
-               DRM_ERROR("rv770_unrestrict_performance_levels_after_switch failed\n");
+               DRM_ERROR("rv770_dpm_force_performance_level failed\n");
                return ret;
        }
 
index 8fb1113a8fd7cb5fd8a5a7bbf47e026f6995d17c..fc71ca6b04cada2637239558d399203781722f71 100644 (file)
@@ -71,6 +71,8 @@ typedef uint8_t PPSMC_Result;
 #define PPSMC_MSG_SwitchToSwState           ((uint8_t)0x20)
 #define PPSMC_MSG_SwitchToInitialState      ((uint8_t)0x40)
 #define PPSMC_MSG_NoForcedLevel             ((uint8_t)0x41)
+#define PPSMC_MSG_ForceHigh                 ((uint8_t)0x42)
+#define PPSMC_MSG_ForceMediumOrHigh         ((uint8_t)0x43)
 #define PPSMC_MSG_SwitchToMinimumPower      ((uint8_t)0x51)
 #define PPSMC_MSG_ResumeFromMinimumPower    ((uint8_t)0x52)
 #define PPSMC_MSG_EnableCac                 ((uint8_t)0x53)
index a5b244dc50cae53cff2d0f7b88e2e2f382ff6721..221a0b31e649bd4a85d55aef97ec8e210fe592db 100644 (file)
@@ -1393,6 +1393,7 @@ static struct radeon_asic rv770_asic = {
                .get_mclk = &rv770_dpm_get_mclk,
                .print_power_state = &rv770_dpm_print_power_state,
                .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
+               .force_performance_level = &rv770_dpm_force_performance_level,
        },
        .pflip = {
                .pre_page_flip = &rs600_pre_page_flip,
@@ -1516,6 +1517,7 @@ static struct radeon_asic evergreen_asic = {
                .get_mclk = &rv770_dpm_get_mclk,
                .print_power_state = &rv770_dpm_print_power_state,
                .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
+               .force_performance_level = &rv770_dpm_force_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
@@ -1762,6 +1764,7 @@ static struct radeon_asic btc_asic = {
                .get_mclk = &btc_dpm_get_mclk,
                .print_power_state = &rv770_dpm_print_power_state,
                .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
+               .force_performance_level = &rv770_dpm_force_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
index 6822c7aeacaadd3e37c12413d67f35981917d613..a053dc1e78662c09da49b5787dba3ad48b2104d4 100644 (file)
@@ -478,6 +478,8 @@ void rv770_dpm_print_power_state(struct radeon_device *rdev,
                                 struct radeon_ps *ps);
 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
                                                       struct seq_file *m);
+int rv770_dpm_force_performance_level(struct radeon_device *rdev,
+                                     enum radeon_dpm_forced_level level);
 
 /*
  * evergreen
index 9af464d48eaa0a9d1da7789329547660794cea1d..c3025de4f4e2b59b204cf4699ac0ee2d0fdde9a7 100644 (file)
@@ -1471,14 +1471,30 @@ int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev)
        return 0;
 }
 
-int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev)
-{
-       if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_NoForcedLevel)) != PPSMC_Result_OK)
-               return -EINVAL;
+int rv770_dpm_force_performance_level(struct radeon_device *rdev,
+                                     enum radeon_dpm_forced_level level)
+{
+       PPSMC_Msg msg;
+
+       if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
+               if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ZeroLevelsDisabled) != PPSMC_Result_OK)
+                       return -EINVAL;
+               msg = PPSMC_MSG_ForceHigh;
+       } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
+               if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
+                       return -EINVAL;
+               msg = (PPSMC_Msg)(PPSMC_MSG_TwoLevelsDisabled);
+       } else {
+               if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
+                       return -EINVAL;
+               msg = (PPSMC_Msg)(PPSMC_MSG_ZeroLevelsDisabled);
+       }
 
-       if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_ZeroLevelsDisabled)) != PPSMC_Result_OK)
+       if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
                return -EINVAL;
 
+       rdev->pm.dpm.forced_level = level;
+
        return 0;
 }
 
@@ -2047,9 +2063,10 @@ int rv770_dpm_set_power_state(struct radeon_device *rdev)
        if (pi->dcodt)
                rv770_program_dcodt_after_state_switch(rdev, new_ps, old_ps);
        rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
-       ret = rv770_unrestrict_performance_levels_after_switch(rdev);
+
+       ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
        if (ret) {
-               DRM_ERROR("rv770_unrestrict_performance_levels_after_switch failed\n");
+               DRM_ERROR("rv770_dpm_force_performance_level failed\n");
                return ret;
        }
 
index f1e1fcf7f6224bd133ab40f5e5ab9bb5131fd67f..96b1b2a62a8a2a0d5950574788d0936aba6ec730 100644 (file)
@@ -262,7 +262,8 @@ void rv770_stop_dpm(struct radeon_device *rdev);
 void r7xx_stop_smc(struct radeon_device *rdev);
 void rv770_reset_smio_status(struct radeon_device *rdev);
 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
-int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev);
+int rv770_dpm_force_performance_level(struct radeon_device *rdev,
+                                     enum radeon_dpm_forced_level level);
 int rv770_halt_smc(struct radeon_device *rdev);
 int rv770_resume_smc(struct radeon_device *rdev);
 int rv770_set_sw_state(struct radeon_device *rdev);