ath9k_hw: Cleanup Tx calibrations for AR9003 chips
authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Thu, 13 Oct 2011 05:30:38 +0000 (11:00 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 14 Oct 2011 18:48:22 +0000 (14:48 -0400)
Currently Tx IQ calibration is enabled by default for all AR9003
chips. But for AR9480, the calibration status should be read from
chip after processing ini. And also the carrier leak calibration
status is checked during init cal. As the init_cal is being called
for fast channel change too, the tx_cl status only be read after
full reset. Hence moving that into process ini function.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_calib.c
drivers/net/wireless/ath/ath9k/ar9003_phy.c
drivers/net/wireless/ath/ath9k/ar9003_phy.h
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/hw.h

index 5f406382677ef9183ecf6dbbfb5d6c639e3b0454..3506e7bd36ebe5771da2252d1a27ce7f0d0b57e4 100644 (file)
@@ -906,15 +906,13 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
        struct ath_common *common = ath9k_hw_common(ah);
        struct ath9k_hw_cal_data *caldata = ah->caldata;
        bool txiqcal_done = false, txclcal_done = false;
-       bool is_reusable = true, txclcal_enabled;
+       bool is_reusable = true;
+       int i, j;
        u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
                                          AR_PHY_CL_TAB_1,
                                          AR_PHY_CL_TAB_2 };
 
-       txclcal_enabled = !!(REG_READ(ah, AR_PHY_CL_CAL_CTL) &
-                                     AR_PHY_CL_CAL_ENABLE);
-
-       if (txclcal_enabled) {
+       if (ah->enabled_cals & TX_CL_CAL) {
                if (caldata && caldata->done_txclcal_once)
                        REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
                                    AR_PHY_CL_CAL_ENABLE);
@@ -923,6 +921,9 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
                                    AR_PHY_CL_CAL_ENABLE);
        }
 
+       if (!(ah->enabled_cals & TX_IQ_CAL))
+               goto skip_tx_iqcal;
+
        /* Do Tx IQ Calibration */
        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
                      AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
@@ -932,7 +933,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
         * For AR9485 or later chips, TxIQ cal runs as part of
         * AGC calibration
         */
-       if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah)) {
+       if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
                if (caldata && !caldata->done_txiqcal_once)
                        REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
@@ -940,13 +941,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
                        REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
                txiqcal_done = true;
-       } else {
-               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
-               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-               udelay(5);
-               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+               goto skip_tx_iqcal;
        }
+       txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
+       REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+       udelay(5);
+       REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 
+skip_tx_iqcal:
        /* Calibrate the AGC */
        REG_WRITE(ah, AR_PHY_AGC_CONTROL,
                  REG_READ(ah, AR_PHY_AGC_CONTROL) |
@@ -966,8 +968,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
                ar9003_hw_tx_iq_cal_reload(ah);
 
 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
-       if (caldata && txclcal_enabled) {
-               int i, j;
+       if (caldata && (ah->enabled_cals & TX_CL_CAL)) {
                txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
                                           AR_PHY_AGC_CONTROL_CLC_SUCCESS);
                if (caldata->done_txclcal_once) {
index 4e31d655c4ea1babddd667e62022f29332d69900..f38307eb24b84b4f87b5289db676b83d44a431e9 100644 (file)
@@ -694,6 +694,19 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
        ath9k_hw_apply_txpower(ah, chan);
 
+       if (AR_SREV_9480(ah)) {
+               if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
+                               AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
+                       ah->enabled_cals |= TX_IQ_CAL;
+               else
+                       ah->enabled_cals &= ~TX_IQ_CAL;
+
+               if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
+                       ah->enabled_cals |= TX_CL_CAL;
+               else
+                       ah->enabled_cals &= ~TX_CL_CAL;
+       }
+
        return 0;
 }
 
index c6ed51fb6858f647735d84caf558bf724beafe39..ef90ab7dbd63be56252fce7f2a8c2bcd3cb42106 100644 (file)
 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR      0x00000004
 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL                   0x80000000
+#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S                         31
 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
 #define AR_PHY_TX_IQCAL_START_DO_CAL       0x00000001
index 0aa05841b2636f95bcce870b6a31c76cc6fe08f0..88bbdc46fd88bd13c8866368077959b2d9acd15d 100644 (file)
@@ -2315,6 +2315,11 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                rx_chainmask >>= 1;
        }
 
+       if (AR_SREV_9300_20_OR_LATER(ah)) {
+               ah->enabled_cals |= TX_IQ_CAL;
+               if (!AR_SREV_9330(ah))
+                       ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
+       }
        return 0;
 }
 
index 446f4d309beca29d42531ec104a7e046188be866..75982a7ebcc0a789f5d32f7e01a9b28db34ee5c8 100644 (file)
@@ -634,6 +634,12 @@ struct ath_nf_limits {
        s16 nominal;
 };
 
+enum ath_cal_list {
+       TX_IQ_CAL         =     BIT(0),
+       TX_IQ_ON_AGC_CAL  =     BIT(1),
+       TX_CL_CAL         =     BIT(2),
+};
+
 /* ah_flags */
 #define AH_USE_EEPROM   0x1
 #define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
@@ -733,6 +739,7 @@ struct ath_hw {
                int32_t sign[AR5416_MAX_CHAINS];
        } meas3;
        u16 cal_samples;
+       u8 enabled_cals;
 
        u32 sta_id1_defaults;
        u32 misc_mode;