media: mfc: support HEVC 422 10, VP9 version3 profile

Change-Id: I773b7638faf86cf67477c191e2900da3b70becf3
Signed-off-by: Ayoung Sim <a.sim@samsung.com>

diff --git a/drivers/media/platform/exynos/mfc/s5p_mfc_buf.c b/drivers/media/platform/exynos/mfc/s5p_mfc_buf.c
index 75de9c69edb8299381881c1c219a628e2a2d8029..2a8bb348d12dbd6b810cc7704d1b61aa4c5f8693 100644 (file)
--- a/drivers/media/platform/exynos/mfc/s5p_mfc_buf.c
+++ b/drivers/media/platform/exynos/mfc/s5p_mfc_buf.c
@@ -335,7 +335,7 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx)
                        enc->chroma_dpb_size + enc->me_buffer_size));
                break;
        case S5P_FIMV_CODEC_VP9_ENC:
-               if (ctx->is_10bit) {
+               if (ctx->is_10bit || ctx->is_422format) {
                        enc->luma_dpb_size =
                                ALIGN(ENC_VP9_LUMA_DPB_10B_SIZE(ctx->img_width, ctx->img_height), 64);
                        enc->chroma_dpb_size =

diff --git a/drivers/media/platform/exynos/mfc/s5p_mfc_common.h b/drivers/media/platform/exynos/mfc/s5p_mfc_common.h
index 750a231c53d98f1e293725db5fff6e255fd7a102..ec4fc1c4ca0b558c365142e23181374ccacb8302 100644 (file)
--- a/drivers/media/platform/exynos/mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/exynos/mfc/s5p_mfc_common.h
@@ -133,6 +133,7 @@
                                IS_VP9_DEC(ctx) || IS_VP9_ENC(ctx) ||           \
                                IS_BPG_DEC(ctx) || IS_BPG_ENC(ctx))
 #define CODEC_422FORMAT(ctx)   (IS_HEVC_DEC(ctx) || IS_HEVC_ENC(ctx) ||        \
+                               IS_VP9_DEC(ctx) || IS_VP9_ENC(ctx) ||           \
                                IS_BPG_DEC(ctx) || IS_BPG_ENC(ctx))
 #define ON_RES_CHANGE(ctx)     (((ctx)->state >= MFCINST_RES_CHANGE_INIT) &&   \
                                 ((ctx)->state <= MFCINST_RES_CHANGE_END))

diff --git a/drivers/media/platform/exynos/mfc/s5p_mfc_enc_internal.h b/drivers/media/platform/exynos/mfc/s5p_mfc_enc_internal.h
index 75ddf6fc12718cfe5f264696dedc198769b8ae16..c337e23cf10367f39b77a0441b9303ee2158b1b3 100644 (file)
--- a/drivers/media/platform/exynos/mfc/s5p_mfc_enc_internal.h
+++ b/drivers/media/platform/exynos/mfc/s5p_mfc_enc_internal.h
@@ -1099,7 +1099,7 @@ static struct v4l2_queryctrl controls[] = {
                .type = V4L2_CTRL_TYPE_INTEGER,
                .name = "VP9 version",
                .minimum = 0,
-               .maximum = 0,
+               .maximum = 3,
                .step = 1,
                .default_value = 0,
        },
@@ -1315,7 +1315,7 @@ static struct v4l2_queryctrl controls[] = {
                .type = V4L2_CTRL_TYPE_BOOLEAN,
                .name = "HEVC Profile",
                .minimum = 0,
-               .maximum = 2,
+               .maximum = 4,
                .step = 1,
                .default_value = 0,
        },

diff --git a/drivers/media/platform/exynos/mfc/s5p_mfc_enc_param.c b/drivers/media/platform/exynos/mfc/s5p_mfc_enc_param.c
index 088025d8290837325ed9926beb6af83ec817cdcd..e7e3c45853d542a7b2089ab8f6fc3d3c7ecaf0db 100644 (file)
--- a/drivers/media/platform/exynos/mfc/s5p_mfc_enc_param.c
+++ b/drivers/media/platform/exynos/mfc/s5p_mfc_enc_param.c
@@ -988,17 +988,31 @@ void s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
 
        /* profile*/
        reg = 0;
-       reg |= (p_vp9->vp9_version) ;
+       reg |= p_vp9->vp9_version;
        /* bit depth minus8 */
        if (ctx->is_10bit) {
                reg &= ~(0x3F << 17);
                reg |= (0x2 << 17);
                reg |= (0x2 << 20);
-               /* fixed profile */
-               reg |= 0x2;
        }
        MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE);
 
+       /* for only information about wrong setting */
+       if (ctx->is_422format) {
+               if ((p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE1) &&
+                       (p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE3)) {
+                       mfc_err_ctx("4:2:2 format is not matched with profile(%d)\n",
+                                       p_vp9->vp9_version);
+               }
+       }
+       if (ctx->is_10bit) {
+               if ((p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE2) &&
+                       (p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE3)) {
+                       mfc_err_ctx("10bit format is not matched with profile(%d)\n",
+                                       p_vp9->vp9_version);
+               }
+       }
+
        reg = MFC_READL(S5P_FIMV_E_VP9_OPTION);
        /* if num_refs_for_p is 2, the performance falls by half */
        reg &= ~(0x1);
@@ -1140,7 +1154,7 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
        /* tier_flag & level & profile */
        reg = 0;
        /* profile */
-       reg |= p_hevc->profile & 0x3;
+       reg |= p_hevc->profile & 0xf;
        /* level */
        reg &= ~(0xFF << 8);
        reg |= (p_hevc->level << 8);
@@ -1151,14 +1165,26 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
                reg &= ~(0x3F << 17);
                reg |= (0x2 << 17);
                reg |= (0x2 << 20);
-               /* fixed profile */
-               if (ctx->is_422format)
-                       reg |= 0x2;
-               else
-                       reg |= 0x3;
        }
        MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE);
 
+       /* for only information about wrong setting */
+       if (ctx->is_422format) {
+               if ((p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10_INTRA) &&
+                       (p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10)) {
+                       mfc_err_ctx("4:2:2 format is not matched with profile(%d)\n",
+                                       p_hevc->profile);
+               }
+       }
+       if (ctx->is_10bit) {
+               if ((p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10_INTRA) &&
+                       (p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_10) &&
+                       (p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10)) {
+                       mfc_err_ctx("10bit format is not matched with profile(%d)\n",
+                                       p_hevc->profile);
+               }
+       }
+
        /* max partition depth */
        reg = MFC_READL(S5P_FIMV_E_HEVC_OPTIONS);
        reg &= ~(0x3);

diff --git a/drivers/media/platform/exynos/mfc/s5p_mfc_macros.h b/drivers/media/platform/exynos/mfc/s5p_mfc_macros.h
index 7ab2085e24609d9e042c69202c8dfbeafa24512e..cf0bb5acd0c671dbeecf4294030c39764d3ecc8c 100644 (file)
--- a/drivers/media/platform/exynos/mfc/s5p_mfc_macros.h
+++ b/drivers/media/platform/exynos/mfc/s5p_mfc_macros.h
@@ -45,11 +45,11 @@
        (((((ENC_LCU_WIDTH(x) * 32 + 3) / 4) + 15) / 16) * 16) *        \
        ((y + 31) / 32 ) * 32 + 64
 #define ENC_VP9_LUMA_DPB_10B_SIZE(x, y)                                        \
-       (((x * 2 + 128) / 128) * 128) *                                 \
+       (((x * 2 + 127) / 128) * 128) *                                 \
        ((y + 31) / 32 ) * 32 + 64
 #define ENC_VP9_CHROMA_DPB_10B_SIZE(x, y)                              \
-       (((x * 2 + 128) / 128) * 128) *                                 \
-       ((((y + 31) / 32 ) * 32) / 2) + 64
+       (((x * 2 + 127) / 128) * 128) *                                 \
+       ((y + 31) / 32 ) * 32 + 64
 #define ENC_LUMA_DPB_SIZE(x, y)                                                \
        ((x + 63) / 64) * 64 * ((y + 31) / 32 ) * 32 + 64
 #define ENC_CHROMA_DPB_SIZE(x, y)                                      \

diff --git a/drivers/media/platform/exynos/mfc/s5p_mfc_regs_v10.h b/drivers/media/platform/exynos/mfc/s5p_mfc_regs_v10.h
index 02997c3b48cc531be4bba05d84e4edf80bc8c4f5..45a9ae2847105181c563f06f25ed4d666f01da55 100644 (file)
--- a/drivers/media/platform/exynos/mfc/s5p_mfc_regs_v10.h
+++ b/drivers/media/platform/exynos/mfc/s5p_mfc_regs_v10.h
@@ -710,7 +710,13 @@
 #define S5P_FIMV_E_PROFILE_H264_CONSTRAINED_HIGH       5
 #define S5P_FIMV_E_PROFILE_MPEG4_SIMPLE                        0
 #define S5P_FIMV_E_PROFILE_MPEG4_ADVANCED_SIMPLE       1
-#define S5P_FIMV_E_PROFILE_HEVC_422_10_INTRA           2
+#define S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10_INTRA      2
+#define S5P_FIMV_E_PROFILE_HEVC_MAIN_10                        3
+#define S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10            4
+#define S5P_FIMV_E_PROFILE_VP9_PROFILE0                        0
+#define S5P_FIMV_E_PROFILE_VP9_PROFILE1                        1
+#define S5P_FIMV_E_PROFILE_VP9_PROFILE2                        2
+#define S5P_FIMV_E_PROFILE_VP9_PROFILE3                        3
 
 
 /* 0xF7A4: S5P_FIMV_E_RC_MODE */